SA Article Coverage Review · 2026-02-25_vera-rubin-extreme-co-design-an-evolution
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Coverage Summary
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235 - Blocks without Atomic Claim:
168 - Unplaced Claims:
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Coverage Review
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SA Full Text + Translation + Atomic Claims
Vera Rubin – Extreme Co-Design: An Evolution from Grace Blackwell Oberon
Vera, Rubin, NVLink 6 Switch, ConnectX-9, BlueField-4, Spectrum-6, Seamless Cableless Compute Tray Design, Power Rack, VR NVL72 TCO and BoM
At CES 2026, Nvidia officially announced in detail all 6 Rubin platform products: the Rubin GPU, Vera CPU, NVLink 6 Switch, ConnectX-9, BlueField-4, and Spectrum-6. VR NVL72 is the second generation of Nvidia’s rack scale Oberon architecture that takes the stage. With competition catching up on rack scale game, Trainium 3 in the Gen2 UltraServer, AMD MI450X Helios Racks, and Google’s TPU which was at rack scale even before GB200, Nvidia answers with “extreme co-design” supremacy. With extreme co-design, Nvidia takes rack scale integration to the next level. Rack system becomes a unit of compute, a single distributed accelerator, and Nvidia designs the system.
Atomic Claim 1/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0002
Claim: Nvidia 發布 Vera CPU。
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Atomic Claim 2/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT01
Claim: 在 CES 2026，Nvidia 正式詳細介紹 Rubin GPU，將其列為 Rubin 平台六大產品之一。
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Atomic Claim 3/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT03
Claim: 在 CES 2026，Nvidia 正式詳細介紹 NVLink 6 Switch，將其列為 Rubin 平台六大產品之一。
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Atomic Claim 4/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT04
Claim: 在 CES 2026，Nvidia 正式詳細介紹 ConnectX-9，將其列為 Rubin 平台六大產品之一。
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Atomic Claim 5/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT05
Claim: 在 CES 2026，Nvidia 正式詳細介紹 BlueField-4，將其列為 Rubin 平台六大產品之一。
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Atomic Claim 6/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT06
Claim: 在 CES 2026，Nvidia 正式詳細介紹 Spectrum-6，將其列為 Rubin 平台六大產品之一。
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Atomic Claim 7/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0002
Claim: VR NVL72 是 Nvidia rack-scale Oberon architecture 的第二代。
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Atomic Claim 8/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0003::SPLIT01
Claim: Trainium 3 部署於 Gen2 UltraServer，作為機櫃級競爭方案。
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Atomic Claim 9/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0003::SPLIT02
Claim: AMD MI450X Helios Racks 是機櫃級競爭方案。
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Atomic Claim 10/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0003::SPLIT03
Claim: Google TPU 早在 GB200 之前就已達到機櫃級規模。
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Atomic Claim 11/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0003::SPLIT04
Claim: Nvidia 以極致協同設計回應逐漸追上的機櫃級競爭。
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Atomic Claim 12/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0004
Claim: 透過 extreme co-design，Nvidia 將 rack-scale integration 推進到更高層級。
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Atomic Claim 13/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0005
Claim: 關於 Rubin：Rack system 被視為一個 compute unit，也就是單一 distributed accelerator。
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Atomic Claim 14/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0006
Claim: Nvidia 負責設計整個 system。
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Source: Nvidia
For the Vera Rubin platform, Nvidia is asserting even more control over the system and rack level design. Rack scale integration and assembly have become more challenging, as every component is being pushed to the limit, whilst also optimizing for cost efficiency. VR NVL72 has a much more holistic design with a modular approach compared to Grace Blackwell for the purpose of integration efficiency and throughput.
Atomic Claim 15/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0007
Claim: 對 Vera Rubin platform，Nvidia 對 system 與 rack-level design 掌握更多控制權。
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Atomic Claim 16/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0008
Claim: Vera Rubin 的元件被推向極限，同時還必須最佳化成本效率，使機櫃級整合與組裝更具挑戰。
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Atomic Claim 17/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0009
Claim: 為提升 integration efficiency 與 throughput，VR NVL72 相較 Grace Blackwell 採用更 holistic、modular 的設計方式。
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Nvidia’s competitiveness strengthens with its extreme co-design supremacy. It is the only player with the best in class or close to the best in class silicon product offerings for all the major silicon contents in an Nvidia trail-blazed AI server system design. Nvidia offers the best accelerator, a SOTA scale up switch, the best NIC, and one of the best Ethernet networking switch, and a much improved purpose-designed CPU. No other competitors have such a complete suite of integrated silicon products.
Atomic Claim 18/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0010
Claim: SemiAnalysis assesses: Nvidia 的 competitiveness 因 extreme co-design 優勢而進一步增強。
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Atomic Claim 19/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0011
Claim: SemiAnalysis assesses: 原文認為，Nvidia 是唯一在其 AI server system 所有主要 silicon content 上，都能提供 best-in-class 或接近 best-in-class silicon product 的業者。
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Atomic Claim 20/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0012::SPLIT01
Claim: SemiAnalysis assesses: Nvidia 提供 best-in-class accelerator。
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Atomic Claim 21/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0012::SPLIT02
Claim: SemiAnalysis assesses: Nvidia 提供 SOTA scale-up switch。
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Atomic Claim 22/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0012::SPLIT03
Claim: SemiAnalysis assesses: Nvidia 提供 best-in-class NIC。
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Atomic Claim 23/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0013::SPLIT01
Claim: SemiAnalysis assesses: Nvidia 提供 one of the best Ethernet networking switches。
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Atomic Claim 24/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0013::SPLIT02
Claim: SemiAnalysis assesses: Nvidia 提供大幅改善且 purpose-designed 的 CPU。
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Atomic Claim 25/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0014
Claim: SemiAnalysis assesses: 原文認為，沒有其他競爭者具備如此完整的一套 integrated silicon products。
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In the sections below, we will discuss the 6 silicon products of the Vera Rubin platform at the silicon level. Then, we will discuss the rack and compute tray evolution from Grace Blackwell to Vera Rubin from the design perspective and the implication to components: cables, connectors, PCB, thermal, mechanical, and power.
Next, we will discuss the major networks of the VR NVL72 system, namely the scale up NVLink 6 network and the backend scale out network. We will discuss the logistical implications of much more limited hyperscaler customisation and the assembly supplier landscape.
Lastly, the report ends with a discussion on the TCO of the VR NVL72 system as well as the BoM and Power Budget estimate supporting the TCO analysis. Behind the paywall, we also provide readers with insight into Nvidia’s plans for their Groq IP. We will also cover some of the challenges with regards to HBM ramp for Micron, SK Hynix, and Samsung.
Today we are also launching the VR NVL72 Component BoM and Power Budget Model. It provides a system-level bill of materials and power budget analysis for the VR NVL72 system covered in this article. This is important because various vendors and their shares of the subcomponents will drive whether they are winners or losers in the $500B Rubin buildout. The downstream impacts and dislocations in the market are large. The model covers:
Atomic Claim 26/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0026
Claim: SemiAnalysis 預期，各 vendor 的 subcomponent share 將影響其在原文所述 $500B Rubin buildout 中的贏家／輸家地位。
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- Nvidia Compute Tray Content: Strata module with Rubin GPU, Vera CPU, SOCAMM memory; BlueField-4; ConnectX-9
Atomic Claim 27/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0028
Claim: Nvidia Compute Tray content 包含搭載 Rubin GPU 的 Strata module。
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Atomic Claim 28/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0029
Claim: Nvidia Compute Tray content 包含 Vera CPU。
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Atomic Claim 29/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0030
Claim: Nvidia Compute Tray content 包含 SOCAMM memory。
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Atomic Claim 30/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0031
Claim: Nvidia Compute Tray content 包含 BlueField-4。
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Atomic Claim 31/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0032
Claim: Nvidia Compute Tray content 包含 ConnectX-9。
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- NVLink System: NVSwitch, NVLink backplane and cabling, associated connectors, host CPU management module
Atomic Claim 32/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0033
Claim: NVLink system 包含 NVSwitch。
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Atomic Claim 33/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0034::SPLIT01
Claim: NVLink system 包含 NVLink backplane。
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Atomic Claim 34/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0034::SPLIT02
Claim: NVLink system 包含 cabling。
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Atomic Claim 35/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0035
Claim: NVLink system 也包含相關 connectors。
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Atomic Claim 36/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0036
Claim: NVLink system 包含 host CPU management module。
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- Liquid Cooling Content: Coldplates, QDs, Manifolds
Atomic Claim 37/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0037
Claim: Liquid Cooling content 包含 Coldplates。
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Atomic Claim 38/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0038
Claim: Liquid Cooling content 包含 QDs。
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Atomic Claim 39/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0039
Claim: Liquid Cooling content 包含 manifolds。
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- PCB, Substrate, and Materials Content: key system boards, ABF substrates, CCL content
Atomic Claim 40/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0040
Claim: PCB、Substrate 與 materials content 包含關鍵 system boards。
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Atomic Claim 41/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0041
Claim: PCB、Substrate 與 materials content 包含 ABF substrates。
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Atomic Claim 42/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0042
Claim: PCB、Substrate 與 materials content 包含 CCL content。
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- Connectors: Paladin HD2 Board to Board Connectors, Paladin HD2 NVLink 6.0 Connectors
Atomic Claim 43/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0043
Claim: Connector content 包含 Paladin HD2 Board-to-Board Connectors。
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Atomic Claim 44/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0044
Claim: Connector content 包含 Paladin HD2 NVLink 6.0 connectors。
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- Power Delivery Content: power shelves, busbars, VRMs, power delivery modules
Atomic Claim 45/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0045
Claim: Power Delivery content 包含 power shelves。
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Atomic Claim 46/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0046
Claim: Power Delivery content 包含 busbars。
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Atomic Claim 47/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0047
Claim: Power Delivery content 包含 VRMs。
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Atomic Claim 48/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0048
Claim: Power Delivery content 包含 power delivery modules。
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- Mechanical Structure: chassis, loading mechanism, railkits, rack chassis
Atomic Claim 49/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0049
Claim: Mechanical Structure 包含 chassis。
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Atomic Claim 50/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0050
Claim: Mechanical Structure 包含 loading mechanism。
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Atomic Claim 51/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0051
Claim: Mechanical Structure 包含 railkits。
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Atomic Claim 52/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0052
Claim: Mechanical Structure 包含 rack chassis。
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- Management modules: BMC
Atomic Claim 53/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0053
Claim: Management modules 包含 BMC。
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- Networking: Transceivers, CX-9
Atomic Claim 54/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0054
Claim: Networking content 包含 transceivers。
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Atomic Claim 55/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0055
Claim: Networking content 包含 CX-9。
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model
Extreme Co-design: 6 Silicon Product Offerings under the Rubin Platform - Chip Floorplans & Specifications
Rubin’s dense FP4 and FP8 FLOPs increase by roughly ~3.5× versus GB200, while FP16 FLOPs rise by a more modest ~1.6x, underscoring NVIDIA’s continued emphasis on FP4/FP8 as the primary scaling vector. On the memory side, HBM capacity remains flat from GB300, while HBM bandwidth scales more aggressively at ~2.8x. Overall, the architecture prioritizes bandwidth and low-precision compute.
Atomic Claim 56/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0047
Claim: 記憶體方面，HBM capacity 與 GB300 相同。
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Atomic Claim 57/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0048
Claim: Rubin 的 HBM 頻寬提升至 Blackwell 的約 2.8 倍。
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Atomic Claim 58/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0056::SPLIT01
Claim: 相較 GB200，Rubin 的 dense FP4 與 FP8 FLOPs 約提升 3.5 倍。
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Atomic Claim 59/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0056::SPLIT02
Claim: 相較 GB200，Rubin 的 FP16 FLOPs 約提升 1.6 倍。
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Atomic Claim 60/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0056::SPLIT03
Claim: SemiAnalysis 認為，這些 scaling differences 顯示 NVIDIA 持續將 FP4／FP8 作為主要 scaling vector。
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Atomic Claim 61/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0058
Claim: Rubin 架構優先著重頻寬與低精度運算。
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Rubin
Rubin’s design is a logical evolution from Blackwell, with the move to a 3nm process and disaggregating I/O into chiplets while keeping the same basic structure of 2 reticle-sized dies with 8 stacks of HBM. 35 PFLOPS dense FP4 is a 3.5x improvement over Blackwell GB200, achieved by:
Atomic Claim 62/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0051
Claim: Rubin 採用 3nm 製程。
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Atomic Claim 63/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0052
Claim: Rubin 將 I/O 拆分至 chiplets。
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Atomic Claim 64/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0053
Claim: Rubin 維持 2 個 reticle-sized dies 的基本架構。
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Atomic Claim 65/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0054
Claim: Rubin 採用 8 stacks HBM。
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Atomic Claim 66/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0059
Claim: Rubin 的設計是從 Blackwell 邏輯演進而來。
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Atomic Claim 67/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0061
Claim: Rubin 的 dense FP4 運算效能為 35 PFLOPS，是 Blackwell GB200 的 3.5 倍。
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- Increasing SM count from 160 to 224
Atomic Claim 68/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0062
Claim: 關於 Rubin：SM 數量由 160 增加至 224。
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- Doubling Tensor Core width in the SM to 32768 FP4 MACs/clock
Atomic Claim 69/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0063
Claim: Rubin 將單一 SM 內的 Tensor Core 寬度加倍，達到每時脈 32,768 次 FP4 MAC 運算。
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- Increasing clock speed 25% from 1.90GHz to 2.38GHz
Atomic Claim 70/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0064
Claim: 關於 Rubin：Clock speed 提高 25%，由 1.90GHz 升至 2.38GHz。
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Additionally, Nvidia claims up to an effective 50 PFLOPS of FP4 performance can be achieved with an updated 3rd generation Transformer Engine that replaces 2:4 structured sparsity from prior generations. We will detail this architectural feature for Rubin below.
Atomic Claim 71/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0065::SPLIT01
Claim: 更新後的第 3 代 Transformer Engine 取代前代採用的 2:4 structured sparsity。
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Atomic Claim 72/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0065::SPLIT02
Claim: Nvidia 宣稱，使用更新後第 3 代 Transformer Engine 可使 FP4 有效效能最高達 50 PFLOPS。
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Notably, the Tensor core width doubling only applies to FP4 and FP8, with BF16 and TF32 remaining the same as Blackwell, resulting in performance scaling only 1.6x of Blackwell. This architectural decision reflects NVIDIA’s belief that most training and inference workloads will move away from TF32 and BF16 and onto FP8 and FP4.
Atomic Claim 73/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0060
Claim: 相較 Blackwell，Rubin 僅在 FP4 與 FP8 將 Tensor Core 寬度加倍。
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Atomic Claim 74/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0061
Claim: Rubin 的 BF16／TF32 Tensor Core 寬度與 Blackwell 相同。
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Atomic Claim 75/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0062
Claim: Rubin 的 BF16／TF32 效能提升至 Blackwell 的 1.6 倍。
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Atomic Claim 76/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0063
On the memory front, the move to HBM4 means double the bus width per stack, running at 10.8 GT/s for 22TB/s total bandwidth or 2.75x Blackwell at the same 288GB capacity as GB300. Memory bandwidth has been upgraded significantly from the original 13TB/s advertised at GTC 2025. In order to catch up to AMD MI450’s memory bandwidth, Nvidia requested much higher HBM4 pin speeds from the DRAM suppliers - well above the speeds that was in the JEDEC specification for HBM4.
Atomic Claim 77/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0064
Claim: 從 HBM3E 轉向 HBM4，使每個堆疊的匯流排寬度加倍。
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Atomic Claim 78/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0065
Claim: Rubin HBM4 運行速率為 10.8 GT/s。
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Atomic Claim 79/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0066
Claim: Rubin 的 HBM 總 bandwidth 為 22TB/s。
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Atomic Claim 80/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0067
Claim: Rubin 規格所列的 22TB/s HBM 頻寬是 Blackwell 的 2.75 倍。
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Atomic Claim 81/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0068
Claim: Rubin 維持 288GB HBM 容量，與 GB300 相同。
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Atomic Claim 82/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0071
Claim: Rubin 的 HBM 頻寬較 GTC 2025 公布的原始 13TB/s 規格大幅提升。
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Atomic Claim 83/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0072
While Nvidia is targeting 22TB/s, we understand that memory suppliers are having challenges hitting Nvidia’s requirements and we see it likely that initial shipments will come in slightly below at closer to 20TB/s. We have discussed the implications to SK Hynix, Samsung, and Micron extensively for Accelerator and HBM model subscribers. Micron is well behind Samsung and Hynix and we believe they are effectively out of the picture for Rubin HBM4.
Atomic Claim 84/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0071
Claim: Nvidia 對 Rubin HBM bandwidth 的目標為 22TB/s。
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Atomic Claim 85/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0072
Claim: SemiAnalysis 了解，memory suppliers 正面臨難以達成 Nvidia HBM bandwidth 要求的挑戰。
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Atomic Claim 86/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0074
Atomic Claim 87/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0075
Claim: 截至 2026 年 2 月，SemiAnalysis 預期 Micron 實際上將被排除在 Rubin HBM4 供應之外。
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Atomic Claim 88/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0074
Claim: SemiAnalysis 預期初期出貨的 Rubin，其 HBM 頻寬將較接近 20TB/s，而非 Nvidia 的 22TB/s 目標。
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The NVLink-C2C chiplet houses the SerDes for the Vera CPU connection, doubled in bandwidth to 1.8TB/s, while the larger NVLink 6 chiplet on the other end of the chip features 36 custom ‘400G’ SerDes links for 2x NVLink bandwidth to all 72 Rubin GPUs.
Atomic Claim 89/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0078::SPLIT01
Claim: NVLink-C2C chiplet 內含用於連接 Vera CPU 的 SerDes。
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Atomic Claim 90/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0078::SPLIT02
Claim: NVLink-C2C 與 Vera CPU 之間的 connection bandwidth 加倍至 1.8TB/s。
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Atomic Claim 91/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0079::SPLIT01
Claim: 較大的 Rubin NVLink 6 chiplet 位於 GPU 封裝上與 C2C I/O chiplet 相對的一側。
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Atomic Claim 92/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0079::SPLIT02
Claim: 較大的 NVLink 6 chiplet 配置 36 條 custom 400G SerDes links。
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Atomic Claim 93/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0079::SPLIT03
Claim: 較大的 NVLink 6 chiplet 的 links 連向全部 72 顆 Rubin GPU。
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Atomic Claim 94/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0079::SPLIT04
Claim: 較大的 NVLink 6 chiplet 對全部 72 顆 Rubin GPU 提供 2 倍 NVLink bandwidth。
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Transistor count has climbed 60% to 336 billion.
Atomic Claim 95/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0080
Claim: Rubin GPU 的電晶體數量較 Blackwell 增加 60%，達 3,360 億個。
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A notable omission from Rubin is the mention of Sparse FLOPs. In previous generations, 2:4 structured sparsity was used to double marketing FLOPs numbers. However, adoption was minimal especially at low precisions due to accuracy losses from the rigid sparsity structure forcing half of the values to be zero. Programmers basically ignored structured sparsity as it was not useful, which caused hardware designs to change as well.
Blackwell Ultra GB300 added 50% more dense FP4 while keeping sparse FP4 FLOPs the same, while AMD’s MI355X stopped supporting structured sparsity on MXFP8, MXFP6 and MXFP4 formats to save silicon area.
Atomic Claim 96/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0087
Claim: Blackwell Ultra GB300 的 sparse FP4 FLOPs 維持不變。
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Atomic Claim 97/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0088
Atomic Claim 98/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0089
Claim: AMD 移除 structured-sparsity 支援，是為了節省 silicon area。
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Atomic Claim 99/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0081
Claim: Rubin 的一個明顯缺項，是沒有提到 Sparse FLOPs。
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Atomic Claim 100/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0082
Claim: 在前幾代產品中，2:4 structured sparsity 曾被用來把 marketing FLOPs 數字放大至 2 倍。
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Atomic Claim 101/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0083
Claim: 然而，structured sparsity 的採用率很低，尤其在 low precision 下，因為僵化的 sparsity 結構迫使一半數值歸零，造成 accuracy loss。
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Atomic Claim 102/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0084::SPLIT01
Claim: Programmers 基本上忽略 structured sparsity，因為它實用性不足。
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Atomic Claim 103/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0084::SPLIT02
Claim: Programmers 對 structured sparsity 的低採用促使 hardware designs 隨之改變。
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Atomic Claim 104/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0085
Claim: Blackwell Ultra GB300 的 dense FP4 增加 50%。
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Rubin’s adaptive compression engine in the improved Transformer Engine is a key feature to re-boost naturally sparser inference performance by doing dynamic computation of sparsity in-flight and eliminating zeros in the data stream without zeroing out non-zero values, thus maintaining model accuracy while still boosting performance. This is done automatically on existing models built for Blackwell without the need for a new programming model or specific optimizations.
While models that utilize Post Training Quantization or Quantization Aware Training will be tuned to maximize adaptive compression speedups, they are not strictly needed to take advantage of dynamic compression.
Atomic Claim 105/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0088
Claim: Rubin 改良版 Transformer Engine 中的 adaptive compression engine，會在資料流中即時動態計算 sparsity 並消除 zeros，但不把非零值強制歸零，因此可維持 model accuracy，同時提升天然較 sparse 的 inference performance。
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Atomic Claim 106/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0089
Claim: Rubin 的自適應壓縮會自動套用至既有為 Blackwell 建立的模型，不需要新的程式設計模型或特定最佳化。
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Atomic Claim 107/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0090
Claim: 使用 Post Training Quantization 或 Quantization Aware Training 的 models 可針對 adaptive compression speedup 進一步調校，但要利用 dynamic compression 並不強制需要這些方法。
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This means the sparser the workload, the closer the performance will be to the 50 PFLOPS marketed peak performance. NVIDIA thus brands the 50 PFLOPS figure as FP4 Inference while the 35 PFLOPS FP4 Training number is for dense workloads. As accuracy is preserved, this allows the marketing team to claim 5x FLOPs for Rubin over GB200, comparing 50 PFLOPS dynamically compressed FP4 to 10 PFLOPS dense FP4. Whether actual GEMM performance reaches 50 PFLOPS depends on how many zeros are in the tensor.
The more zeros, the closer it can reach. The less zeros in the tensor, the lower the speedup. Overall, we expect to see much greater traction for Rubin’s adaptive sparsity compression as opposed to structured sparsity thanks to the automatic implementation.
Atomic Claim 108/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0091
Claim: 在 Rubin 自適應壓縮下，較稀疏的工作負載預期能更接近宣傳的 50 PFLOPS 峰值。
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Atomic Claim 109/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0092::EPI01
Claim: Nvidia 將 50 PFLOPS 標示為 FP4 Inference。
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Atomic Claim 110/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0092::EPI02
Claim: Nvidia 將針對稠密工作負載的 35 PFLOPS 標示為 FP4 Training。
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Atomic Claim 111/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0093
Claim: 在維持 accuracy 的前提下，marketing team 可宣稱 Rubin 的 FLOPs 是 GB200 的 5 倍：比較 50 PFLOPS 的 dynamically compressed FP4 與 10 PFLOPS 的 dense FP4。
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Atomic Claim 112/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0094
Claim: Rubin 自適應壓縮的 GEMM 效能能否達到 50 PFLOPS，取決於張量含有多少個零。
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Atomic Claim 113/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0095
Claim: 張量中的零越多，Rubin 自適應壓縮效能就越能接近宣傳的 50 PFLOPS 峰值。
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Atomic Claim 114/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0096
Claim: 張量中的零越少，Rubin 自適應壓縮所能提供的加速幅度就越小。
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Atomic Claim 115/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0097
Claim: 整體而言，SemiAnalysis 預期 Rubin 的 adaptive sparsity compression，因為能自動實作，採用度會明顯高於 structured sparsity。
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With that said, many ML Systems engineers are still skeptical that this new form of sparsity will work well, and it is very possible that Nvidia’s 50 PFLOPS is purely marketing like prior generations.
Atomic Claim 116/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0098
Claim: 儘管如此，許多 ML Systems engineers 仍懷疑這種新的 sparsity 是否能良好運作。
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Atomic Claim 117/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0099
Claim: 也很可能 Nvidia 所稱的 50 PFLOPS 和前幾代一樣，主要只是 marketing 數字。
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Rubin’s chip level TDP increases up to 2,300W vs 1000-1400W for Blackwell. Supply chain rumors have indicated that there are 2 different “SKUs” with different power and performance profiles: a Max-P variant at 2,300W and a Max-Q variant at 1,800W. However, these are not distinct hardware SKUs but the 2 default power profiles that Nvidia is offering users based on their workload needs. Max-Q is what Nvidia believes offers the best performance per Watt.
Max-P offers the greatest absolute performance though this would come with an efficiency penalty. Running the Max-P setting results in a 20% increase in rack power draw but the performance gain fall well short of this 20% power consumption increase.
Atomic Claim 118/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0104
Claim: 但這兩者並非不同硬體 SKU，而是 Nvidia 依使用者 workload 需求提供的兩種預設 power profile。
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Atomic Claim 119/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0105
Claim: Nvidia 認為 Max-Q 提供最佳 performance per Watt。
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Atomic Claim 120/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0100
Claim: Rubin 的 chip-level TDP 最高增加到 2,300W，相較之下 Blackwell 為 1,000–1,400W。
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Atomic Claim 121/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0101
Claim: Supply chain rumors 指出有兩種不同 power/performance profile：Max-P 為 2,300W，Max-Q 為 1,800W。
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Atomic Claim 122/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0102
Claim: Rubin Max-P 與 Max-Q 是同一硬體的軟體功耗設定，而非不同的硬體 SKU。
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Atomic Claim 123/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0104
Claim: Rubin Max-P 提供最高的絕對效能，但效率較 Max-Q 低。
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Atomic Claim 124/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0105
Claim: 來源指出，Rubin Max-P 的機櫃功耗較 Max-Q 高 20%。
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Atomic Claim 125/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0106
Claim: 來源指出，Rubin Max-P 相對 Max-Q 的效能增幅，遠低於其 20% 的耗電增幅。
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These power profiles are software managed. Users can also choose whatever max power draw they prefer (as long as it is no more than 2,300W per GPU) and this has been the case for previous GPU generations as well. Several hyperscalers and labs have chosen to run their GPUs at lower power to optimize for performance per Watt as well as taking into account power availability constraints.
Atomic Claim 126/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0107
Claim: Rubin Max-P 與 Max-Q 的功耗設定由軟體管理。
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Atomic Claim 127/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0108
Claim: 使用者可選擇 Rubin 的最高功耗，上限為每顆 GPU 2,300W。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 128/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0109
Claim: 前幾代 GPU 也同樣可以這樣調整 power draw。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 129/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0110
Claim: 部分 hyperscalers 與 labs 選擇讓 GPUs 以較低 power 運作，以最佳化 performance per Watt，同時納入 power availability constraints。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 130/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TIM1
Claim: Rubin 封裝示意圖將 TIM1 標示為石墨烯薄膜。
Frame:ATTRIBUTE· Mode:ATTRIBUTED· Mapping:COMPLETE
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For the mechanical structure of the Rubin package, upgrades have also been made with the addition of an upgraded heat spreader and a stiffener. This compares to Blackwell B200 and B300 packages that only have a heat spreader lid. The heat spreader lid allows more equal distribution of heat exiting the package. It also provides mechanical support for the package to prevent warpage.
Atomic Claim 131/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0112
Claim: 相較之下，Blackwell B200 與 B300 package 僅配置 heat spreader lid。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 132/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0111::SPLIT01
Claim: The Rubin package mechanical structure adds an upgraded heat spreader.
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 133/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0111::SPLIT02
Claim: The Rubin package mechanical structure adds a stiffener.
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 134/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0114
Claim: Rubin 的均熱上蓋讓離開封裝的熱量分布更均勻。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 135/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0115
Claim: Rubin 的均熱上蓋提供機械支撐，以減少封裝翹曲。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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For Rubin, the heat spreader lid is a module made up of two separate lids. Beside the heat spreader lid, a stiffener is added to the package structure to provide even more mechanical support to avoid warpage. At the surface of the heat spreader lid, there will also be a layer of electroplated gold. The reason for this is to prevent corrosion from liquid metal TIM2, which is between the heat spreader lid and the cold plate.
Atomic Claim 136/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0116
Claim: 對 Rubin 而言，heat spreader lid 是由兩個獨立 lids 組成的 module。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 137/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0117
Claim: 除了 heat spreader lid 之外，package structure 也加入 stiffener，提供更多 mechanical support 以避免 warpage。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 138/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0118
Claim: Rubin 的均熱上蓋表面以電鍍方式鍍金。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 139/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0119::SPLIT01
Claim: Rubin 的均熱上蓋表面鍍金，以防止液態金屬 TIM2 造成腐蝕。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 140/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0119::SPLIT02
Claim: Rubin 的液態金屬 TIM2 位於均熱上蓋與冷板之間。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Vera
NVIDIA was aggressive on the CPU front, with Vera doubling performance over Grace by moving to a 3nm reticle-sized compute die and disaggregating the memory controllers and I/O into chiplets. Core count increases from 72 to 88, with 91 cores printed on die to leave redundancy for yield improvement. These cores mark the return of NVIDIA’s custom ARM CPU designs, with the ‘Olympus’ core now supporting SMT multi-threading for a total of 176 processing threads.
L3 cache also received a 40% capacity bump to 162MB. Memory bus width doubled to 1024-bit and speed increased to 9600MT/s for 2.5x bandwidth, while maximum capacity tripled to 1.5TB with 8 SOCAMM modules. The NVLink-C2C to the Rubin GPUs also doubled in bandwidth to 1.8TB/s. PCIe6 and CXL3.1 are now supported as well. All this results in transistor count increasing 2.2x to 227 billion.
Atomic Claim 141/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT01
Claim: 在 Nvidia 的 CPU 設計中，Vera CPU 的效能是 Grace 的兩倍。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 142/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT02
Claim: 在 Nvidia 的 CPU 設計中，Vera CPU 採用光罩尺寸等級的 3nm 運算晶粒。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 143/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT03
Claim: 在 Nvidia 的 CPU 設計中，Vera CPU 將記憶體控制器拆分為 chiplet。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 144/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT04
Claim: 在 Nvidia 的 CPU 設計中，Vera CPU 將 I/O 拆分為 chiplet。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 145/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT05
Atomic Claim 146/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0121::SPLIT01
Claim: Vera CPU 的啟用核心數由 72 個增加至 88 個。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 147/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0121::SPLIT02
Claim: Vera CPU 晶粒上實際製作 91 個核心，保留冗餘以改善良率。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 148/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0122::SPLIT01
Claim: Vera CPU 的 Olympus 核心標誌著 Nvidia 自訂 ARM CPU 設計的回歸。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 149/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0122::SPLIT02
Claim: Vera CPU 的 Olympus 核心支援 SMT 多執行緒。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 150/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0122::SPLIT03
Claim: Vera CPU 提供 176 個處理執行緒。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 151/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0123
Claim: Vera CPU 的 L3 快取容量較 Grace 增加 40%，達 162MB。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 152/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT01
Claim: Vera CPU 的記憶體匯流排寬度加倍至 1024-bit。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 153/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT02
Claim: Vera CPU 的記憶體速度提高至 9600MT/s。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 154/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT03
Claim: Vera CPU 更寬且更快的記憶體介面提供 2.5 倍的記憶體頻寬。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 155/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT04
Claim: Vera CPU 的最大記憶體容量增加至三倍，達 1.5TB。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 156/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT05
Claim: Vera CPU 使用八個 SOCAMM 模組以達到最大記憶體容量。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 157/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0125
Claim: Vera CPU 與 Rubin GPU 之間的 NVLink-C2C 頻寬加倍至 1.8TB/s。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 158/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0126::SPLIT01
Claim: Vera CPU 支援 PCIe6。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 159/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0126::SPLIT02
Claim: Vera CPU 支援 CXL3.1。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 160/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0127
Claim: Vera CPU 的電晶體數量增加至 Grace 的 2.2 倍，達 2,270 億個。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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NVLink 6 Switch
While the rack-level switching bandwidth has doubled, the number of NVLink Switch chips per rack has also doubled to 36, with each switch tray now housing 4 Switch chips. This means the new NVLink 6 Switch chip has the same 28.8T bandwidth as NVLink5 Switch, with half the number of ports but running at double the rate using ‘400G’ bi-directional SerDes. This allows the high bandwidth switch design to remain as a single monolithic die, saving on design complexity.
The layout remains the same as NVIDIA’s previous switches, with 2 sides for IO and a central logic section crossbar and 3.6 TFlop SHARP in-network compute acceleration.
Atomic Claim 161/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0128::SPLIT01
Claim: Rubin 的機櫃級 NVLink 交換頻寬加倍。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 162/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0128::SPLIT02
Claim: Rubin 將每個機櫃的 NVLink 交換晶片數量加倍至 36 顆。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 163/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0128::SPLIT03
Claim: 每個 Rubin NVLink 交換器托盤容納四顆交換晶片。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 164/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0129
Claim: 新的 NVLink 6 Switch chip 與 NVLink5 Switch 一樣具有 28.8T bandwidth，但 ports 數量只有一半。
Frame:ATTRIBUTE· Mode:INFERRED· Mapping:PARTIAL
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Atomic Claim 165/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0130
Claim: NVLink 6 交換器使用自訂 400G 雙向 SerDes，資料速率為前一代的兩倍。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 166/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0131
Claim: 所述 NVLink 6 SerDes 設計使高頻寬交換器仍可採用單一單體晶粒，降低設計複雜度。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 167/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0132::SPLIT01
Claim: NVLink 6 交換晶片沿用先前 Nvidia 交換器的配置：I/O 位於兩側，中央邏輯區為 crossbar。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 168/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0132::SPLIT02
Claim: NVLink 6 交換器提供 3.6 TFlop 的 SHARP 網路內運算加速。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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ConnectX-9
The ConnectX-9 is largely iterative from ConnectX-8, with the same 800G networking bandwidth and 48-lane PCIe6 switch capability. However, CX-9 now supports 800G Ethernet with 4x200G PAM4 SerDes, compared to CX-8 that only supported it on InfiniBand. For the Rubin platform, NVIDIA is doubling the number of NICs per GPU to achieve 2x scale-out bandwidth.
Atomic Claim 169/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0133::SPLIT01
Claim: ConnectX-9 大致上是 ConnectX-8 的漸進改版。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 170/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0133::SPLIT02
Claim: ConnectX-9 維持與 ConnectX-8 相同的 800G 網路頻寬。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 171/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0133::SPLIT03
Claim: ConnectX-9 維持與 ConnectX-8 相同的 48-lane PCIe6 交換能力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 172/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0134
Claim: CX-9 現在可透過 4×200G PAM4 SerDes 支援 800G Ethernet；相較之下，CX-8 的 800G 僅支援 InfiniBand。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 173/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0135
Claim: 在 Rubin platform 上，NVIDIA 將每顆 GPU 對應的 NIC 數量加倍，以達到 2 倍 scale-out bandwidth。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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BlueField-4
BlueField-4’s design departs significantly from BlueField-3. Instead of doing a bespoke tapeout with compute and networking, NVIDIA simply reuses their large Grace CPU die, co-packaged with a ConnectX-9 die to make an 800G DPU with massive compute capabilities. 128GB of LPDDR5 feeds the Grace CPU at half the bandwidth of regular Grace. That is 4x the memory capacity of BlueField-3. BlueField-4 can also function as a storage controller, with four BF-4 chips in each Context Memory Storage system.
Atomic Claim 174/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0137
Claim: NVIDIA 不再做 compute/networking 的 bespoke tapeout，而是重用大型 Grace CPU die，與 ConnectX-9 die co-package，形成具備大量 compute capability 的 800G DPU。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 175/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0138
Claim: 128GB LPDDR5 供給 Grace CPU，其 bandwidth 為一般 Grace 的一半。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 176/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0139
Claim: BlueField-4 的記憶體容量是 BlueField-3 的四倍。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 177/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0140::SPLIT01
Claim: BlueField-4 可作為儲存控制器。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 178/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0140::SPLIT02
Claim: 每個 Context Memory Storage 系統包含四顆 BlueField-4 晶片。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Spectrum-6
While not part of the Rubin NVL72 rack, Spectrum-6 CPO enables even larger scale-out clusters with its doubled radix. The design retains the same features as Spectrum-5, with 8 IO chiplets surrounding the main switch die. 102.4T switching bandwidth is achieved with 512x 200G SerDes. 32 3.2T optical engines on the package convert these electrical signals to optical links, each with a detachable fiber connector.
The SN6810 features one of these chips, while the SN6800 houses four, multiplexed together to create a 409.6T switch box. There will also be a non-CPO version with pluggable OSFP cages in the SN6600. The non-CPO version will be more common in our view.
Atomic Claim 179/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0141
Claim: Spectrum-6 CPO 雖不屬於 Rubin NVL72 rack，但藉由 doubled radix 可支援更大的 scale-out clusters。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 180/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0142::SPLIT01
Claim: Spectrum-6 保留與 Spectrum-5 相同的設計特性。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 181/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0142::SPLIT02
Claim: Spectrum-6 的主交換晶粒周圍配置八個 I/O chiplet。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 182/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0143
Claim: Spectrum-6 透過 512 條 200G SerDes 通道達到 102.4T 交換頻寬。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 183/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0144::SPLIT01
Claim: The Spectrum-6 CPO package has 32 optical engines rated at 3.2T each.
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 184/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0144::SPLIT02
Claim: Spectrum-6 package optical engines convert electrical signals to optical links.
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 185/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0144::SPLIT03
Claim: Each Spectrum-6 package optical engine has a detachable fiber connector.
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 186/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0145
Claim: Spectrum-6 SN6810 包含一個 102.4T 交換器封裝。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 187/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0146
Claim: Spectrum-6 SN6800 將四個 102.4T 交換器封裝多工整合為一台 409.6T 交換器。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 188/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0147
Claim: Spectrum-6 也提供採用可插拔 OSFP 插槽、未使用 CPO 的 SN6600 版本。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 189/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0148
Claim: SemiAnalysis 預期 Spectrum-6 的 non-CPO SN6600 版本會比 CPO 版本更普遍。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:PARTIAL
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Rubin Oberon Rack: NVL72 not NVL144 nor NVL36
Since the announcement of GB200 at Nvidia GTC 2024, the concept of an AI server system has shifted from a chassis to a rack scale system. In our GB200 article, we discussed the evolution of Nvidia AI server form factor from HGX (8 GPU per node) to Oberon (NVL72 rack scale). While the HGX form factor still exists, the majority of Nvidia’s Blackwell GPUs are integrated in the Oberon form factor. Rubin will also be offered in both HGX and Oberon systems.
Atomic Claim 190/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0149
Claim: 自 Nvidia 在 GTC 2024 發表 GB200 後，AI server system 的概念已從 chassis 轉向 rack-scale system。
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Atomic Claim 191/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0151
Claim: 雖然 HGX form factor 仍存在，但 Nvidia 多數 Blackwell GPUs 已整合在 Oberon form factor。
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Atomic Claim 192/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0152
Claim: Rubin 提供 HGX 與 Oberon 兩種系統形式。
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The key difference between the Blackwell and Rubin Oberon architecture is the number of SKUs offered to customers. As Blackwell Oberon was the first ever mass deployment of a rack scale solution with rack power density over 100KW for the GB200 NVL72 SKU, many datacenters did not have the infrastructure ready to support 100kw+ per rack. Nvidia offered two SKUs of Blackwell Oberon: GB200 NVL72 and GB200 NVL36x2. The latter being a lower density SKU offered for customers who did not have the infra ready to handle the thermals of a single high density rack.
Atomic Claim 193/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0153
Claim: Blackwell 與 Rubin Oberon architecture 的主要差異，是提供給 customers 的 SKU 數量。
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Atomic Claim 194/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0154::SPLIT01
Claim: Blackwell Oberon GB200 NVL72 是首個大規模部署、每櫃功率密度超過 100kW 的機櫃級方案。
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Atomic Claim 195/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0154::SPLIT02
Claim: Blackwell Oberon 初期部署時，許多資料中心缺乏支援 100kW 以上機櫃的基礎設施。
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Atomic Claim 196/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0155::SPLIT01
Claim: Nvidia 提供 GB200 NVL72 作為 Blackwell Oberon 的一種 SKU。
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Atomic Claim 197/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0155::SPLIT02
Claim: Nvidia 提供 GB200 NVL36x2 作為 Blackwell Oberon 的一種 SKU。
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Atomic Claim 198/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0156
Claim: GB200 NVL36x2 是功率密度較低的 Blackwell SKU，供無法支援單一 NVL72 機櫃熱負載的客戶使用。
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Unlike Blackwell, Rubin is only offered in the VR NVL72 SKU. The set up is very similar to that of GB200/GB300 NVL72. Each VR NVL72 system consists of:
Atomic Claim 199/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0157
Claim: 不同於 Blackwell，Rubin 只提供 VR NVL72 SKU。
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Atomic Claim 200/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0158
Claim: 所述 VR NVL72 機櫃配置與 GB200／GB300 NVL72 非常相近。
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Atomic Claim 201/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0160
Claim: 每套系統包含 72 個 Rubin GPU packages。
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Atomic Claim 202/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPU36
Claim: 每個 VR NVL72 機櫃包含 36 顆 Vera CPU。
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Atomic Claim 203/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0161
Claim: 每套系統包含 36 顆 NVLink 6 Switch ASICs。
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Atomic Claim 204/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-OOB
Claim: VR NVL72 配置包含兩台頻外管理用的 1GbE 交換器。
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Atomic Claim 205/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TRAY-CPU
Claim: VR NVL72 配置中的每個運算托盤包含兩顆 Vera CPU。
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Atomic Claim 206/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TRAY-GPU
Claim: VR NVL72 配置中的每個運算托盤包含四顆 Rubin GPU。
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Atomic Claim 207/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TRAYS
Claim: VR NVL72 機櫃配置包含十八個 1U 運算托盤。
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On a side note, VR NVL72 was initially known as VR NVL144 as Jensen math from GTC 2025 defined the number of GPU as the number of GPU compute die in system (with 2 compute dies per package and 72 Rubin packages per Oberon rack = 144 compute die). The naming was changed back to VR NVL72 to represent the 72 Rubin GPU packages in the system in late December. This was right before CES 2026 where the naming was officially confirmed as VR NVL72.
Atomic Claim 208/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT01
Claim: VR NVL72 最初名為 VR NVL144。
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Atomic Claim 209/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT02
Claim: 在 GTC 2025，Jensen 以 GPU 運算晶粒數而非封裝數，為 VR NVL144 命名。
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Atomic Claim 210/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT03
Claim: Each Rubin GPU package contains two compute dies.
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Atomic Claim 211/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT04
Claim: 每個 Rubin Oberon 機櫃包含 72 個 Rubin GPU 封裝。
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Atomic Claim 212/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT05
Claim: With two compute dies per package and 72 packages, the Rubin Oberon rack contains 144 GPU compute dies.
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Atomic Claim 213/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0163
Claim: 到 12 月下旬，命名改回 VR NVL72，以代表 system 內的 72 個 Rubin GPU packages。
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Atomic Claim 214/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0164::SPLIT01
Claim: VR NVL72 的名稱在 12 月下旬、CES 2026 前不久恢復使用。
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Atomic Claim 215/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0164::SPLIT02
Claim: VR NVL72 的名稱在 CES 2026 正式確認。
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CPX Form Factor
Atomic Claim 216/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPX-TRAY
Claim: 提出的 Rubin CPX 機櫃示意圖標示，每個運算托盤配置八顆 Rubin CPX GPU。
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Although Nvidia initially planned to integrate the CPX accelerator into the VR NVL72 rack, the current development suggests that CPX will only be offered as a standalone rack. To recap Rubin-era system planning, Nvidia initially contemplated three VR NVL72 configurations:
Atomic Claim 217/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0165
Claim: 雖然 Nvidia 最初計畫把 CPX accelerator 整合進 VR NVL72 rack，但目前 development 顯示 CPX 將只以 standalone rack 形式提供。
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Atomic Claim 218/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0166
Claim: 回顧 Rubin 時代的 system planning，Nvidia 最初考慮過 3 種 VR NVL72 configurations。
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Atomic Claim 219/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0167
Claim: VR NVL72 Regular configuration 是標準 Oberon VR NVL72，不包含 CPX。
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Atomic Claim 220/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0168
Claim: VR NVL72 CPX Integrated configuration 把 Rubin GPU 與 Rubin CPX 放在同一個 compute tray 內。
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Atomic Claim 221/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0169
Claim: VR NVL72 CPX Dual Rack configuration 則把 Rubin CPX 部署在獨立 rack，與 VR NVL72 rack 並列。
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The standalone/dedicated rack direction materially changes the deployment calculus. A dual-rack approach allows hyperscalers to scale prefill and decode capacity independently, optimize datacenter power envelopes, and reduce system-level failure domains versus tightly coupled trays. More importantly, it formalizes architectural disaggregation between inference prefill (compute-bound) and decode (bandwidth-bound).
Atomic Claim 222/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0171::RESEG01
Claim: Dual-rack approach 讓 hyperscalers 可以獨立擴展 prefill 與 decode capacity。
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Atomic Claim 223/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0171::RESEG02
Claim: Dual-rack approach 可最佳化 datacenter power envelope。
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Atomic Claim 224/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0171::RESEG03
Claim: Dual-rack approach 相較 tightly coupled trays 可縮小 system-level failure domain。
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Atomic Claim 225/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0173
Claim: 更重要的是，這正式形成 inference prefill（compute-bound）與 decode（bandwidth-bound）之間的 architectural disaggregation。
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Rubin CPX was originally architected as a GDDR7-based accelerator optimized for prefill, based on three key considerations:
Atomic Claim 226/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0174
Claim: Rubin CPX 原先被設計成以 GDDR7 為基礎、針對 prefill 最佳化的 accelerator，主要基於三項考量。
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Atomic Claim 227/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0175
Claim: Prefill 主要受 FLOPs 限制，而不是 bandwidth 限制，因此 HBM 的不可替代性較低。
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Atomic Claim 228/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0176
Claim: HBM 增加的 bandwidth 在 prefill 中結構性地沒有被充分利用。
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- GDDR7 offers materially lower cost per GB and avoids the need for 2.5D packaging.
Atomic Claim 229/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0177
Claim: GDDR7 的每 GB 成本明顯較低。
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Atomic Claim 230/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0178
Claim: GDDR7 avoids the need for 2.5D packaging.
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However, Nvidia began exploring HBM-equipped variants for prefill, either via modified CPX configurations or through lower memory spec (such as using HBM3E) Rubin deployments dedicated to prefill.
Atomic Claim 231/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0179::SPLIT01
Claim: Nvidia 開始探索配備 HBM、用於 prefill 的修改版 CPX 配置。
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Atomic Claim 232/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0179::SPLIT02
Claim: Nvidia 開始探索專用於 prefill、採用較低記憶體規格（例如 HBM3E）的 Rubin 部署方式。
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We also think a lot this shift is driven by evolving memory economics. Conventional DRAM pricing has risen sharply: As DDR pricing increases, the relative premium of HBM compresses because pricing is more locked down in long term contracts, narrowing the cost gap between a GDDR-based CPX and lower-spec HBM configurations, therefore eliminating a lot of the cost benefits GDDR offers relative to performance. While memory bandwidth is not as important for pre-fill compare to decode, it is still necessary.
Atomic Claim 233/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0180
Claim: 傳統 DRAM 價格已大幅上漲。
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Atomic Claim 234/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0181
Claim: 隨 DDR 價格上升，HBM 的相對 premium 被壓縮。
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Atomic Claim 235/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0182
Claim: HBM premium 被壓縮的原因之一，是 HBM pricing 更多已被 long-term contracts 鎖定。
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Atomic Claim 236/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0183
Claim: HBM premium 收斂，使 GDDR-based CPX 與 lower-spec HBM configuration 之間的成本差距縮小。
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Atomic Claim 237/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0184
Claim: 成本差距縮小後，GDDR 相對於其效能所具備的 cost advantage 也下降。
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Atomic Claim 238/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0180
Claim: SemiAnalysis 認為轉向 HBM-equipped prefill 設計很大程度由持續變化的 memory economics 驅動。
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Atomic Claim 239/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0183
Claim: 雖然 memory bandwidth 對 prefill 的重要性低於 decode，但仍然是必要條件。
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Compute Tray Redesign
One of the major changes with VR NVL72 is within the compute tray. This redesign of the compute tray is centered around simplifying assembly, namely eliminating cables from the compute tray as cables have been the major point of failure of GB200/300 assembly. As Jensen put it at CES 2026, the cableless design reduces the compute tray assembly time from 2 hours to 5 minutes. To achieve this, the VR NVL72 compute tray adopts a modular design with the modules connecting to each via board-to-board connectors.
Atomic Claim 240/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0185
Claim: compute tray redesign 的核心是簡化 assembly，尤其是從 compute tray 移除 cables；因為 cables 是 GB200／300 assembly 的主要 failure point。
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Atomic Claim 241/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0186
Claim: 依 Jensen 在 CES 2026 的說法，cableless design 將 compute tray assembly time 從 2 小時降到 5 分鐘。
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Atomic Claim 242/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0187
Claim: 為達到這個目標，VR NVL72 compute tray 採 modular design，各 modules 透過 board-to-board connectors 相互連接。
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To understand the compute tray of VR NVL72 we must first understand the 6 modules that make up the VR NVL72 compute tray:
- Strata Module x 2
- Orchid Module x4
- Compute Tray Midplane x 1
Atomic Claim 243/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-STRATA2
Claim: 每個 VR NVL72 運算托盤包含 2 個 Strata 模組。
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Atomic Claim 244/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-ORCHID4
Claim: 每個 VR NVL72 運算托盤包含 4 個 Orchid 模組。
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Atomic Claim 245/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0189
Claim: 其中包含 1 個 Compute Tray Midplane。
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- Power Delivery Module x 1
Atomic Claim 246/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0190
Claim: 關於 compute tray：其中包含 1 個 Power Delivery Module。
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- BlueField-4 Module x 1
Atomic Claim 247/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0191
Claim: 其中包含 1 個 BlueField-4 Module。
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- System Management Module x 1
Atomic Claim 248/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0192
Claim: 每個 VR NVL72 運算托盤包含一個系統管理模組。
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Strata
Atomic Claim 249/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-STRATA-CON
Claim: Strata 示意圖顯示，每塊板配置三個 Paladin HD2 板對板連接器。
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Situated at the back of the chassis, the Strata module of VR NVL72 is the equivalent of the Bianca board of GB200/300. It houses two Rubin GPUs and one Vera CPU. Unlike Bianca, the LPDDR5X memory for Vera is socketed via SOCAMM module. 8 SOCAMM sockets are placed on the left and right of Vera. Two SOCAMM modules of different capacities are offered, 192GByte and 128GByte, for a maximum of 1,534GByte and a minimum of 1,024GByte per Vera.
The Connect-X NICs mezzanine module is also taken off the Strata module as CX-9 is moved to the front of the chassis. Under the cableless design, all the cable connector ports are also removed and replaced by Paladin HD2 board-to-board connectors at the bottom of the module. On the other side, the same set of Paladin HD2 backplane connectors as GB200 and GB300 are identically placed at the back of the module connecting to the NVLink 6 Switches via the NVLink backplane.
Atomic Claim 250/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0193::SPLIT01
Claim: VR NVL72 的 Strata 模組位於機箱後方。
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Atomic Claim 251/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0193::SPLIT02
Claim: VR NVL72 的 Strata 模組對應 GB200／300 的 Bianca 板。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 252/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0194::SPLIT01
Claim: 每個 Strata 模組包含兩顆 Rubin GPU。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 253/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0194::SPLIT02
Claim: 每個 Strata 模組包含一顆 Vera CPU。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 254/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0195
Claim: 不同於 Bianca，Vera 使用的 LPDDR5X memory 透過 SOCAMM module 以 socket 方式安裝。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 255/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0196
Claim: Vera 左右兩側配置 8 個 SOCAMM sockets。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 256/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0197::SPLIT01
Claim: Vera CPU 的 SOCAMM 選項包含 192GByte 模組。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 257/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0197::SPLIT02
Claim: Vera CPU 的 SOCAMM 選項包含 128GByte 模組。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 258/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0197::SPLIT03
Claim: 來源所列每顆 Vera CPU 的最大容量為 1,534GByte。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 259/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0197::SPLIT04
Claim: 來源所列每顆 Vera CPU 的最小容量為 1,024GByte。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 260/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0198
Claim: Connect-X NIC mezzanine module 也從 Strata module 移除，因為 CX-9 被移到 chassis 前方。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 261/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0199
Claim: 在 cableless design 下，所有 cable connector ports 都被移除，改由 module 底部的 Paladin HD2 board-to-board connectors 取代。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 262/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0200::SPLIT01
Claim: Strata 模組使用與 GB200、GB300 相同的 Paladin HD2 背板連接器，且同樣配置在後方。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 263/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0200::SPLIT02
Claim: Strata 後方的 Paladin HD2 連接器透過 NVLink 背板連接 NVLink 6 交換器。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Orchid
Atomic Claim 264/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-ORCHID-E1S
Claim: Orchid 示意圖顯示，每塊板配置一個 E1.S 儲存插槽。
Frame:ATTRIBUTE· Mode:ATTRIBUTED· Mapping:COMPLETE
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The Orchid Module houses two ConnectX-9 NICs, two 800G transceiver cages, and one E1.S module slot. Four Orchid modules sit at the front of the chassis. With two Orchid modules stacked on top of each other, they occupy the front left and front right chassis space. At the end of the module there is one Paladin HD2 board-to-board connector that mates with the connector on the midplane.
The Orchid module is slim and long, allowing the PCIe 6 signal to travel from the midplane to the CX-9 NICs at the front of the chassis.
Atomic Claim 265/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0209
Claim: Orchid module 採細長設計，讓 PCIe 6 signal 能從 midplane 傳到 chassis 前方的 CX-9 NICs。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 266/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0201::SPLIT01
Claim: 每個 Orchid 模組容納兩張 ConnectX-9 NIC。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 267/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0201::SPLIT02
Claim: 每個 Orchid 模組容納兩個 800G 收發器插槽。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 268/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0201::SPLIT03
Claim: 每個 Orchid 模組容納一個 E1.S 模組插槽。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 269/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0202
Claim: Chassis 前方配置 4 個 Orchid modules。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 270/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0203
Claim: 每兩個 Orchid modules 上下堆疊，分別占據 chassis 前方左側與右側空間。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 271/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0204
Claim: Module 末端有 1 個 Paladin HD2 board-to-board connector，會與 midplane 上的 connector 對接。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Midplane
The midplane acts as a bridge for the PCIe signal between the two Strata modules and the modules at the front of the chassis. The midplane module is vertically placed across the middle of the chassis with Paladin HD2 board-to-board connector on both sides of the module. Strata modules connect to one side of the midplane while the Orchid modules, the BlueField-4 module, the PDB module, and the management modules connects to the other side.
Atomic Claim 272/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0207
Claim: midplane 作為 PCIe signal bridge，連接兩個 Strata modules 與 chassis 前方的 modules。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 273/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0208::SPLIT01
Claim: VR NVL72 的中板垂直橫跨機箱中央。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 274/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0208::SPLIT02
Claim: VR NVL72 的中板兩側皆有 Paladin HD2 板對板連接器。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 275/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0209
Claim: Strata modules 連接到 midplane 的其中一側。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 276/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0210::SPLIT01
Claim: Orchid 模組連接 VR NVL72 中板上與 Strata 模組相對的一側。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 277/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0210::SPLIT02
Claim: BlueField-4 模組連接 VR NVL72 中板上與 Strata 模組相對的一側。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 278/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0210::SPLIT03
Claim: PDB 模組連接 VR NVL72 中板上與 Strata 模組相對的一側。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 279/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0210::SPLIT04
Claim: 管理模組連接 VR NVL72 中板上與 Strata 模組相對的一側。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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BlueField-4
The BlueField-4 DPU sits in center of the front of the chassis between the left-side Orchid module and the management module. BlueField-4 is made up of a Grace CPU and a CX-9 NIC. The module also comes with 128GByte of on board LPDDR5x, 512Gbyte of on board pluggable SSD and an integrated AST2600 BMC from Aspeed. In the reference design of the VR NVL72 compute tray, BlueField-4 acts as a DPU providing up to 800Gb/s of front end networking capability.
However, just like BlueField-3, BlueField-4 will only be adopted by a handful of customers, namely CoreWeave and other smaller Neoclouds customers who have less customization capability. For most hyperscalers’ deployments, the BlueField-4 module will be replaced with their in-house frontend networking module or simply with a CX-9 which is cheaper.
Atomic Claim 280/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0218
Claim: 與 BlueField-3 類似，BlueField-4 預期只會被少數客戶採用，例如 CoreWeave 與其他 customization 能力較低的小型 Neoclouds 客戶。
Frame:COMPARISON· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 281/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0211
Claim: BlueField-4 DPU 位於 chassis 前方中央，在左側 Orchid module 與 management module 之間。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 282/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0212::SPLIT01
Claim: BlueField-4 包含一顆 Grace CPU。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 283/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0212::SPLIT02
Claim: BlueField-4 包含一張 CX-9 NIC。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 284/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0213::SPLIT01
Claim: BlueField-4 模組板載 128GByte LPDDR5X。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 285/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0213::SPLIT02
Claim: BlueField-4 模組板載 512GByte 可插拔 SSD 儲存裝置。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 286/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0214
Claim: 該 module 還整合一顆來自 Aspeed 的 AST2600 BMC。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 287/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0215
Claim: 在 VR NVL72 compute tray reference design 中，BlueField-4 作為 DPU，提供最高 800Gb/s front-end networking capability。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 288/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0218::SPLIT01
Claim: 對多數 hyperscaler 部署，來源預期 BlueField-4 的替代選項之一是自研前端模組。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 289/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0218::SPLIT02
Claim: 在此前端網路替換情境下，來源指出 CX-9 比 BlueField-4 模組便宜。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 290/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0218::SPLIT03
Claim: 對多數 hyperscaler 部署，來源所述 BlueField-4 的另一替代選項是 CX-9。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Speaking of BlueField-4, it is important to discuss the new offering Jensen highlighted at CES earlier this year: ICMS, or Inference Context Memory Storage — a platform that we hear may be rebranded to “CMX” at GTC. ICMS, or CMX, introduces a third, entirely separate network dedicated solely to context memory. CMX is a purpose-built KV cache fabric.
As long-context inference pushes context windows toward millions of tokens and agentic concurrency scales across users and services, the current memory hierarchy used to store KVcache begins to look insufficient.
Atomic Claim 291/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0220
Claim: 在討論 BlueField-4 時，Jensen 於 CES 提出了 ICMS（Inference Context Memory Storage）平台。
Frame:ATTRIBUTE· Mode:ATTRIBUTED· Mapping:PARTIAL
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Atomic Claim 292/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0220::SPLIT02
Claim: SemiAnalysis 聽聞 ICMS（Inference Context Memory Storage）平台可能在 GTC 改名為「CMX」。
Frame:ATTRIBUTE· Mode:RUMORED· Mapping:PARTIAL
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Atomic Claim 293/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0220
Claim: ICMS（或 CMX）新增第 3 個、完全獨立的 network，專門服務 context memory。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 294/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0221
Claim: CMX 是為 KV cache 專門打造的 fabric。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 295/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0222
Claim: 隨 long-context inference 把 context window 推向數百萬 tokens，且 agentic concurrency 在 users 與 services 間擴大，現有用於儲存 KV cache 的 memory hierarchy 開始顯得不足。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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KV cache grows linearly with sequence length and multiplicatively with workload parallelism, quickly expanding beyond what any single tier of memory was designed to hold. GPU HBM, while unmatched in bandwidth and latency, is not enough on its own to store KV especially for longer sequence length queries that are becoming popular between turns or tool calls. Host DRAM extends capacity but remains node-bound and limited in aggregate footprint and ultimately has limited capacity.
Meanwhile, traditional shared storage—architected for durability rather than latency—has more access time and power overhead, making it unsuitable for participation in the decode loop.
Atomic Claim 296/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0227
Claim: Host DRAM 可以擴充 memory capacity。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 297/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0228
Claim: Host DRAM 仍受限於單一 node。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 298/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0229
Claim: Host DRAM 的 aggregate footprint 與 capacity 有上限。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 299/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0223::SPLIT01
Claim: KV cache 隨序列長度呈線性成長。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 300/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0223::SPLIT02
Claim: KV cache 隨工作負載平行度呈倍乘成長。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 301/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0223::SPLIT03
Claim: 合併後的 KV cache 成長可能很快超出任何單一記憶體層級原先設計的容納能力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 302/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0224
Claim: GPU HBM 雖然在 bandwidth 與 latency 上無可匹敵，但單靠 HBM 不足以儲存 KV，尤其是愈來愈常見、跨 turns 或 tool calls 的較長 sequence-length queries。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 303/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0227
Claim: 另一方面，traditional shared storage 的設計重點是 durability 而不是 latency，因此 access time 與 power overhead 較高，不適合參與 decode loop。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Nvidia’s ICMS inserts a new G3.5 tier between local SSD (G3) and shared storage (G4), optimized specifically for ephemeral, recomputable KV cache. The ICMS requires a dedicated networking layer designed exclusively for KV traffic. Wherever networking is used in this architecture, it is provisioned as a context memory network—isolated from general data movement and optimized for predictable decode latency.
Atomic Claim 304/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0233
Claim: 在此架構中，只要使用 networking，就會配置成 context memory network，與一般 data movement 隔離，並針對可預測的 decode latency 最佳化。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 305/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0228
Claim: Nvidia 的 ICMS 在 local SSD（G3）與 shared storage（G4）之間插入新的 G3.5 tier，專門針對 ephemeral、可重新計算的 KV cache 最佳化。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 306/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0229
Claim: ICMS 需要一層專門為 KV traffic 設計的獨立 networking layer。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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The challenge with this is that the volumes of SSDs going to ICMS / CMX are quite overblown by the industry.
Atomic Claim 307/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0232
Claim: SemiAnalysis 認為，業界對流向 ICMS／CMX 的 SSD volumes 有相當程度的高估。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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BlueField-4 will be the silicon anchor of this third network. Positioned on the storage array, it terminates NVMe-oF and RDMA traffic at line rate and manages KV movement independently of host CPUs and GPUs. With 2×400G SerDes links providing 800Gb/s of bandwidth, integrated Grace CPU, and LPDDR, BlueField-4 would act as the controller for a distributed context memory fabric.
In a preferred DGX-style configuration, a single BlueField-4 per tray may serve four Rubin processors, with the DPU dedicated purely to KV cache traffic and not shared with generic storage I/O.
Atomic Claim 308/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0233
Claim: BlueField-4 將成為這個第 3 network 的 silicon anchor。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 309/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0234::SPLIT01
Claim: 在提出的 context-memory 網路中，儲存陣列上的 BlueField-4 以線速終結 NVMe-oF 流量。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 310/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0234::SPLIT02
Claim: 在提出的 context-memory 網路中，儲存陣列上的 BlueField-4 以線速終結 RDMA 流量。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 311/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0234::SPLIT03
Claim: 在提出的 context-memory 網路中，BlueField-4 獨立於主機 CPU 與 GPU 管理 KV 搬移。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 312/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0235::SPLIT01
Claim: BlueField-4 有兩條 400G SerDes 連線，提供 800Gb/s 頻寬。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 313/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0235::SPLIT02
Claim: BlueField-4 整合一顆 Grace CPU。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 314/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0236
Claim: 搭配 LPDDR，BlueField-4 將作為 distributed context memory fabric 的 controller。
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Atomic Claim 315/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0237
Claim: 在偏好的 DGX-style configuration 中，每個 tray 可能配置 1 顆 BlueField-4，服務 4 顆 Rubin processors。
Frame:NARY_RELATION· Mode:HYPOTHETICAL· Mapping:COMPLETE
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Atomic Claim 316/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0238
Claim: 在原文偏好的 DGX-style context-memory 配置中，BlueField-4 DPU 將專用於 KV cache traffic，不與 generic storage I/O 共用。
Frame:ATTRIBUTE· Mode:HYPOTHETICAL· Mapping:PARTIAL
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The new CMX/ICMS ecosystem will likely include leading storage providers such as Weka, DDN, Dell Technologies, NetApp, VAST Data, and others.
Atomic Claim 317/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0242
Claim: 新的 CMX／ICMS ecosystem 可能包含主要 storage provider Weka。
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Atomic Claim 318/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0239::SPLIT02
Claim: CMX／ICMS 生態系很可能包含 DDN。
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Atomic Claim 319/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0239::SPLIT03
Claim: CMX／ICMS 生態系很可能包含 Dell Technologies。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 320/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0239::SPLIT04
Claim: CMX／ICMS 生態系很可能包含 NetApp。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 321/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0239::SPLIT05
Claim: CMX／ICMS 生態系很可能包含 VAST Data。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Power Delivery
The power delivery module sits above the BlueField-4 module. The module receives 50V power from the internal busbar cable. Then the current is stepped down to 12V with a modular power brick. Then, 12V current is delivered to the Orchid module, the BlueField-4 module, the management modules via smaller internal busbars.
Atomic Claim 322/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0240
Claim: VR NVL72 的供電模組位於 BlueField-4 模組上方。
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Atomic Claim 323/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0241
Claim: VR NVL72 的供電模組從內部匯流排纜線接收 50V 電力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 324/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0242
Claim: 在 VR NVL72 運算托盤的供電路徑中，模組化電源磚將電壓降至 12V。
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Atomic Claim 325/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0243::SPLIT01
Claim: VR NVL72 電源模組透過較小的內部匯流排，向 Orchid 模組供應 12V 電力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 326/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0243::SPLIT02
Claim: VR NVL72 電源模組透過較小的內部匯流排，向 BlueField-4 模組供應 12V 電力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 327/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0243::SPLIT03
Claim: VR NVL72 電源模組透過較小的內部匯流排，向管理模組供應 12V 電力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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System Management
The management module is made up of multiple smaller management modules that fall under this category. These modules occupy a long slim space between the BlueField-4 module and the right-side Orchid modules. The management modules are the following:
Atomic Claim 328/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0244
Claim: VR NVL72 的管理模組類別包含多個較小的管理模組。
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Atomic Claim 329/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0245
Claim: 這些 management modules 位於 BlueField-4 module 與右側 Orchid modules 之間的一條狹長空間。
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- System Management Module (SMM)
Atomic Claim 330/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0247
Claim: VR NVL72 的管理模組類別包含系統管理模組（SMM）。
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- Trusted Platform Module (TPM)
Atomic Claim 331/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0248
Claim: 其中包含 Trusted Platform Module（TPM）。
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- Datacenter Secure Control Module (DC-SCM)
Atomic Claim 332/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0249
Claim: VR NVL72 的管理模組類別包含資料中心安全控制模組（DC-SCM）。
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These modules provide management security functions over the compute tray. Hyperscalers usually have their own in-house management module design. Therefore, the management modules may be different for each end customer. Besides BlueField-4, the power delivery module and the management modules are the only other two components within the compute tray that Nvidia allows customization for. Some end customers are considering integrating the management modules into the power delivery module.
Nevertheless, the modules need to follow the form factor that Nvidia provides so it can fit into the designated connector on the compute tray midplane.
Atomic Claim 333/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0250
Claim: 這些 modules 為 compute tray 提供 management 與 security functions。
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Atomic Claim 334/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0251
Claim: Hyperscalers 通常有自家的 management module 設計。
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Atomic Claim 335/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0252
Claim: VR NVL72 管理模組的設計可依終端客戶而異。
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Atomic Claim 336/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0253
Claim: 除了 BlueField-4 之外，power delivery module 與 management modules 是 compute tray 內另外兩種 Nvidia 允許客製化的 components。
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Atomic Claim 337/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0254
Claim: 部分 VR NVL72 客戶正在考慮將管理模組整合進供電模組。
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Atomic Claim 338/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0255
Claim: 不過，這些 modules 仍必須遵循 Nvidia 提供的 form factor，才能裝入 compute tray midplane 上指定的 connector。
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Compute Tray Topology
The compute tray topology of VR NVL72 is roughly similar to that of GB200 and GB300. The three main differences to Grace Blackwell are the connections between GPU and ConnectX NICs, the connections to the local NVMe storage, and the connection between the BlueField-4 and ConnectX-9.
Atomic Claim 339/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0256
Claim: VR NVL72 的 compute tray topology 與 GB200、GB300 大致相似。
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Atomic Claim 340/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0257::SPLIT01
Claim: 相較 Grace Blackwell，VR NVL72 改變了 GPU 與 ConnectX NIC 之間的連接方式。
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Atomic Claim 341/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0257::SPLIT02
Claim: 相較 Grace Blackwell，VR NVL72 改變了本地 NVMe 儲存裝置的連接方式。
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Atomic Claim 342/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0257::SPLIT03
Claim: 相較 Grace Blackwell，VR NVL72 改變了 BlueField-4 與 ConnectX-9 之間的連接方式。
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Firstly, the connection between the GPU and the ConnectX NICs evolved from GB200 to GB300 then to Vera Rubin. For GB200, the GPU does not have direct access to the ConnectX-7. Instead, B200 connects to Grace CPU via C2C connection then the Grace CPU talks to the ConnectX-7 over PCIe 5. For GB300, Nvidia introduced NIC direct to ConnectX-8, which allows the B300 GPU to communicate directly with the ConnectX-8 NIC without going through the Grace CPU.
Atomic Claim 343/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0258
Claim: 首先，GPU 與 ConnectX NICs 之間的連線，從 GB200 到 GB300，再到 Vera Rubin 持續演進。
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Atomic Claim 344/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0259
Claim: 在 GB200 中，GPU 無法直接存取 ConnectX-7。
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Atomic Claim 345/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0260
Claim: 相反地，B200 先透過 C2C connection 連到 Grace CPU，再由 Grace CPU 透過 PCIe 5 與 ConnectX-7 通訊。
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Atomic Claim 346/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0261
Claim: 在 GB300 中，Nvidia 導入 NIC direct to ConnectX-8，使 B300 GPU 可直接與 ConnectX-8 NIC 通訊，不需經過 Grace CPU。
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Essentially, this means ConnectX-8 has two hosts, Grace CPU and B300 GPU. This improves latency in the backend network. However, for VR NVL72, the direct connection between Rubin GPU and ConnectX-9 is reverted back to the same design as GB200, as Rubin does not have PCIe bandwidth for two ConnectX-9. Rubin connects to Vera via C2C link, then Vera will connect to ConnectX-9 via PCIe6 lanes.
Atomic Claim 347/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0262
Claim: 這代表 ConnectX-8 有兩個 hosts：Grace CPU 與 B300 GPU。
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Atomic Claim 348/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0263
Claim: 所述 Astra 管理工作卸載旨在改善 VR NVL72 後端網路延遲。
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Atomic Claim 349/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0264
Claim: 但在 VR NVL72 中，Rubin GPU 與 ConnectX-9 的 direct connection 又回到與 GB200 相同的設計，因為 Rubin 沒有足夠的 PCIe bandwidth 供兩個 ConnectX-9 使用。
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Atomic Claim 350/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0265
Claim: Rubin 先透過 C2C link 連到 Vera，再由 Vera 透過 PCIe6 lanes 連到 ConnectX-9。
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Secondly, the local NVMe storage for Rubin has been moved to a different location from that of NVMe storage in Grace Blackwell. Previously, local NVMe storage was managed by BlueField-3. For VR NVL72, the local NVMe storage is physically on the Orchid module managed by the ConnectX-9.
Atomic Claim 351/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0266
Claim: 第二，Rubin 的 local NVMe storage 已移到與 Grace Blackwell 中 NVMe storage 不同的位置。
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Atomic Claim 352/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0267
Claim: 過去，local NVMe storage 由 BlueField-3 管理。
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Atomic Claim 353/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0268::SPLIT01
Claim: VR NVL72 的本地 NVMe 儲存裝置實際位於 Orchid 模組上。
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Atomic Claim 354/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0268::SPLIT02
Claim: ConnectX-9 管理 VR NVL72 的本地 NVMe 儲存裝置。
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Lastly, the BlueField-4 DPU is able to control the 8 ConnectX-9 backend NICs allowing for unified management of both front end north-south network & back end high speed East-West networks. This system, known as Advanced Secure Trusted Resource Architecture (Astra), thus takes the provisioning and monitoring load off of the host CPU. The only issue with this is that BlueField-4 is expensive, so we expect most hyperscale customers to deploy their in-house DPU solutions instead.
Atomic Claim 355/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0269::SPLIT01
Claim: BlueField-4 DPU 可控制八張 ConnectX-9 後端 NIC。
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Atomic Claim 356/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0269::SPLIT02
Claim: BlueField-4 對後端 NIC 的控制，讓前端南北向網路與後端高速東西向網路得以統一管理。
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Atomic Claim 357/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0270
Claim: 這套稱為 Advanced Secure Trusted Resource Architecture（Astra）的 system，會把 provisioning 與 monitoring 負載從 host CPU 移開。
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Atomic Claim 358/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0271
Claim: 問題在於 BlueField-4 成本高，因此 SemiAnalysis 預期多數 hyperscale customers 會改用自家的 DPU solutions。
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Evolution from Blackwell
All of these modules in the VR NVL72 compute tray, while not exactly the same, are found in the compute tray of GB200/300. The only difference is the midplane module as it is a new component introduced to eliminate internal cables form the compute tray. Also, the modules at the front of the chassis (daughter modules) are much longer than their equivalent in Blackwell to connect the signal from the midplane to the front I/O ports via PCB.
In the sections below we will discuss the cableless design, the changes in thermal design, and the changes in mechanical design in the compute tray.
Atomic Claim 359/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0272
Claim: VR NVL72 compute tray 裡的這些 modules 雖然不完全相同，但在 GB200/300 的 compute tray 中也都找得到對應元件。
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Atomic Claim 360/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0273
Claim: 唯一的差異是 midplane module；它是新加入的 component，用來消除 compute tray 內部 cables。
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Atomic Claim 361/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0274
Claim: 此外，chassis 前端的 daughter modules 比 Blackwell 中的對應模組長得多，以便透過 PCB 把 midplane 的 signal 接到前端 I/O ports。
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Compute Tray Cableless Design
As mentioned above the VR NVL72 compute tray is designed around the cableless concept. There are two reasons for this design. First, flyover cables present multiple different points of failure as they can easily be damaged during assembly.
Second, the high-density design of VR NVL72 leaves limited space for cables to be routed.
Atomic Claim 362/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0277
Claim: 如前所述，VR NVL72 compute tray 是以 cableless concept 為核心設計。
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Atomic Claim 363/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0279
Claim: 第一，flyover cables 有多個不同的 failure points，因為它們在 assembly 過程中很容易受損。
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Atomic Claim 364/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0280
Claim: 第二，VR NVL72 的 high-density design 留給 cable routing 的空間有限。
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Replacing Internal Cables with Board-to-Board Connectors
For the GB200/300, the most valuable cable that is exclusively supplied by Amphenol is the DensiLink OverPass cable set within the compute tray. This cable provides the ethernet connection between the CX-7/8 NIC and the OSFP cages. However, this cable is extremely vulnerable to scratches and damage of the cable termination during assembly, thereby creating many points of failure. There are also several other lower-end PCIe cables in use (MCIO and SlimSAS) that also suffer from the same points of failure.
These cables involve many other suppliers as well—complicating procurement and vendor management. Given the delicate nature of the cable, workers must be extremely careful while placing the cables in a very dense and compact chassis, which prolongs assembly time.
Atomic Claim 365/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0281
Claim: 在 GB200/300 中，compute tray 內最有價值、由 Amphenol 獨家供應的 cable 是 DensiLink OverPass cable set。
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Atomic Claim 366/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0282
Claim: 這條 cable 提供 CX-7/8 NIC 與 OSFP cages 之間的 Ethernet connection。
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Atomic Claim 367/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0283
Claim: GB300 的 DensiLink OverPass 纜線在組裝時容易刮傷或端接受損，形成故障點。
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Atomic Claim 368/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0284
Claim: 另外也使用多種較低階的 PCIe cables（MCIO、SlimSAS），同樣存在這些 failure points。
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Atomic Claim 369/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0285
Claim: GB300 運算托盤使用的纜線類型涉及多家供應商，使採購與供應商管理更複雜。
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Atomic Claim 370/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0286
Claim: 由於 cable 很脆弱，工人在非常 dense、compact 的 chassis 中放置 cables 時必須格外小心，因而拉長 assembly time。
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Although a cableless design might initially appear unfavorable for Amphenol, it is in fact a positive. Signals between the Strata module and the daughter modules still need a physical interconnect. In this architecture, those signals exit the Strata board through Amphenol’s PaladinHD2 board-to-board connectors. The signal is then routed through a PCB midplane sitting in the middle of the chassis.
On the other side of the PCB midplane, the daughter modules connect to the PCB midplane via another set of Paladin HD2 B2B connectors.
Atomic Claim 371/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0287
Claim: 原文判斷：雖然 cableless design 初看可能對 Amphenol 不利，但實際上反而是正面因素，因為 Strata module 與 daughter modules 之間的 signals 仍需要 physical interconnect。
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Atomic Claim 372/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0288
Claim: 在這個 architecture 中，signals 會從 Strata board 經由 Amphenol 的 PaladinHD2 board-to-board connectors 離開。
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Atomic Claim 373/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0289
Claim: 接著 signal 會經過位於 chassis 中央的 PCB midplane。
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Atomic Claim 374/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0290
Claim: 在 PCB midplane 另一側，daughter modules 透過另一組 Paladin HD2 B2B connectors 連到 PCB midplane。
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Atomic Claim 375/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-BW-CON-COMPARE
Claim: Amphenol 內容表列出，每個 GB300 運算托盤配置四條 DensiLink Overpass flyover 纜線。
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Atomic Claim 376/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CON-COMPARE
Claim: Amphenol 內容表列出，每個 VR NVL72 運算托盤配置 22 個 Paladin HD2 板對板連接器。
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Relocating ConnectX-9
To accommodate this cableless design, the CX-9 NICs, that would have been on the Strata modules, are relocated to the Orchid module (from the back half to the front half of the chassis).
Atomic Claim 377/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0291
Claim: 為了配合 cableless design，原本會放在 Strata modules 上的 CX-9 NICs 被移到 Orchid module，也就是從 chassis 後半部移到前半部。
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For the GB200/GB300, the PCIe signal distance between the GPU/CPU and the CX-7/8 is shorter than the Ethernet/InfiniBand signal distance between the CX-7/8 and the OSFP cages. Previously—having to transmit a 200G Ethernet/InfiniBand signal from the NIC in the back half of the compute tray to the OSFP cage in the front of the compute tray necessitated the use of flyover cables as the signal loss over PCB at 200Gbit/s (uni-directional) per lane is too high.
Atomic Claim 378/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0292
Claim: 在 GB200／GB300 中，GPU／CPU 到 CX-7/8 的 PCIe signal 距離，比 CX-7/8 到 OSFP cages 的 Ethernet／InfiniBand signal 距離更短。
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Atomic Claim 379/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0293
Claim: 過去，從 compute tray 後半部的 NIC，把 200G Ethernet／InfiniBand signal 傳到前端 OSFP cage 時，必須使用 flyover cables，因為 PCB 上每 lane 200Gbit/s（uni-directional）的 signal loss 太高。
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But now that the NIC is closer to the OSFP cage, the lower speed PCIe Gen6 signal (64Gbit/s per lane uni-directional) travels the longer distance. By making the PCIe Gen6 signal longer, the signal can travel over PCB given that PCIe Gen6 has better signal integrity than the higher speed 200G Ethernet/InfiniBand signal.
Atomic Claim 380/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0294
Claim: 現在 NIC 更靠近 OSFP cage，因此較低速的 PCIe Gen6 signal（每 lane 64Gbit/s、uni-directional）改為走較長距離。
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Atomic Claim 381/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0295
Claim: 把 PCIe Gen6 signal 的路徑拉長後，仍可讓 signal 走 PCB，因為 PCIe Gen6 的 signal integrity 優於更高速的 200G Ethernet／InfiniBand signal。
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PCB vs Flyover Cables
Nevertheless, it is still challenging to drive a PCIe Gen6 signal over around 500mm of PCB distance from the Strata Module to the front of the Orchid Module. In addition to having high quality SerDes, proper signal integrity is still achievable by upgrading PCB materials.
Atomic Claim 382/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0296
Claim: 即便如此，要讓 PCIe Gen6 signal 從 Strata Module 經約 500mm 的 PCB 距離走到 Orchid Module 前端，仍然很有挑戰。
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Atomic Claim 383/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0297
Claim: 除了需要高品質 SerDes，透過升級 PCB materials，仍可達成適當的 signal integrity。
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First, we must understand why high-speed signals perform worse on PCB versus flyover cables. As SerDes rates increase, high-speed channels become increasingly constrained by insertion loss introduced by PCB traces, vias, dielectric materials and conductor roughness. Insertion loss is defined as the signal power that is lost as a signal is traveling through an interconnect channel.
Atomic Claim 384/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0299::SPLIT01
Claim: 隨著 SerDes 速率提高，PCB 走線造成的插入損耗對高速通道的限制日益加重。
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Atomic Claim 385/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0299::SPLIT02
Claim: 隨著 SerDes 速率提高，導通孔造成的插入損耗對高速通道的限制日益加重。
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Atomic Claim 386/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0299::SPLIT03
Claim: 隨著 SerDes 速率提高，介電材料造成的插入損耗對高速通道的限制日益加重。
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Atomic Claim 387/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0299::SPLIT04
Claim: 隨著 SerDes 速率提高，導體粗糙度造成的插入損耗對高速通道的限制日益加重。
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Atomic Claim 388/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0300
Claim: Insertion loss 定義為 signal 通過 interconnect channel 時損失的 signal power。
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Atomic Claim 389/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCL-FILLER
Claim: CCL 組成示意圖將填料描述為絕緣層的一部分，用以提供穩定性。
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Atomic Claim 390/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCL-FOIL
Claim: CCL 組成示意圖將銅箔標示為導電層。
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The three main mechanisms contributing to insertion loss in a PCB channel are conductor loss from skin effect and copper surface roughness, dielectric loss from laminate absorption, and geometry loss from discontinuities such as vias and layer changes.
Atomic Claim 391/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0301::SPLIT01
Claim: 集膚效應與銅表面粗糙度造成的 PCB 導體損耗，是插入損耗的來源之一。
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Atomic Claim 392/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0301::SPLIT02
Claim: 基材吸收造成的 PCB 介電損耗，是插入損耗的來源之一。
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Atomic Claim 393/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0301::SPLIT03
Claim: 導通孔與換層等不連續結構造成的 PCB 幾何損耗，是插入損耗的來源之一。
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Atomic Claim 394/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-SKIN
Claim: 所引用的訊號損耗投影片將集膚深度表示為 1/sqrt(pifmu*sigma)。
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Conductor loss is driven by copper surface roughness. As signals travel down the copper traces in the PCB, energy is lost due to the resistance in copper. At higher frequencies, the signal traveling through the copper crowds toward the surface of the trace, which is known as the skin effect. On top of the natural resistance of copper, if the surface is rough, the current will not travel along a uniform path incurring more resistance and loss.
Atomic Claim 395/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0302
Claim: Conductor loss 主要由 copper surface roughness 驅動。
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Atomic Claim 396/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0303
Claim: Signal 沿 PCB 的 copper traces 傳輸時，會因 copper 的電阻而損失能量。
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Atomic Claim 397/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0304
Claim: 在更高頻率下，signal 在 copper 中傳輸時會往 trace 表面集中，這種現象稱為 skin effect。
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Atomic Claim 398/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0305
Claim: 除了 copper 本身的電阻之外，如果表面粗糙，current 會沿不均勻路徑傳輸，進一步增加 resistance 與 loss。
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Dielectric loss is driven by the energy absorption nature of the dielectric materials. Dielectric materials, resins and glass fiber cloth, provide insulation and mechanical reinforcement function for the PCB traces. At high frequency, high-speed signal doesn’t simply travel through the copper traces, the signal travels as an electromagnetic wave with electric field extending into the dielectric materials.
As the signal propagates, the dielectric absorbs a portion of the energy and dissipates as heat, contributing to insertion loss. Dielectric loss scales with frequency, hence dielectric loss is a dominant limiter of signal performance of long reach PCB traces.
Atomic Claim 399/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0306
Claim: Dielectric loss 來自 dielectric materials 吸收能量的特性。
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Atomic Claim 400/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT01
Claim: 介電材料為 PCB 走線提供絕緣。
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Atomic Claim 401/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT02
Claim: 介電材料為 PCB 走線提供機械補強。
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Atomic Claim 402/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT03
Claim: 樹脂為 PCB 走線提供絕緣。
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Atomic Claim 403/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT04
Claim: 樹脂為 PCB 走線提供機械補強。
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Atomic Claim 404/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT05
Claim: 玻璃纖維布為 PCB 走線提供絕緣。
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Atomic Claim 405/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT06
Claim: 玻璃纖維布為 PCB 走線提供機械補強。
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Atomic Claim 406/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0308
Claim: 在高頻下，high-speed signal 不只是沿 copper traces 傳輸，而是以 electromagnetic wave 形式傳播，其 electric field 會延伸進 dielectric materials。
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Atomic Claim 407/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0309
Claim: Signal 傳播時，dielectric 會吸收部分能量並以熱的形式耗散，進而造成 insertion loss。
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Atomic Claim 408/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0310
Claim: Dielectric loss 會隨 frequency 上升，因此是 long-reach PCB traces signal performance 的主要限制因素。
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Geometry loss describes the insertion loss incurred from abrupt structures of the PCB traces. Real PCB channels include many abrupt structures, such as vias and layer swaps. These are like bumps in a highway, and signals could reflect backward and be interrupted increasing insertion loss.
Atomic Claim 409/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0311
Claim: Geometry loss 指的是 PCB traces 中 abrupt structures 所造成的 insertion loss。
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Atomic Claim 410/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0312
Claim: 實際的 PCB channels 含有許多 abrupt structures，例如 vias 與 layer swaps。
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Atomic Claim 411/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0314
Claim: PCB 訊號路徑上的導通孔與換層可能造成訊號反射與中斷，增加插入損耗。
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Another factor that affects signal performance is cross-talk. Given the increase in the number of I/Os per GPU, lane density in the PCB also increases. Cross-talk describes the scenario where the copper traces are too close to each other and the signal from one lane affects the signal in a neighboring lane. Some copper traces are designed for power as well. When the power lanes are too close to the signal lanes, noise from the power lanes can also modulate the signal as well.
Atomic Claim 412/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0315
Claim: 另一個影響 signal performance 的因素是 cross-talk。
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Atomic Claim 413/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0316
Claim: 隨著每顆 GPU 的 I/O 數量增加，PCB 的 lane density 也會提高。
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Atomic Claim 414/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0317
Claim: Cross-talk 指的是 copper traces 太靠近時，一條 lane 的 signal 會影響相鄰 lane signal 的情況。
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Atomic Claim 415/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0318
Claim: 部分 copper traces 也被設計用來傳輸 power。
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Atomic Claim 416/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0319
Claim: 當 power lanes 與 signal lanes 太靠近時，power lanes 的 noise 也可能調變 signal。
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In conclusion, insertion loss scales with signal frequency, and high-speed signal suffers more insertion loss from PCB than from fly over cables. Hence, as traditional CPU servers upgrade to higher signaling frequencies such as upgrading to newer PCIe generations, the CPU server design increases the adoption of fly over cables to compensate for insertion loss from the PCB.
The alternative solution would be upgrading PCB materials, however, fly over cables are more cost effective and remain feasible for traditional server applications.
Atomic Claim 417/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0320::SPLIT01
Claim: 插入損耗隨訊號頻率增加而提高。
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Atomic Claim 418/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0320::SPLIT02
Claim: 高速訊號在 PCB 上的插入損耗高於 flyover 纜線。
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Atomic Claim 419/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0321
Claim: 因此，traditional CPU servers 升級到更高 signaling frequencies、例如新版 PCIe generations 時，會增加採用 flyover cables，以補償 PCB 的 insertion loss。
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Atomic Claim 420/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0322::RESEG01
Claim: 相對於採用 flyover cables，另一種處理 PCB insertion loss 的方案是升級 PCB materials。
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Atomic Claim 421/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0322::RESEG02
Claim: 對 traditional server applications 而言，flyover cables 相較升級 PCB materials 更具成本效益。
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Atomic Claim 422/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0323::RESEG01
Claim: flyover cables 在 traditional server applications 中仍然可行。
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For VR NVL72, the design has turned toward cableless given the higher density and manufacturing complexity of AI server. The cost saved on improving higher manufacturing yields and assembly time reduction more than offsets the higher cost of the upgraded PCB materials. It is critical that all the factors that contribute towards insertion loss in the PCB are mitigated, hence PCB material upgrades are necessary for VR NVL72.
Atomic Claim 423/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0324
Claim: 對 VR NVL72 而言，由於 AI server 的 density 與 manufacturing complexity 更高，設計方向轉向 cableless。
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Atomic Claim 424/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0325
Claim: 提高 manufacturing yield 與縮短 assembly time 所節省的成本，足以超過升級 PCB materials 帶來的額外成本。
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Atomic Claim 425/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0326
Claim: 必須降低 PCB 中所有造成 insertion loss 的因素，因此 VR NVL72 必須升級 PCB materials。
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PCB Materials Upgrade and Area Growth
PCB content value in VR NVL72 will grow significantly compared to that of GB200/GB300. The two main drivers of this content growth are significant material upgrades and the notable increase of high-end PCB area and layers.
Atomic Claim 426/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0327
Claim: VR NVL72 的 PCB content value 相較 GB200／GB300 將顯著成長。
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Atomic Claim 427/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0328::RESEG01
Claim: VR NVL72 的 PCB content growth 其中一個主要 driver 是顯著的 material upgrades。
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Atomic Claim 428/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0329::RESEG01
Claim: VR NVL72 的 PCB content growth 另一個主要 driver，是 high-end PCB area 與 layer count 顯著增加。
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On the material side, CCL content upgrades from M7 to M8/M9 drives material upgrades. Copper foil is upgraded to HVLP4 across the board for the main compute and networking boards. A glass fiber cloth upgrade is necessary to reduce dielectric loss, but whether quartz cloth (Q glass) is necessary remains a debate. Below let’s discuss the materials upgrade and the key considerations behind the adoption of each material.
Atomic Claim 429/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0330
Claim: 在 material 方面，CCL content 從 M7 升級到 M8/M9，帶動 material upgrade。
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Atomic Claim 430/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0331
Claim: 在 VR NVL72 的板材升級中，主要運算板與網路板採用 HVLP4 銅箔。
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Atomic Claim 431/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0332
Claim: 為降低 dielectric loss，需要升級 glass fiber cloth。
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Atomic Claim 432/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0333
Claim: VR NVL72 板材是否需要石英布（Q glass），仍有爭議。
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Atomic Claim 433/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCL-NVSwitch
Claim: 2 月的 VR NVL72 CCL 表將 NVSwitch 規格列為 M8.5（HVLP4、LDK2）。
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Atomic Claim 434/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCL-Strata
Claim: 2 月的 VR NVL72 CCL 表將 Strata／HPM 規格列為 M8.5／M6（HVLP4、LDK2）。
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Atomic Claim 435/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCLSUP-HPM
Claim: 2 月的表格將 Doosan 列為 VR NVL72 HPM 的 CCL 供應商。
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Atomic Claim 436/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCLSUP-NVSwitch
Claim: 2 月的表格將 EMC 列為 VR NVL72 NVSwitch 的 CCL 供應商。
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Atomic Claim 437/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCLSUP-daughter
Claim: 2 月的表格將 EMC 列為 VR NVL72 子板／周邊板的 CCL 供應商。
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Atomic Claim 438/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCLSUP-midplane
Claim: 2 月的表格將 EMC 列為 VR NVL72 中板的 CCL 供應商。
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Atomic Claim 439/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-GPU_ABF_AREA
Claim: 2 月的表格將 VR NVL72 GPU ABF 面積列為 8,051mm²。
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Atomic Claim 440/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-GPU_ABF_LAYERS
Claim: 2 月的表格將 VR NVL72 GPU ABF 層數列為 18 層。
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Atomic Claim 441/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCB-NVSwitch
Claim: 2 月的 VR NVL72 PCB 表將 NVSwitch 列為 32L PTH。
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Atomic Claim 442/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCB-Strata
Claim: 2 月的 VR NVL72 PCB 表將 Strata／HPM 列為 26L HDI（6+14+6）。
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Atomic Claim 443/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCB-daughter
Claim: 2 月的 VR NVL72 PCB 表將子板／周邊板列為 20L PTH。
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Atomic Claim 444/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCB-midplane
Claim: 2 月的 VR NVL72 PCB 表將中板列為 44L PTH。
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Atomic Claim 445/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-HPM-Unimicron
Claim: 2 月的表格將 Unimicron 列為 VR NVL72 HPM 的 PCB 供應商。
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Atomic Claim 446/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-HPM-VGT
Claim: 2 月的表格將 VGT 列為 VR NVL72 HPM 的 PCB 供應商。
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Atomic Claim 447/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-NVSwitch-ISU
Claim: 2 月的表格將 ISU 列為 VR NVL72 NVSwitch 的 PCB 供應商。
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Atomic Claim 448/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-NVSwitch-TTM
Claim: 2 月的表格將 TTM 列為 VR NVL72 NVSwitch 的 PCB 供應商。
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Atomic Claim 449/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-NVSwitch-WUS
Claim: 2 月的表格將 WUS 列為 VR NVL72 NVSwitch 的 PCB 供應商。
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Atomic Claim 450/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-daughter-ISU
Claim: 2 月的表格將 ISU 列為 VR NVL72 子板／周邊板的 PCB 供應商。
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Atomic Claim 451/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-daughter-TTM
Claim: 2 月的表格將 TTM 列為 VR NVL72 子板／周邊板的 PCB 供應商。
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Atomic Claim 452/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-daughter-WUS
Claim: 2 月的表格將 WUS 列為 VR NVL72 子板／周邊板的 PCB 供應商。
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Atomic Claim 453/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-midplane-ISU
Claim: 2 月的表格將 ISU 列為 VR NVL72 中板的 PCB 供應商。
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Atomic Claim 454/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-midplane-TTM
Claim: 2 月的表格將 TTM 列為 VR NVL72 中板的 PCB 供應商。
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Atomic Claim 455/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-midplane-WUS
Claim: 2 月的表格將 WUS 列為 VR NVL72 中板的 PCB 供應商。
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The classification of CCL materials is determined by its dielectric constant (Dk) and dissipation factor (Df) at a given frequency. Insertion loss is lower at lower Dk and Df value. The common classification is anchored to the Megtron series from Panasonic as they have been setting the industry standard. When people describe the CCL as M7 classification it usually means it matches the same Dk and Df specifications as Megtron 7 of Panasonic.
Atomic Claim 456/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0335
Claim: CCL materials 的 classification，是依特定 frequency 下的 dielectric constant（Dk）與 dissipation factor（Df）決定。
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Atomic Claim 457/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0336
Claim: Dk 與 Df 越低，insertion loss 也越低。
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Atomic Claim 458/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0337
Claim: 業界常見的 classification 以 Panasonic 的 Megtron series 為基準，因為該系列一直在設定 industry standard。
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Atomic Claim 459/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0338
Claim: 當 CCL 被描述為 M7 classification，通常代表其 Dk 與 Df specifications 與 Panasonic Megtron 7 相同。
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Copper foil content in Rubin is upgraded from HVLP2 to HVLP4 grade copper foil for the signal layers. As discussed earlier, due to the skin effect, smoother copper foil equals to lower insertion loss. HVLP is the classification of copper foil standing for Ultra-Low Profile Copper Foil. The higher the HVLP grade equals to lower surface roughness.
Atomic Claim 460/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0339
Claim: Rubin 的 signal layers 將 copper foil 從 HVLP2 升級到 HVLP4 grade。
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Atomic Claim 461/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0340
Claim: 如前述 skin effect 所示，copper foil 越平滑，insertion loss 越低。
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Atomic Claim 462/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0341
Claim: HVLP 是 copper foil 的 classification，代表 Ultra-Low Profile Copper Foil。
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Atomic Claim 463/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0342
Claim: HVLP grade 越高，surface roughness 越低。
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For the power layers, the additional layers in Strata compared to Blackwell are mostly power layers to accommodate more power going into the GPU. By adding more dedicated power layers, cross talk is reduced as power layers and signal layers are separated. Power layer copper foils are much thicker to insulate the current travelling through it.
Atomic Claim 464/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0364
Claim: 關於 PCB：增加 dedicated power layers 並把 power layers 與 signal layers 分離，可降低 cross-talk。
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Atomic Claim 465/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0343
Claim: 在 power layers 方面，Strata 相較 Blackwell 增加的 layers 多數是 power layers，用來承載更多送入 GPU 的 power。
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Atomic Claim 466/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0346
Claim: 來源將電源層銅箔描述為較厚，以「隔離電流」；此處保留來源措辭，不視為已驗證的電學解釋。
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The glass fiber cloth upgrade aims to reduce the dielectric constant of CCL. Beside glass fiber cloth, resin is also a key factor contributing to dielectric constant. To achieve a desirable dielectric constant, the CCL makers have their unique recipes to their formulation of the two dielectric materials in the CCL. Currently, debate around the CCL spec is around the adoption of Quartz cloth (Q glass).
Atomic Claim 467/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0347
Claim: Glass fiber cloth upgrade 的目標是降低 CCL 的 dielectric constant。
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Atomic Claim 468/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0348
Claim: 除了 glass fiber cloth 之外，resin 也是影響 dielectric constant 的重要因素。
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Atomic Claim 469/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0349
Claim: 為了達到理想的 dielectric constant，各家 CCL makers 對 CCL 中兩種 dielectric materials 的配方都有自己的 recipe。
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Atomic Claim 470/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0350
Claim: 目前 CCL spec 的主要爭議在於是否採用 Quartz cloth（Q glass）。
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Quartz cloth is the next generation material that replaces the glass fiber cloth materials as the reinforcing layer, pushing dielectric constant even lower. Besides lower dielectric constant, quartz cloth also has the benefits of being stronger, more temperature resistance, and having a lower CTE. On the other hand, the cost is multiples higher than that of the highest-grade glass fiber cloth and is much harder to process at the PCB manufacturing level, leading to worse yield.
Atomic Claim 471/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0371
Claim: 來源指出，石英布的強度高於玻璃纖維布。
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Atomic Claim 472/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0372
Claim: 來源指出，石英布比玻璃纖維布更耐高溫。
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Atomic Claim 473/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0373
Claim: 來源指出，石英布的熱膨脹係數（CTE）低於玻璃纖維布。
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Atomic Claim 474/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0351
Claim: Quartz cloth 是下一代 reinforcing-layer material，可取代 glass fiber cloth，並把 dielectric constant 進一步降低。
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Atomic Claim 475/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0354
Claim: 另一方面，quartz cloth 成本是 highest-grade glass fiber cloth 的數倍。
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Atomic Claim 476/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0355
Claim: Quartz cloth is harder to process at the PCB manufacturing level than the highest-grade glass fiber cloth, leading to worse yield.
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Within VR NVL72, Quartz is initially adopted for the Orchid board and the midplane to allow the longest distance PCIe Gen 6 signal traveling through these two boards with as little insertion loss as possible. However, given the cost of the Quartz cloth and the difficulty in Q cloth processing, Nvidia is currently exploring the option of downgrading back to glass fiber cloth. The final decision is pending on the signal performance with the downgraded glass fiber cloth.
Atomic Claim 477/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0356::RESEG01
Claim: 在 VR NVL72 中，Quartz cloth 最初用於 Orchid board。
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Atomic Claim 478/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0356::RESEG02
Claim: 在 VR NVL72 中，Quartz cloth 最初用於 midplane。
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Atomic Claim 479/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0357::RESEG01
Claim: VR NVL72 在 Orchid board 與 midplane 最初採用 Quartz cloth，是為了讓最長距離的 PCIe Gen 6 signal 穿過這兩塊 boards 時，insertion loss 盡可能低。
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Atomic Claim 480/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0358
Claim: 不過考量 Quartz cloth 的成本與 Q-cloth processing 難度，Nvidia 目前正在評估降回 glass fiber cloth 的方案。
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Atomic Claim 481/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0359
Claim: VR NVL72 採用石英布或玻璃布的材料決策，仍待使用降規玻璃布進行訊號效能測試的結果。
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Beside material upgrade, the other driver of PCB content value is the increase of high end PCB area coverage. In Grace Blackwell, the only boards with high end material are the Bianca board with M7 grade CCL and the NVSwitch board with M8 grade CCL, leaving front half of the compute tray uncovered by high end PCB board. For VR NVL72, the Orchid board and the midplane board increases the high end PCB board area in the compute tray covering the front half of the chassis.
With the Strata board bigger than the Bianca board and the extra peripheral boards in the compute tray, we estimate that the area of high end PCB board increases by ~2.3 times from GB300 to VR NVL72. The Orchid board is the main contributor to the delta of total high-end PCB area between GB300 and VR NVL72 rack.
Atomic Claim 482/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0360
Claim: 除了 material upgrade，PCB content value 的另一個驅動因素是 high-end PCB area coverage 增加。
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Atomic Claim 483/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0361::SPLIT01
Claim: 在 Grace Blackwell 中，Bianca 板使用 M7 等級 CCL。
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Atomic Claim 484/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0361::SPLIT02
Claim: 在 Grace Blackwell 中，NVSwitch 板使用 M8 等級 CCL。
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Atomic Claim 485/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0361::SPLIT03
Atomic Claim 486/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0362
Claim: 對 VR NVL72 而言，Orchid board 與 midplane board 增加了 compute tray 的 high-end PCB board area，覆蓋 chassis 前半部。
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Atomic Claim 487/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0363
Claim: 由於 Strata board 比 Bianca board 更大，加上 compute tray 額外的 peripheral boards，SemiAnalysis 估計 high-end PCB board area 從 GB300 到 VR NVL72 增加約 2.3 倍。
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Atomic Claim 488/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0364
Claim: Orchid board 是 GB300 與 VR NVL72 rack 之間 total high-end PCB area 差異的主要貢獻者。
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Compute Tray: Thermal
VR NVL72 takes liquid cooling to the next level. The VR NVL72 compute tray is 100% liquid cooled, whereas GB200 and GB300 compute trays adopt a hybrid of 85% liquid cooling and 15% air cooling. As a result of this, fans are removed from the compute tray and the cold plate coverage increases to remove heat from the front half of the chassis. An internal manifold will be placed in the middle of the chassis to distribute inlet coolant to the various modules and to collect the outlet coolant.
Each of the modules within the compute tray will have a cold plate module attached. Each cold plate module connects to the internal manifolds via MQD (a smaller form factor quick disconnect specification standard by Nvidia for compact area application within the compute tray).
Atomic Claim 489/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0366
Claim: VR NVL72 compute tray 採 100% liquid cooling。
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Atomic Claim 490/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0367
Claim: GB200 與 GB300 compute trays 採用 85% liquid cooling、15% air cooling 的 hybrid cooling。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 491/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0368
Claim: 因此，compute tray 中的 fans 被移除。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 492/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0369
Claim: cold plate coverage 增加，以移除 chassis 前半部的熱。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 493/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0370
Claim: VR NVL72 運算托盤中央的內部分歧管，將入口冷卻液分配至各模組並收集出口冷卻液。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 494/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0371
Claim: compute tray 內每個 module 都會附上一個 cold plate module。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 495/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0372::SPLIT01
Claim: 每個 VR NVL72 冷板模組透過 MQD 連接內部分歧管。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 496/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0372::SPLIT02
Claim: MQD 是 Nvidia 為運算托盤內狹小區域制定的小型快速接頭規格。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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The coolant enters the compute tray via UQD from the left rear side of the chassis. Then, the coolant enters the internal manifold via a tube, where the coolant is distributed to all the modules. The coolant collects the heat from the different modules and re-enters the internal manifold. Finally, the coolant exits the compute tray via UQD at the rear right side of the chassis.
Atomic Claim 497/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0373
Claim: Coolant 從 chassis 左後側透過 UQD 進入 compute tray。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 498/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0374
Claim: 在 VR NVL72 中，冷卻液先經由管路進入內部分歧管，再分配至各模組。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 499/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0375
Claim: 在 VR NVL72 中，冷卻液吸收各模組的熱量後返回內部分歧管。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 500/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0376
Claim: 最後 coolant 從 chassis 右後側透過 UQD 離開 compute tray。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Several upgrades are also made on the cold plate for VR NVL72. For each Strata module, the cold plate will be provided as a single module covering the entire Strata board including two Rubin GPUs, one Vera CPU, SOCAMM modules, and the various VRM components. The cold plate of the Rubin GPU is upgraded to a “micro-channel cold plate” (MCCP). Essentially, the pitch between the channels in the cold plate is reduced to 100 micron from 150 micron.
This increases the surface area and increases the thermal dissipation capacity of the cold plate. Also, there will be a layer of gold plated on the surface contacting the Rubin GPU. The reason for this is to prevent corrosion of the copper from the liquid metal Indium TIM2.
Atomic Claim 501/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT01
Claim: Strata 冷板以單一模組形式提供，覆蓋整塊 Strata 板。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 502/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT02
Claim: 單一 Strata 冷板模組覆蓋兩顆 Rubin GPU。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 503/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT03
Claim: 單一 Strata 冷板模組覆蓋一顆 Vera CPU。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 504/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT04
Claim: 單一 Strata 冷板模組覆蓋 SOCAMM 模組。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 505/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT05
Claim: 單一 Strata 冷板模組覆蓋 VRM 元件。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 506/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0379
Claim: Rubin GPU 的 cold plate 升級為 micro-channel cold plate（MCCP）。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 507/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0380
Claim: Rubin 微流道冷板的流道間距由 150 微米縮小至 100 微米。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 508/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0381::RESEG01
Claim: 將 cold plate 的 channel pitch 從 150 micron 縮小到 100 micron，會增加其 surface area。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 509/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0382::RESEG01
Claim: 增加 surface area 會提高 cold plate 的 thermal dissipation capacity。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 510/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0383
Claim: 此外，與 Rubin GPU 接觸的表面會鍍上一層 gold。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 511/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0384
Claim: Rubin 冷板接觸面的鍍金可防止液態金屬銦 TIM2 腐蝕銅材。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Beyond the Strata module, the modules at the front of the chassis will also have a cold plate module attached. Each Orchid module will have a cold plate module covering the CX-9, the E1.S SSD, the transceiver cages and the various VRMs. The cold plate and the board will be less than 0.5U tall as two Orchid modules are stacked on top of each other in a 1U chassis. Each pair of Orchid modules shares only a pair of QD from the manifold.
There will be another set of manifolds that distribute the coolant to the top and the bottom cold plates for the pair of Orchid modules.
Atomic Claim 512/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0385
Claim: 除了 Strata module，chassis 前端的 modules 也會附上 cold plate module。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 513/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0386::SPLIT01
Claim: 每個 Orchid 模組的冷板覆蓋 CX-9。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 514/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0386::SPLIT02
Claim: 每個 Orchid 模組的冷板覆蓋 E1.S SSD。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 515/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0386::SPLIT03
Claim: 每個 Orchid 模組的冷板覆蓋收發器插槽。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 516/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0386::SPLIT04
Claim: 每個 Orchid 模組的冷板覆蓋 VRM。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 517/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0387
Claim: cold plate 與 board 的高度都會低於 0.5U，因為 2 個 Orchid modules 會上下堆疊在 1U chassis 中。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 518/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0388
Claim: 每一對 Orchid modules 只共用一對來自 manifold 的 QD。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 519/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0389
Claim: 另有一組 manifolds，將 coolant 分配到這對 Orchid modules 的上、下 cold plates。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Previously, cold plates were assembled at the L10 assembly level where the various components are put into place in the chassis. Given the modular approach, the cold plates need to be more tightly integrated with the module itself. Hence, the cold plate will be attached at the L6 assembly level right after the PCBA process. This increases the assembly efficiency as the assembly at L10 is simplified to slotting in the completed modules into the corresponding connectors and quick disconnects.
Atomic Claim 520/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0390
Claim: 過去 cold plates 是在 L10 assembly level 組裝，也就是把各種 components 裝入 chassis 的階段。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 521/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0391
Claim: 採用 modular approach 後，cold plates 必須與 module 本體更緊密整合。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 522/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0392
Claim: 因此，cold plate 會在 PCBA process 後、L6 assembly level 就先安裝。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 523/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0393
Claim: 這會提高 assembly efficiency，因為 L10 assembly 被簡化為把完成的 modules 插入對應 connectors 與 quick disconnects。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Compute Tray: Power Delivery
At the compute tray level, 50VDC power enters the compute tray via the busbar clips at the back of the chassis. Then power travels to the middle of the chassis via the internal busbar cables. From the internal busbar cables, the power path is split into three destinations. The first and second path goes to the left and the right Strata Board, where the internal busbar cable feeds 50VDC power to the Strata Board directly. The third path goes to the power distribution module at the front of the chassis.
The internal busbar cables will feed 50VDC power to a busbar device that travels under the PCB midplane to connect to the power distribution board (PDB) on the other side of the PCB midplane. This differs from Grace Blackwell, where 50VDC power goes directly to the PDB. Then, the PDB feeds 12VDC to all the boards in the compute tray.
Atomic Claim 524/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0394
Claim: 在 compute tray 層級，50VDC power 會透過 chassis 後方的 busbar clips 進入 compute tray。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 525/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0395
Claim: 接著 power 透過內部 busbar cables 傳到 chassis 中央。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 526/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0396
Claim: 從內部 busbar cables 開始，power path 分成三個 destinations。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 527/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0397
Claim: 第一、第二條 path 分別前往左、右 Strata Board，由內部 busbar cable 直接供應 50VDC power。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 528/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0398
Claim: VR NVL72 運算托盤的第三條供電路徑，供電給機箱前方的配電模組。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 529/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0399
Claim: Internal busbar cables 先提供 50VDC 給一個 busbar device；該 device 從 PCB midplane 下方穿過，連接到 midplane 另一側的 power distribution board（PDB）。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 530/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0400
Claim: 這與 Grace Blackwell 不同；在 Grace Blackwell 中，50VDC power 會直接送到 PDB。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 531/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0401
Claim: 接著 PDB 向 compute tray 中所有 boards 提供 12VDC。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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50VDC enters the Strata Board via one of the 50V power connectors on both sides of the Strata board. 50VDC is stepped down to 12VDC by the IBC module at the bottom of the Strata Board. Then the 12VDC will be stepped down to 1VDC by the VRM before feeding into the Rubin GPU and Vera CPU. Strata directly receives 50VDC whereas the Bianca board of Grace Blackwell receives 12VDC from the PDB.
As the Strata board draws around 4800W of power (equivalent to the TDP of half a general server rack) versus Bianca at 3000W, it is necessary to deliver power to the board at a higher voltage. The benefit of moving 50VDC-12VDC conversion closer is to the reduce current and increase transmission efficiency. 96 Amps at 50V has 17x lower power loss than 400A at 12V due to the quadratic relationship between power loss and current.
Atomic Claim 532/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0402
Claim: 50VDC 會透過 Strata Board 兩側的 50V power connectors 進入 Strata Board。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 533/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0403
Claim: 位於 Strata Board 底部的 IBC module 將 50VDC 降壓至 12VDC。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 534/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0404
Claim: 之後 VRM 再把 12VDC 降至 1VDC，供給 Rubin GPU 與 Vera CPU。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 535/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0405
Claim: Strata 直接接收 50VDC；相較之下，Grace Blackwell 的 Bianca board 從 PDB 接收 12VDC。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 536/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0406::SPLIT01
Claim: Strata 板功耗約為 4,800W，Bianca 則約為 3,000W。
Frame:ATTRIBUTE· Mode:ESTIMATED· Mapping:COMPLETE
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Atomic Claim 537/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0406::SPLIT02
Claim: 來源將 Strata 約 4,800W 的功耗，比擬為半個通用伺服器機櫃的 TDP。
Frame:ATTRIBUTE· Mode:ESTIMATED· Mapping:COMPLETE
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Atomic Claim 538/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0406::SPLIT03
Claim: Strata 的功耗高於 Bianca，因此需要以更高電壓向板端供電。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 539/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0407::SPLIT01
Claim: 將 50VDC 至 12VDC 的轉換位置移近 Strata，可降低傳輸電流。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 540/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0407::SPLIT02
Claim: 將 50VDC 至 12VDC 的轉換位置移近 Strata，可改善傳輸效率。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 541/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0408
Claim: 在 power loss 與 current 呈平方關係下，50V、96A 的 power loss 比 12V、400A 低 17 倍。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Power sloshing between Vera and Rubin is still present, a feature carried over from GB300. This enables more efficient power planning by sharing the 4800W provided amongst both GPU and CPU. In GPU demanding loads, 2300W goes to each GPU leaving 200W for the CPU. Vera can then dynamically boost to higher power when GPU demand drops to help minimize GPU idle time while not overprovisioning power.
Atomic Claim 542/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0409
Claim: Vera 與 Rubin 之間仍保留 power sloshing，這項 feature 從 GB300 延續而來。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 543/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0410
Claim: 這讓 4,800W power 可以在 GPU 與 CPU 間共享，提升 power planning efficiency。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 544/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0411
Claim: 在 GPU demand 高的負載下，每顆 GPU 分配 2,300W，剩下 200W 給 CPU。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 545/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0412
Claim: 當 GPU 需求下降時，Vera CPU 可動態提高功率，減少 GPU 閒置時間，而無需超額配置電力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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For the modules at the front of chassis—CX-9, BlueField-4, and management—the PDB feeds 12VDC of power to each of the modules. 50VDC is stepped down to 12VDC at the PDB then, via a copper busbar device, the PDB feeds 12VDC to its neighboring modules. The power connector of CX-9 is located near the Paladin HD2 at the top of the modules.
Atomic Claim 546/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0413::SPLIT01
Claim: PDB 向機箱前方的 CX-9 模組供應 12VDC 電力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 547/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0413::SPLIT02
Claim: PDB 向機箱前方的 BlueField-4 模組供應 12VDC 電力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 548/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0413::SPLIT03
Claim: PDB 向機箱前方的管理模組供應 12VDC 電力。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 549/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0414
Claim: PDB 先將 50VDC 降至 12VDC，再透過 copper busbar device，向鄰近 modules 供應 12VDC。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 550/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0415
Claim: CX-9 的 power connector 位於 module 頂部、靠近 Paladin HD2 的位置。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Compute Tray: Mechanical
The mechanical components of the VR NVL72 compute tray are slightly more sophisticated than that of the Grace Blackwell. At the front of the chassis, there is a mechanical structure that separates the front into three sections, with the left and right sections housing the Orchid modules and the middle sections housing the BlueField-4, the power delivery and the management modules. Each of the modules will also have a small metal chassis.
The mechanical structure provides a simple guiding mechanism that guides the modules to a blind mate process with the midplane and the internal manifolds.
Atomic Claim 551/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0416
Claim: VR NVL72 compute tray 的 mechanical components，比 Grace Blackwell 稍微更複雜。
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Atomic Claim 552/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT01
Claim: 一個機械結構將 VR NVL72 機箱前部分為三區。
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Atomic Claim 553/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT02
Claim: Orchid 模組位於 VR NVL72 機箱前部的左右兩區。
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Atomic Claim 554/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT03
Claim: BlueField-4 模組位於 VR NVL72 機箱前部的中間區。
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Atomic Claim 555/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT04
Claim: 供電模組位於 VR NVL72 機箱前部的中間區。
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Atomic Claim 556/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT05
Claim: 管理模組位於 VR NVL72 機箱前部的中間區。
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Atomic Claim 557/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0418
Claim: 每個可拆卸的 VR NVL72 前部模組都有一個小型金屬機箱。
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Atomic Claim 558/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0419
Claim: Mechanical structure 提供簡單的 guiding mechanism，引導 modules 與 midplane、internal manifolds 進行 blind-mate。
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The midplane and the internal manifolds are shipped together as a module. These highlighted mechanical parts act as a loading mechanism for the modules. These loading mechanisms ensure the modules are well connected to the Paladin connectors and the MQD by applying some force to the modules locking them in place.
Atomic Claim 559/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0420
Claim: midplane 與 internal manifolds 會一起以一個 module 的形式出貨。
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Atomic Claim 560/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0421
Claim: VR NVL72 運算托盤示意圖中標出的機械零件，用作模組裝載機構。
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Atomic Claim 561/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0422
Claim: VR NVL72 裝載機構將模組鎖定就位，確保與 Paladin 連接器及 MQD 介面可靠接合。
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Rack Level Infrastructure: Thermal
Beyond the redesigned fanless front chassis and the 100% liquid-cooled compute tray, the most notable point in the Vera Rubin cooling architecture discussion was Jensen’s comment on coolant/water warm temperatures and the use of chillers. For many, the statement that Vera Rubin can operate with 45C inlet temperatures, potentially avoiding mechanical compressor-based chillers, was viewed as a major surprise for much of the cooling supplier ecosystem.
We instead view this as a continuation of existing trends.
Atomic Claim 562/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0426
Claim: 依 SemiAnalysis 轉述，Jensen 表示 Vera Rubin 可在冷卻液入口溫度 45°C 下運作。
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Vera Rubin will be able to operate at a 45C inlet temperature, but Blackwell is already capable of operating with inlet water temperatures above 40C. Major system vendors such as Lenovo and HPE have also been discussing 100% liquid-cooled architectures operating at 45C since early 2025. In 2024, HPE announced an industrial cooling system based on full liquid cooling, and similar approaches have long been used before in HPC.
Lenovo discussed the next generation of its Neptune liquid solution at the 2025 OCP Summit, which is fully liquid-cooled and also uses 45C water.
Atomic Claim 563/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0427
Claim: Blackwell 已能在高於 40°C 的 inlet water temperature 下運行。
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Atomic Claim 564/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0428
Claim: Lenovo、HPE 等 major system vendors 自 2025 年初起，也一直在討論以 45°C 運行的 100% liquid-cooled architectures。
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Atomic Claim 565/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0429
Claim: 2024 年，HPE 發布以 full liquid cooling 為基礎的 industrial cooling system。
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Atomic Claim 566/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0430
Claim: 類似的做法在 HPC 領域早已使用多年。
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Atomic Claim 567/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0431::RESEG01
Claim: Lenovo 在 2025 OCP Summit 討論下一代 Neptune liquid solution。
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Atomic Claim 568/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0431::RESEG02
Claim: Lenovo 的下一代 Neptune liquid solution 採 fully liquid-cooled architecture。
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Atomic Claim 569/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0432::RESEG01
Claim: Lenovo 的下一代 Neptune liquid solution 使用 45°C water。
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Consider Schneider’s GB300 Reference Design 111, presented in September 2025, as another example. In this reference design, the datacenter uses a dual-loop architecture: a chilled-water loop dedicated to air cooling and a separate, higher-temperature loop dedicated to liquid cooling.
On the liquid side, the TCS circulates coolant to the cold plates at roughly 40C and returns it at a higher temperature, while the CDU transfers that heat into the facility water loop, which can enter the CDU at approximately 37C.
Atomic Claim 570/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0433
Claim: 另一個例子是 Schneider 的 GB300 Reference Design 111，於 2025 年 9 月發表。
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Atomic Claim 571/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0434
Claim: 所引用的 Schneider 資料中心參考設計，將冰水迴路與較溫暖的液冷迴路分開。
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Atomic Claim 572/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0435
Claim: 在 liquid loop 中，TCS 以約 40°C coolant 供給 cold plates，回水溫度更高；CDU 再把熱傳到 facility water loop，而 facility water 進入 CDU 時約為 37°C。
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So 45C cooling is not entirely new. Even with this capability, most operators deploying Blackwell are still designing for 20-30C water temperatures. As a rough approximation, current Blackwell inlet temperatures are around room temperature, with outlet temperatures in the 40-50C range. Only a small number of operators have removed chillers from the loop in favor of highly optimized economizer designs where climate permits.
Avoiding the compression step in mechanical cooling can deliver meaningful energy efficiency gains.
Atomic Claim 573/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0436
Claim: 因此，45°C cooling 並不是完全新的概念。
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Atomic Claim 574/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0437
Claim: 即使具備較高溫操作能力，多數部署 Blackwell 的 operators 目前仍以 20–30°C water temperature 進行設計。
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Atomic Claim 575/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0438::EPI01
Claim: 粗略估計，目前 Blackwell 的入口溫度接近室溫。
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Atomic Claim 576/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0438::EPI02
Claim: 粗略估計，目前 Blackwell 的出口溫度介於 40–50°C。
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Atomic Claim 577/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0439
Claim: 只有少數 operators 在 climate 條件允許時，以高度最佳化的 economizer design 取代 loop 中的 chillers。
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Atomic Claim 578/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0440
Claim: 在 mechanical cooling 中避開 compression step，可以帶來有意義的 energy-efficiency improvement。
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Now, how does Nvidia cool this heat monster, given that Vera Rubin’s power consumption and heat generation is roughly double that of Blackwell? Before answering, it is worth adding another consideration. Warmer inlet temperatures, while improving energy efficiency, can make cooling more challenging as inlet temperatures approach the maximum outlet temperature and the delta-T tightens.
With less temperature differential, you need higher water/coolant flow to remove the same amount of heat. In Blackwell reference architectures, the ceiling temperature is around 65C.
Atomic Claim 579/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0443
Claim: 較高的 inlet temperature 雖能提升 energy efficiency，但當 inlet temperature 接近 maximum outlet temperature、delta-T 收窄時，cooling 會變得更困難。
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Atomic Claim 580/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0444
Claim: 當 temperature differential 較小時，要移除相同熱量，就需要更高的 water/coolant flow。
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Atomic Claim 581/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0445
Claim: 在 Blackwell reference architectures 中，ceiling temperature 約為 65°C。
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Although NVIDIA initially did not formally publish full specifications for Vera Rubin’s liquid cooling system, we believe the platform will support maximum coolant return temperatures up to 65C. This aligns with Nvidia’s warm-water operating envelope, and while the exact implication for delta-T depends on the chosen supply setpoint and flow control strategy, we can expect a slightly tighter delta-T.
The pressure envelope is expected to be unchanged versus GB200, with maximum operating pressure of 72 psig (5 bar) and minimum burst pressure of 217 psig (15 bar), aligning with OCP’s MGX rack-level liquid-cooling specification.
Atomic Claim 582/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0446
Claim: 雖然 NVIDIA 起初未正式公布 Vera Rubin liquid-cooling system 的完整規格，SemiAnalysis 認為該 platform 將支援最高 65°C 的 coolant return temperature。
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Atomic Claim 583/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0447::SPLIT01
Claim: SemiAnalysis 認為，Vera Rubin 最高達 65°C 的冷卻液回水溫度，符合 Nvidia 的溫水操作範圍。
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Atomic Claim 584/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0447::SPLIT02
Claim: Vera Rubin 的確切溫差（delta-T）影響，取決於供水設定點與流量控制策略。
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Atomic Claim 585/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0447::SPLIT03
Claim: SemiAnalysis 預期 Vera Rubin 的溫差（delta-T）會略為縮小。
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Atomic Claim 586/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0448::SPLIT01
Claim: Vera Rubin 的壓力範圍預期與 GB200 相同。
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Atomic Claim 587/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0448::SPLIT02
Claim: Vera Rubin 的最大操作壓力預期為 72 psig（5 bar）。
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Atomic Claim 588/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0448::SPLIT03
Claim: Vera Rubin 的最小爆破壓力預期為 217 psig（15 bar）。
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Atomic Claim 589/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0448::SPLIT04
Claim: 預期的 Vera Rubin 壓力範圍符合 OCP MGX 機櫃級液冷規格。
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Atomic Claim 590/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-INLET-MIN
Claim: NVIDIA 冷卻液操作範圍表列出的最低冷卻液入口溫度為 17°C。
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In practice, cooling follows straightforward physics. To cool a system, you must deliver sufficient water/coolant at the appropriate temperature and pressure through the loop. If you want to increase the cooling capacity of a CDU, you increase flow rate while managing pressure, which in this case implies around a 2.0-2.5x flow increase, depending on how far outlet temperatures are actually pushed by operators.
Atomic Claim 591/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0450
Claim: 要冷卻一套 system，必須在 loop 中以適當 temperature 與 pressure 提供足夠的 water／coolant。
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Atomic Claim 592/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0451
Claim: 若要提高 CDU 的 cooling capacity，就需要提高 flow rate。
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Atomic Claim 593/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0452::RESEG01
Claim: 提高 CDU cooling capacity、增加 flow rate 時，同時需要管理 pressure。
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Atomic Claim 594/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0452::RESEG02
Claim: 在此案例中，需要的 flow increase 約為 2.0–2.5 倍；實際幅度取決於 operators 將 outlet temperature 推高到何種程度。
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Nvidia has indicated that Vera Rubin increases liquid flow rate and achieves nearly double the thermal performance vs Blackwell, without increasing CDU pressure head or introducing additional cooling complexity or cost. Nvidia has achieved this by optimizing the entire hydraulic path. We expect larger quick disconnects to support higher flow, as well as updated manifolds and piping.
Vendor roadmaps suggest that, at least for the next generation of racks, 2 inch QDs should be sufficient to accommodate higher flow while staying within pressure and flow-velocity limits.
Atomic Claim 595/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0453
Claim: Nvidia 表示，Vera Rubin 會提高 liquid flow rate。
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Atomic Claim 596/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0454::RESEG01
Claim: Nvidia 表示，Vera Rubin 的 thermal performance 接近 Blackwell 的 2 倍。
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Atomic Claim 597/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0454::RESEG02
Claim: Nvidia 表示，Vera Rubin 達到上述 thermal performance 時，不需要提高 CDU pressure head。
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Atomic Claim 598/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0454::RESEG03
Claim: Nvidia 表示，Vera Rubin 不需要增加額外 cooling complexity。
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Atomic Claim 599/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0454::RESEG04
Claim: Nvidia 表示，Vera Rubin 不需要增加額外 cooling cost。
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Atomic Claim 600/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0455
Claim: Nvidia 透過最佳化整條 hydraulic path 達成這項結果。
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Atomic Claim 601/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0456::SPLIT01
Claim: SemiAnalysis 預期 Vera Rubin 將使用更大的快速接頭以支援更高流量。
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Atomic Claim 602/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0456::SPLIT02
Claim: SemiAnalysis 預期 Vera Rubin 將更新分歧管。
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Atomic Claim 603/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0456::SPLIT03
Claim: SemiAnalysis 預期 Vera Rubin 將更新管路。
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Atomic Claim 604/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0457
Claim: Vendor roadmaps 顯示，至少對下一代 racks 而言，2-inch QD 應足以容納較高 flow，同時維持在 pressure 與 flow-velocity limits 內。
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Procurement and Cooling Vendor Implications
The primary vendor implication of the updated cooling architecture and doubled power density relates to CDUs and the rack-to-CDU ratio. Today, a CDU can support around 10 GB200 racks. With a rack generating about 2x the heat, that ratio would need to decline unless CDU capacity increases, implying either more CDUs or higher-capacity CDUs. We believe most major operators expect to maintain a ratio of around 10 racks per CDU. As rack power density rises, this points to larger CDUs.
Today, in-row CDUs offer cooling capacities up to roughly 2 MW, but we expect future facility CDUs to reach 3-6 MW. Delta currently leads in the CDU specialist segment, alongside Schneider Electric, Vertiv, and nVent. Foxconn and Quanta dominate the system integrator category.
Atomic Claim 605/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0458
Claim: Updated cooling architecture 與約翻倍的 power density，對 vendors 的主要影響落在 CDU 與 rack-to-CDU ratio。
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Atomic Claim 606/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0459
Claim: 目前一台 CDU 大約可支援 10 個 GB200 racks。
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Atomic Claim 607/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0460
Claim: 如果單一 rack 產生約 2 倍 heat，而 CDU capacity 沒有提高，rack-to-CDU ratio 就需要下降；也就是需要更多 CDU 或更高 capacity 的 CDU。
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Atomic Claim 608/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0461
Claim: SemiAnalysis 認為，多數 major operators 預期維持約 10 racks／CDU 的比例。
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Atomic Claim 609/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0462
Claim: 在 rack power density 上升且 operators 預期維持約十個 rack／CDU 的前提下，SemiAnalysis 推論將需要更大型的 CDU。
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Atomic Claim 610/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0463
Claim: 關於 CDU：目前 in-row CDUs cooling capacity 最高約 2MW。
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Atomic Claim 611/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0464
Claim: SemiAnalysis 預期未來 facility CDU capacity 將達 3–6MW。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 612/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0465::SPLIT01
Claim: Delta currently leads the CDU specialist segment.
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 613/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0465::SPLIT02
Claim: Schneider Electric 參與 CDU 專業供應商市場。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 614/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0465::SPLIT03
Claim: Vertiv 參與 CDU 專業供應商市場。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 615/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0465::SPLIT04
Claim: nVent 參與 CDU 專業供應商市場。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 616/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0466
Claim: Foxconn 與 Quanta 主導 system integrator category。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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The shift from liquid + air to 100% liquid systems, combined with higher flow rates and greater cooling capacity, will require changes across the cooling stack. Fans and radiators used in L2A CDUs will become less critical over time. That said, L2A is likely to maintain meaningful share during the current upcycle, where deployment speed matters more than full optimization, though the long-term trajectory clearly favors L2L. High-density L2L systems will also require redesigns across much of the TCS.
This includes updated manifolds, larger quick disconnects (Colder Products Company, Danfoss, Staubli, Parker Hannifin), gold-plated cold plates (AVC, Delta, Boyd, CoolIT, Auras) and, very critically, larger pumps capable of delivering the required water volume. Pump sizing is directly linked to power density and the heat that must be removed.
Even manufacturers of motor and drive components used in these pumps, such as Allegro MicroSystems, could see their prospects change as either larger motors, more motors, or both are required. In summary, higher heat on the TCS loop likely increases content/MW for white-space cooling vendors. QDs should benefit most, alongside manifolds and cold plates, with CDUs also benefiting, though to a lesser extent.
Atomic Claim 617/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0467
Claim: 從 liquid + air 轉向 100% liquid cooling，再加上更高 flow rate 與更大 cooling capacity，會要求整個 cooling stack 發生變化。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 618/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0468::EPI01
Claim: 隨著系統轉向全液冷，L2A CDU 使用的風扇將逐漸變得較不重要。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 619/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0468::EPI02
Claim: 隨著系統轉向全液冷，L2A CDU 使用的散熱器將逐漸變得較不重要。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 620/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0469::SPLIT01
Claim: L2A 很可能在本輪上行週期維持可觀占比，因為部署速度比完全最佳化更重要。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 621/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0469::SPLIT02
Claim: 來源判斷，長期散熱發展方向有利於 L2L。
Frame:ATTRIBUTE· Mode:INFERRED· Mapping:COMPLETE
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Atomic Claim 622/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0470
Claim: 原文預期：High-density L2L systems 也需要重新設計 TCS 的大部分內容。
Frame:CLAIM_ONLY· Mode:EXPECTED· Mapping:PARTIAL
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Atomic Claim 623/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT01
Claim: 高密度 L2L 系統將需要更新分歧管。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 624/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT02
Claim: 高密度 L2L 系統將需要更大的快速接頭。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 625/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT03
Claim: 高密度 L2L 系統將需要鍍金冷板。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 626/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT04
Claim: 高密度 L2L 系統將需要更大的泵浦，以提供所需水量。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 627/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT05
Claim: 在 L2L 重新設計的討論中，來源將 Colder Products Company 列為快速接頭供應商。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 628/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT06
Claim: 在 L2L 重新設計的討論中，來源將 Danfoss 列為快速接頭供應商。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 629/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT07
Claim: 在 L2L 重新設計的討論中，來源將 Staubli 列為快速接頭供應商。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 630/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT08
Claim: 在 L2L 重新設計的討論中，來源將 Parker Hannifin 列為快速接頭供應商。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 631/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT09
Claim: 在 L2L 重新設計的討論中，來源將 AVC 列為冷板供應商。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 632/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT10
Claim: The source names Delta among cold-plate vendors in the L2L redesign discussion.
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 633/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT11
Claim: 在 L2L 重新設計的討論中，來源將 Boyd 列為冷板供應商。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 634/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT12
Claim: 在 L2L 重新設計的討論中，來源將 CoolIT 列為冷板供應商。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 635/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT13
Claim: 在 L2L 重新設計的討論中，來源將 Auras 列為冷板供應商。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 636/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0472
Claim: Pump sizing 與 power density 直接相關。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 637/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0473::RESEG01
Claim: Pump sizing 與需要移除的 heat 直接相關。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 638/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0474
Claim: 像 Allegro MicroSystems 這類用於 pumps 的 motor 與 drive component makers，也可能因需要更大型 motors、更多 motors、或兩者兼具而改變其前景。
Frame:CLAIM_ONLY· Mode:HYPOTHETICAL· Mapping:PARTIAL
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Atomic Claim 639/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0475
Claim: 總結而言，TCS loop 上更高的 heat 可能提高 white-space cooling vendors 的 content／MW。
Frame:CLAIM_ONLY· Mode:EXPECTED· Mapping:PARTIAL
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Atomic Claim 640/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0476::SPLIT01
Claim: SemiAnalysis 預期，快速接頭將最受惠於 TCS 迴路熱負載增加。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 641/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0476::SPLIT02
Claim: SemiAnalysis 預期，分歧管將受惠於 TCS 迴路熱負載增加。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 642/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0476::SPLIT03
Claim: SemiAnalysis 預期，冷板將受惠於 TCS 迴路熱負載增加。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 643/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0476::SPLIT04
Claim: SemiAnalysis 預期，CDU 將受惠於 TCS 迴路熱負載增加，但受惠程度低於快速接頭。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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For the FWS layout, the headline implication is the potential for chiller-less designs. Some operators are already running Blackwell systems without chillers in more AI-optimized designs, while others choose to retain chillers for workload flexibility, mixed-hall compatibility, redundancy, and reliability.
Over the long term, we expect AI-optimized systems to make chillers less necessary, with content shifting from air-cooled chillers toward dry coolers or adiabatic towers. We currently estimate roughly 0.2M/MW for dry coolers or adiabatic towers. SPX Technologies, alongside BAC and Evapco, could benefit, while Johnson Controls, Carrier, and Trane may be challenged.
Nonetheless, we expect this efficiency/flexibility trade-off to persist in the medium term and do not foresee a chiller downturn occurring overnight.
Atomic Claim 644/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0477
Claim: 對 FWS layout 而言，最主要的 implication 是 chiller-less design 的可能性。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 645/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0478
Claim: 部分 operators 已在更偏 AI-optimized 的 designs 中，讓 Blackwell systems 在沒有 chillers 的情況下運行。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 646/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0479::SPLIT01
Claim: 部分營運商為保有工作負載彈性而保留冰水主機。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 647/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0479::SPLIT02
Claim: 部分營運商為相容混合機房而保留冰水主機。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 648/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0479::SPLIT03
Claim: 部分營運商為備援而保留冰水主機。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 649/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0479::SPLIT04
Claim: 部分營運商為可靠性而保留冰水主機。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 650/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0480::SPLIT01
Claim: SemiAnalysis 預期，長期而言，針對 AI 最佳化的系統將降低對冰水主機的需求。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 651/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0480::SPLIT02
Claim: SemiAnalysis 預期，長期而言，設備配置價值將從氣冷式冰水主機轉向乾式冷卻器或絕熱冷卻塔。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 652/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0481
Claim: SemiAnalysis 目前估計 air-cooled chiller content 約為 0.2M／MW。
Frame:CLAIM_ONLY· Mode:ESTIMATED· Mapping:PARTIAL
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Atomic Claim 653/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0482::SPLIT01
Claim: SPX Technologies 可能受惠於散熱設備配置價值轉向乾式冷卻器或絕熱冷卻塔。
Frame:ATTRIBUTE· Mode:HYPOTHETICAL· Mapping:COMPLETE
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Atomic Claim 654/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0482::SPLIT02
Claim: BAC 可能受惠於散熱設備配置價值轉向乾式冷卻器或絕熱冷卻塔。
Frame:ATTRIBUTE· Mode:HYPOTHETICAL· Mapping:COMPLETE
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Atomic Claim 655/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0482::SPLIT03
Claim: Evapco 可能受惠於散熱設備配置價值轉向乾式冷卻器或絕熱冷卻塔。
Frame:ATTRIBUTE· Mode:HYPOTHETICAL· Mapping:COMPLETE
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Atomic Claim 656/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0483::SPLIT01
Claim: 散熱設備配置價值移出氣冷式冰水主機，可能對 Johnson Controls 形成挑戰。
Frame:ATTRIBUTE· Mode:HYPOTHETICAL· Mapping:COMPLETE
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Atomic Claim 657/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0483::SPLIT02
Claim: 散熱設備配置價值移出氣冷式冰水主機，可能對 Carrier 形成挑戰。
Frame:ATTRIBUTE· Mode:HYPOTHETICAL· Mapping:COMPLETE
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Atomic Claim 658/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0483::SPLIT03
Claim: 散熱設備配置價值移出氣冷式冰水主機，可能對 Trane 形成挑戰。
Frame:ATTRIBUTE· Mode:HYPOTHETICAL· Mapping:COMPLETE
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Atomic Claim 659/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0484
Claim: 即便如此，SemiAnalysis 預期 efficiency／flexibility trade-off 在中期仍會持續，不認為 chiller downturn 會一夕發生。
Frame:CLAIM_ONLY· Mode:EXPECTED· Mapping:PARTIAL
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Rack Level Infrastructure: Power Delivery
In the GB200 article from 2024, we discussed the previous evolution on power delivery from node level PSU (power supply unit) to centralized rack level power shelf. As VR NVL72 rack TDP reaches 180kW-220kW per rack from 120kW-140kW for GB200 and GB300, the power delivery infrastructure has evolved yet again. In the section below we will discuss the power delivery infrastructure at the rack level of the reference design and the power delivery at the compute tray level for VR NVL72.
Atomic Claim 660/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0486::RESEG01
Claim: VR NVL72 rack TDP 為每 rack 180–220kW，較 GB200／GB300 的 120–140kW 更高。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 661/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0487::RESEG01
Claim: VR NVL72 rack TDP 提升到 180–220kW，使 power delivery infrastructure 再次演進。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Since the deployment of GB200, the main theme of the power delivery infrastructure evolution has been about transmission efficiency and power stability. Hyperscalers are developing power delivery infrastructure to address the challenges that comes with high density AI server racks with the roadmap set to 1MW per rack in the next couple of years.
Hence, HVDC (high voltage direct current) power rack, BBU (battery back up units), CBU (capacitor backup units), liquid cooled busbar, and SST (solid state transformers) are being developed to increase transmission efficiency and power stability. These will be deployed by customers depending on their proprietary infrastructure designs.
Atomic Claim 662/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0518
Claim: SST（solid state transformers）也在開發，以提高 transmission efficiency 與 power stability。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 663/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0489
Claim: 自 GB200 部署以來，power delivery infrastructure 演進的主要主題一直是 transmission efficiency 與 power stability。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
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Atomic Claim 664/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0490::SPLIT01
Claim: Hyperscaler 正在開發電力基礎設施，以因應高密度 AI 伺服器機櫃的挑戰。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 665/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0490::SPLIT02
Claim: Hyperscaler 的電力路線圖以未來幾年內達到每櫃 1MW 為目標。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:COMPLETE
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Atomic Claim 666/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0491::SPLIT01
Claim: HVDC 正作為電力基礎設施開發，以改善輸電效率與電力穩定性；部署取決於客戶的基礎設施設計。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 667/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0491::SPLIT02
Claim: BBU 正作為電力基礎設施開發，以改善輸電效率與電力穩定性；部署取決於客戶的基礎設施設計。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 668/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0491::SPLIT03
Claim: CBU 正作為電力基礎設施開發，以改善輸電效率與電力穩定性；部署取決於客戶的基礎設施設計。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 669/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0491::SPLIT04
Claim: 液冷匯流排正在開發中，以改善輸電效率與穩定性；部署取決於客戶的基礎設施設計。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 670/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0492
Claim: 所述 HVDC、BBU、CBU 與液冷匯流排技術的部署，取決於各客戶的基礎設施設計。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:PARTIAL
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For the VR NVL72 reference design, the power delivery infrastructure at the rack level includes four 110kW power shelves. The VR NVL72 system has a TDP up to 220kW for the 2300W Rubin TDP SKU. The design with four 110kW power shelves is an N+1 redundancy approach. Each 110kW power shelf is 3U tall and includes six 18.3kW PSU with built in capacitors in the PSU. Each power shelf receives three phase 415VAC-480VAC of power from two 100A whips.
The power shelves step down the power from 415VAC-480VAC to 50VDC and sends it to the busbar. Interestingly, the busbar of VR NVL72 is rated for 5000A+, which is much higher than that of Grace Blackwell at 2900A. Given the extremely high current and the lack of fans in the rack, the busbar has to be liquid cooled.
Atomic Claim 671/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0493
Claim: VR NVL72 reference design 的 rack-level power delivery infrastructure 包含 4 個 110kW power shelves。
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Atomic Claim 672/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0494
Claim: 對 2,300W Rubin TDP SKU 而言，VR NVL72 system TDP 最高可達 220kW。
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Atomic Claim 673/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0495
Claim: 採用 4 個 110kW power shelves 的設計，是 N+1 redundancy approach。
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Atomic Claim 674/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0496
Claim: 每個 110kW power shelf 高度為 3U。
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Atomic Claim 675/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0497::SPLIT01
Claim: 每個 110kW 的 VR NVL72 電源層架包含六個 18.3kW PSU。
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Atomic Claim 676/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0497::SPLIT02
Claim: VR NVL72 電源層架的 PSU 內建電容。
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Atomic Claim 677/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0498
Claim: 每個 power shelf 由兩條 100A whips 接收 three-phase 415VAC–480VAC power。
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Atomic Claim 678/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0499
Claim: power shelves 將 415VAC–480VAC 降壓為 50VDC，並送到 busbar。
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Atomic Claim 679/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0500
Claim: VR NVL72 的 busbar rated current 為 5,000A+，明顯高於 Grace Blackwell 的 2,900A。
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Atomic Claim 680/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0501
Claim: 由於 current 極高且 rack 內沒有 fans，busbar 必須採 liquid cooling。
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Atomic Claim 681/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BUSBAR-AIR
Claim: 所引用的 OCP 2025 匯流排比較資料，將氣冷 ORv3 HPR 範例的額定功率列為 140kW。
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Atomic Claim 682/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BUSBAR-CURRENT
Claim: 所引用的 OCP 2025 匯流排比較資料，將液冷 ORv3 HPR 範例的額定電流列為 15,625A。
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Atomic Claim 683/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BUSBAR-LIQ
Claim: 所引用的 OCP 2025 匯流排比較資料，將液冷 ORv3 HPR 範例的額定功率列為 750kW。
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For the hyperscale customers, they might choose to deploy a standalone power rack either in LVDC (low voltage direct current) or HVDC (high voltage direct current). Below we provide two possible scenarios of the power rack deployment for VR NVL72.
Atomic Claim 684/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0502
Claim: 對 hyperscale customers 而言，他們可能選擇部署 standalone power rack，採 LVDC 或 HVDC。
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First, VR NVL72 rack with an HVDC power rack running at 800VDC (Nvidia Spec) or +/-400VDC (OCP Spec). Since the VR NVL72 rack busbar is still running at 50V and the compute tray can only take in 50V, the 800VDC from the power rack cannot be directly delivered to the busbar. There would still be DC-DC power shelves in the VR NVL72 rack. The DC-DC power shelves will step down the voltage of the current from 800VDC to 50VDC.
Atomic Claim 685/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0504::SPLIT01
Claim: 一種可能的 VR NVL72 電力配置，是使用依 Nvidia 規格在 800VDC 下運作的 HVDC 電源櫃。
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Atomic Claim 686/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0504::SPLIT02
Claim: VR NVL72 的另一種 HVDC 電源櫃規格為 OCP +/-400VDC。
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Atomic Claim 687/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0505::RESEG01
Claim: 在第一個 HVDC power-rack deployment scenario 中，VR NVL72 rack 的 busbar 仍運行於 50V。
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Atomic Claim 688/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0506::RESEG01
Claim: 在第一個 HVDC power-rack deployment scenario 中，compute tray 只能接收 50V。
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Atomic Claim 689/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0506::RESEG02
Claim: 在第一個 HVDC power-rack deployment scenario 中，power rack 的 800VDC 無法直接送入 busbar。
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Atomic Claim 690/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0507
Claim: 在假設的 HVDC 電源櫃部署中，VR NVL72 機櫃仍需要 DC-DC 電源層架。
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Atomic Claim 691/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0508
Claim: 在假設的 HVDC 電源櫃部署中，DC-DC 層架將 800VDC 轉換為 50VDC。
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Second, some customers, namely Meta, may look to integrate their network switch rack with BBU and CBU shelves for efficiency and peak shaving. This allows more CBU and BBU capacity that wouldn’t have been able to fit in the GPU rack. The BBU/CBU and switch rack will be connected to the GPU rack with 50V horizontal busbars. Meta calls this the high power rack, discussed at OCP.
Atomic Claim 692/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0509::SPLIT01
Claim: 部分客戶，尤其是 Meta，可能將 BBU 層架整合進網路交換器機櫃，以提升效率並削峰。
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Atomic Claim 693/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0509::SPLIT02
Claim: 部分客戶，尤其是 Meta，可能將 CBU 層架整合進網路交換器機櫃，以提升效率並削峰。
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Atomic Claim 694/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0510::RESEG01
Claim: 在所提出的 switch-rack integration scenario 中，這種配置可容納更多 CBU capacity；這些 capacity 原本無法放進 GPU rack。
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Atomic Claim 695/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0511::RESEG01
Claim: 在所提出的 switch-rack integration scenario 中，這種配置可容納更多 BBU capacity；這些 capacity 原本無法放進 GPU rack。
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Atomic Claim 696/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0512
Claim: 在提出的 Meta 高功率機櫃情境中，50V 水平匯流排將 BBU／CBU 與交換器機櫃連接至 GPU 機櫃。
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Atomic Claim 697/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0513::SPLIT01
Claim: Meta 將所述 BBU／CBU 與網路交換器的整合配置稱為 high power rack。
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Atomic Claim 698/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0513::SPLIT02
Claim: Meta 曾在 OCP 討論 high power rack。
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Networking: NVLink 6, Rubin Scale Out
NVIDIA’s gen-on-gen innovations are evolutionary and not revolutionary. With GPU scale-up and scale-out bandwidth doubling approximately every 18 months, the copper infrastructure in NVIDIA racks are being innovated to accommodate higher bandwidth workloads. Scale-up network infrastructure will eventually involve optics to build larger world sizes, but that is the topic of a separate article.
Atomic Claim 699/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0515::SPLIT01
Claim: GPU scale-up 頻寬約每 18 個月加倍。
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Atomic Claim 700/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0515::SPLIT02
Claim: GPU scale-out 頻寬約每 18 個月加倍。
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Atomic Claim 701/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0515::SPLIT03
Claim: Nvidia 機櫃的銅互連基礎設施正在演進，以適應更高頻寬的工作負載。
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Atomic Claim 702/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0515::SPLIT04
Claim: Scale-up 網路基礎設施最終將導入光學互連，以建立更大的 world size。
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NVLink 6 used in Vera Rubin doubles NVLink bandwidth by implementing bi-directional signaling over the same number of copper cables—effectively delivering 4 Lanes of 200G per NVLink.
Atomic Claim 703/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0517
Claim: Vera Rubin 使用的 NVLink 6，透過在相同數量 copper cables 上實作 bi-directional signaling，使 NVLink bandwidth 翻倍；等效為每個 NVLink 提供 4 lanes × 200G。
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Bi-directional SerDes for Scale-Up
The doubling of bandwidth per logical GPU from NVLink 5 in GB300 NVL72 to NVLink 6 in Vera Rubin NVL72 are made possible by using a simultaneous bi-directional SerDes for the copper backplane instead of increasing the modulation or baud rate. Whereas NVLink 5 delivers 224G per electrical lane, NVLink 6.0 delivers 448G per electrical lane. Each electrical lane is one differential pair (DP) consisting of two conductors that carry equal magnitude, and opposite polarity signals.
Atomic Claim 704/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0518
Claim: 從 GB300 NVL72 的 NVLink 5 到 Vera Rubin NVL72 的 NVLink 6，每個 logical GPU 的 bandwidth 翻倍；原文認為這是藉由 copper backplane 上 simultaneous bi-directional SerDes 達成，而不是提高 modulation 或 baud rate。
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Atomic Claim 705/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0519
Claim: NVLink 5 每個 electrical lane 為 224G；NVLink 6.0 則為 448G。
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Atomic Claim 706/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0520
Claim: 每個 electrical lane 是一組 differential pair（DP），由兩條 conductors 組成，兩者承載 magnitude 相等、polarity 相反的 signals。
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This gives rise to the engineering problem of ensuring that a clean signal can be received at either end of the wire because two signals sent in opposite directions over the same copper wire will superpose to form a composite signal that is different from the intended transmitting signal.
Atomic Claim 707/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0521
Claim: 在銅線同時雙向傳訊中，反向訊號會在導線上疊加，因此需要在接收端分離。
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In optics, bidirectional interconnect can be achieved by integrating an optical circulator to a transceiver. The circulator works by routing the inbound and outbound signal onto separate paths, ensuring no overlaps between both at the photodiode receiver. Bidirectional interconnect is, however, much trickier in the copper domain.
A circulator cannot be used as copper cables are linear transmission lines, which means that the inbound and outbound signals will be summed at the receiver through superposition. The receiver at each end of the copper wire therefore needs a mechanism to separate the local TX from the local RX.
Atomic Claim 708/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0522
Claim: 在 optics 中，可以透過把 optical circulator 整合進 transceiver 來實作 bidirectional interconnect。
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Atomic Claim 709/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0523
Claim: Circulator 會把 inbound 與 outbound signals 導向不同 paths，確保兩者在 photodiode receiver 不重疊。
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Atomic Claim 710/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0524
Claim: 但在 copper domain 中，bidirectional interconnect 困難得多。
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Atomic Claim 711/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0525::RESEG01
Claim: Copper cables 是 linear transmission lines。
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Atomic Claim 712/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0525::RESEG02
Claim: Copper cable path 無法使用 circulator。
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Atomic Claim 713/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0526::RESEG01
Claim: 在 copper cable receiver，inbound 與 outbound signals 會透過 superposition 相加。
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Atomic Claim 714/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0527
Claim: 因此 copper wire 兩端的 receiver 都需要一套 mechanism，把 local TX 與 local RX 分離。
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The solution to this problem is the use of a hybrid at each end of the wire. Without a hybrid, there will be self-interference at the local RX because both the local TX and local RX are being transmitted along the same wire:
Atomic Claim 715/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0561
Claim: 關於 SerDes：若沒有 hybrid，local TX 與 local RX 同時沿同一條 wire 傳送，會在 local RX 產生 self-interference。
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Atomic Claim 716/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0528
Claim: 所述同時雙向銅連線，在導線兩端各使用一個 hybrid 電路來抑制自我干擾。
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(B0 + A0 = BA0)
Atomic Claim 717/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0532
Claim: 在來源的回聲消除符號中，疊加訊號表示為 B0 + A0 = BA0。
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An inverted copy of the local TX must therefore be generated at the local RX for proper echo cancellation:
Atomic Claim 718/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0531
Claim: 因此 local RX 必須產生 local TX 的 inverted copy，才能進行正確的 echo cancellation。
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(B0 + A0 = BA0 + (-A0) = B0)
Atomic Claim 719/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-ECHO-CANCEL
Claim: 來源將消除式寫為 B0+A0=BA0+(−A0)=B0；此處記錄來源符號，不代表認可整串等式。
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While bidirectional signaling is being used for short-reach (less than 5mm) die-to-die interconnect, what stands out is that NVIDIA has extended this technology to longer reach transmission over copper backplane with a reach of at least 1m.
Atomic Claim 720/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0533
Claim: Bidirectional signaling 已用於小於 5mm 的 short-reach die-to-die interconnect；更值得注意的是，NVIDIA 已把這項技術延伸到 copper backplane 上至少 1m 的 longer-reach transmission。
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The challenge with bidirectional signaling is that echo cancellation must be precisely calibrated or slight delays in the generation of the local TX copy can cause link failure. However, if NVIDIA were to continue using the 200G SerDes, doubling the bandwidth would mean doubling the number of copper cables at the backplane, which is a tall order for several reasons.
Atomic Claim 721/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0534
Claim: Bidirectional signaling 的挑戰是 echo cancellation 必須精準校準；local TX copy 的生成只要有些微 delay，就可能造成 link failure。
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Atomic Claim 722/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0535
Claim: 如果 NVIDIA 繼續使用 200G SerDes，要把 bandwidth 翻倍就代表 copper backplane 上的 copper cable 數量也要翻倍，這在多個層面都很困難。
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Cramming in approximately five thousand copper cables on the backplane at the Blackwell generation has introduced non-trivial reliability failure modes at scale. To double scale-up bandwidth while staying on regular 200G SerDes would require the backplane to double to ten thousand copper cables: only further increasing the manufacturing complexity and likelihood of failure of the system.
Atomic Claim 723/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0536
Claim: 在 Blackwell generation，copper backplane 已塞入約 5,000 條 copper cables，並在 scale deployment 下帶來不可忽視的 reliability failure modes。
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Atomic Claim 724/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0537::RESEG01
Claim: 若維持一般 200G SerDes 並讓 scale-up bandwidth 加倍，backplane 需要約 10,000 條 copper cables。
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Atomic Claim 725/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0538::RESEG01
Claim: 約 10,000 條 copper cables 的 backplane 配置會進一步提高 manufacturing complexity。
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Atomic Claim 726/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0538::RESEG02
Claim: 約 10,000 條 copper cables 的 backplane 配置會進一步提高 system failure 的 likelihood。
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NVIDIA could also opt to deploy wider racks instead as is the case of AMD’s Helios rack, but this could affect the signal integrity on the PCB as electrical signals will have to traverse a longer path.
Atomic Claim 727/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0539
Claim: 在假設情境下，Nvidia 可以為其機櫃架構選擇類似 AMD Helios 的較寬機櫃。
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Atomic Claim 728/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0540
Claim: 採用更寬 rack 也可能影響 PCB 上的 signal integrity，因為 electrical signals 必須走更長的 path。
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Scale-Up Network – NVLink 6
The bidirectional SerDes technology employed on the copper backplane is used for NVIDIA’s scale-up network. For Vera Rubin NVL72, the scale-up network continues to be rail-optimized with all-to-all connectivity between each GPU and switch ASIC in the scale-up domain.
Atomic Claim 729/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0541
Claim: Copper backplane 上採用的 bidirectional SerDes technology，用於 NVIDIA 的 scale-up network。
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Atomic Claim 730/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0542
Claim: 對 Vera Rubin NVL72，scale-up network 繼續採 rail-optimized design，scale-up domain 中每顆 GPU 與 switch ASIC 之間都是 all-to-all connectivity。
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NVIDIA’s GB200 scale-up architecture consists of 18 NVLink 5 Switch chips in a single rack for the NVL72 system.
Atomic Claim 731/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0543
Claim: NVIDIA 的 GB200 scale-up architecture，在單一 NVL72 rack 中包含 18 顆 NVLink 5 Switch chips。
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Although the NVLink 6 Switch used in the VR NVL72 system delivers the same per switch 28.8T aggregate bandwidth as NVLink 5 Switch, the SerDes speed on the NVLink 6 Switch is double the SerDes speed of NVLink 5 Switch but with the same number of DPs. As such, in order to deliver double the aggregate scale-up bandwidth required for NVLink 6, Vera Rubin NVL72 racks will contain double the number of NVLink Switches as compared to GB200 racks.
This translates to four NVLink Switch chips per tray on 9 switch trays, or 36 NVLink Switch chips in each rack.
Atomic Claim 732/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0544::SPLIT01
Claim: VR NVL72 的 NVLink 6 交換器維持與 NVLink 5 相同的每顆 28.8T 總頻寬。
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Atomic Claim 733/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0544::SPLIT02
Claim: NVLink 6 交換器的 SerDes 速度是 NVLink 5 的兩倍。
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Atomic Claim 734/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0544::SPLIT03
Claim: NVLink 6 交換器維持與 NVLink 5 相同的差動對（DP）數量。
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Atomic Claim 735/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0545
Claim: 為提供 NVLink 6 所需的 2 倍 aggregate scale-up bandwidth，Vera Rubin NVL72 rack 的 NVLink Switch 數量會是 GB200 rack 的 2 倍。
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Atomic Claim 736/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0546::SPLIT01
Claim: VR NVL72 每個交換器托盤有四顆 NVLink 交換晶片。
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Atomic Claim 737/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0546::SPLIT02
Claim: VR NVL72 有九個交換器托盤。
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Atomic Claim 738/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0546::SPLIT03
Claim: VR NVL72 每個機櫃有 36 顆 NVLink 交換晶片，由九個托盤、每盤四顆組成。
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Each VR NVL72 Switch tray contains four NVLink 6 Switch ASICs and one system management module. The design of the Rubin NVLink 6 Switch tray is also simpler and relatively seamless compared to the first Oberon NVLink 5 Switch released for GB200 because Rubin NVLink 6 Switch trays will not use flyover cables. As such, all NVLink signals will run over the PCB.
Atomic Claim 739/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0547::SPLIT01
Claim: 每個 VR NVL72 交換器托盤包含四顆 NVLink 6 交換 ASIC。
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Atomic Claim 740/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0547::SPLIT02
Claim: 每個 VR NVL72 交換器托盤包含一個系統管理模組。
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Atomic Claim 741/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0548::RESEG01
Claim: Rubin NVLink 6 Switch tray 相較 GB200 首代 Oberon NVLink 5 Switch 更簡化。
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Atomic Claim 742/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0549::RESEG01
Claim: Rubin NVLink 6 Switch tray 相較 GB200 首代 Oberon NVLink 5 Switch 更 seamless。
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Atomic Claim 743/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0549::RESEG02
Claim: Rubin NVLink 6 Switch trays 不使用 flyover cables。
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Atomic Claim 744/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0550
Claim: 在 Rubin NVLink 6 交換器板上，NVLink 訊號經由 PCB 走線傳輸。
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The NVLink 6 Switch board is liquid cooled and will be covered with a cold plate, which is a single module. Connected to the NVSwitch tray is the system management module (SMM) that comes with a CPU and acts as a host to the switch tray. The switch tray to SMM connection uses flyover cables, but this is the only flyover cable connection required in the entire Vera Rubin NVL72 system.
Given that the PCIe connection is lower speed and the NVLink Switch tray contains relatively few modules, assembly of the switch tray is unlikely to be challenging.
Atomic Claim 745/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0584
Claim: NVLink 6 Switch board 會由單一 module 形式的 cold plate 覆蓋。
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Atomic Claim 746/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0551
Claim: NVLink 6 Switch board 採 liquid cooling。
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Atomic Claim 747/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0553::SPLIT01
Claim: 一個系統管理模組連接至 NVSwitch 托盤。
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Atomic Claim 748/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0553::SPLIT02
Claim: NVSwitch 托盤的系統管理模組包含一顆 CPU。
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Atomic Claim 749/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0553::SPLIT03
Claim: 系統管理模組擔任 NVSwitch 托盤的主機。
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Atomic Claim 750/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0554
Claim: switch tray 與 SMM 之間使用 flyover cables 連接。
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Atomic Claim 751/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0555
Claim: 在所述 VR NVL72 系統中，交換器托盤與 SMM 之間的連接，是唯一需要 flyover 纜線的連接。
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Atomic Claim 752/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0556::RESEG01
Claim: 由於 PCIe connection 速度較低、且 NVLink Switch tray 內 modules 相對少，switch tray assembly 不太可能構成重大挑戰。
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Each of the green lines in the reference topology represents nine 400G logical ports of NVLink 6, or 18 TX/RX lanes of 200G. Because there is only 1 DP per lane using bidirectional SerDes, there are a total of 18 DPs between any connector and any switch for a total of 72 DPs per connector, which is the same as prior generation of NVLink 5 Switch Tray.
Atomic Claim 753/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0558
Claim: Reference topology 中每條 green line 代表 NVLink 6 的 9 個 400G logical ports，或 18 條 200G TX/RX lanes。
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Atomic Claim 754/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0559::RESEG01
Claim: 使用 bidirectional SerDes 時，每個 lane 只需要 1 個 differential pair（DP）。
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Atomic Claim 755/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0559::RESEG02
Claim: 在圖示的 Rubin NVLink 6 交換器托盤拓撲中，每條連接器至交換器的路徑包含 18 組差動對。
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Atomic Claim 756/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0560::RESEG01
Claim: 在圖示的 Rubin NVLink 6 交換器托盤拓撲中，每個連接器包含 72 組差動對。
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Atomic Claim 757/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0560::RESEG02
Claim: 每個 connector 的 72 個 differential pairs（DPs）與前代 NVLink 5 Switch Tray 相同。
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High speed signals require better PCB materials, especially for NVLink 6 which has much lower tolerance for insertion loss given the use of bidirectional signaling. The number of lanes between the PaladinHD2 connectors and the NVLink Switch also creates complexity for PCB design. Hence, the NVLink 6 Switch board PCB is upgraded to 32 layers with M8+ graded CCL—minimally LDK2 glass fiber cloth or potentially Quartz fiber cloth.
Atomic Claim 758/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0561
Claim: High-speed signals 需要更好的 PCB materials；尤其 NVLink 6 因採 bidirectional signaling，對 insertion loss 的 tolerance 更低。
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Atomic Claim 759/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0562
Claim: PaladinHD2 connectors 與 NVLink Switch 之間的 lane 數量，也提高了 PCB design complexity。
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Atomic Claim 760/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0563::SPLIT01
Claim: NVLink 6 交換器板的 PCB 升級至 32 層。
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Atomic Claim 761/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0563::SPLIT02
Claim: NVLink 6 交換器板的 PCB 使用 M8+ 等級 CCL。
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Atomic Claim 762/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0563::SPLIT03
Claim: The NVLink 6 switch board requires at least LDK2 glass fiber cloth.
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Atomic Claim 763/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0563::SPLIT04
Claim: NVLink 6 交換器板可能使用石英纖維布。
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Zooming out, backplane copper cables are used to connect NVLink Switch trays to the GPU trays for the VR NVL72 system. Although the bandwidth doubles, with bi-directional SerDes, the number of cables required does not change from the GB300 backplane generation to the Vera Rubin NVL72 backplane generation. The number of connectors and the number of DPs per connector also does not change from Grace Blackwell NVL72 to VR NVL72.
Atomic Claim 764/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0564
Claim: 從 rack-level 來看，VR NVL72 使用 backplane copper cables 連接 NVLink Switch trays 與 GPU trays。
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Atomic Claim 765/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0565
Claim: 雖然 bandwidth 翻倍，但因使用 bidirectional SerDes，從 GB300 backplane 到 Vera Rubin NVL72 backplane，所需 cable 數量並未增加。
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Atomic Claim 766/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0566::SPLIT01
Claim: 從 Grace Blackwell NVL72 到 VR NVL72，背板連接器數量維持不變。
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Atomic Claim 767/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0566::SPLIT02
Claim: 從 Grace Blackwell NVL72 到 VR NVL72，每個背板連接器的差動對數量維持不變。
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While the VR NVL72 system features GPUs and scale-up switches that are connected by copper cables, the VR HGX system features servers consisting of eight Rubin GPUs and four NVLink Switch chips. The second meaningful difference between the NVL72 and HGX deployments is that the former has a scale-out bandwidth of 1.6T per GPU while the latter only has a scale-out bandwidth of 800G per GPU.
Atomic Claim 768/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0605
Claim: Rubin NVL72 配置提供每顆 GPU 1.6T 的 scale-out 頻寬，HGX 則為每顆 GPU 800G。
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Atomic Claim 769/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0567::RESEG01
Claim: VR NVL72 system 的 GPUs 與 scale-up switches 透過 copper cables 連接。
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Atomic Claim 770/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0568::RESEG01
Claim: 每台 VR HGX server 包含 8 顆 Rubin GPUs。
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Atomic Claim 771/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0568::RESEG02
Claim: 每台 VR HGX server 包含 4 顆 NVLink Switch chips。
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The HGX Rubin NVL8 server consists of eight 800G CX-9 NIC packages—one NIC per GPU—which means that the scale-out bandwidth does not increase from its predecessor, the HGX B300 server. The Vera Rubin NVL72 deployment on the other hand doubles the per GPU scale-out bandwidth to 1.6T, but not by doubling the bandwidth per NIC. Rather, the “1.6T NIC” attached to each Rubin chip is comprised of two 800G CX-9 packages that is connected to the Vera CPU by PCIe Gen 6.0 lanes.
Atomic Claim 772/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0571::SPLIT01
Atomic Claim 773/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0571::SPLIT02
Atomic Claim 774/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0572
Claim: 相較之下，Vera Rubin NVL72 把每顆 GPU 的 scale-out bandwidth 翻倍至 1.6T，但不是藉由把單一 NIC bandwidth 翻倍。
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Atomic Claim 775/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0573::SPLIT01
Atomic Claim 776/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0573::SPLIT02
Claim: 每顆 Rubin 晶片連接的兩個 CX-9 封裝，透過 PCIe Gen 6.0 通道連接 Vera CPU。
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Each compute tray on the VR NVL72 has eight 800G CX-9 NICs, but there are two possibilities for the number of OSFP cages—either one 1.6T OSFP cage per GPU for a total of 4 per compute tray, or two 800G OSFP cages per GPU for a total of 8 cages per compute tray. We think that the latter would be the more popular deployment assumption.
Atomic Claim 777/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0574
Claim: VR NVL72 每個 compute tray 配置 8 顆 800G CX-9 NICs。
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Atomic Claim 778/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0575::SPLIT01
Claim: VR NVL72 的一種選項是每顆 GPU 使用一個 1.6T OSFP 插槽，每個運算托盤共四個。
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Atomic Claim 779/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0575::SPLIT02
Claim: VR NVL72 的另一種選項是每顆 GPU 使用兩個 800G OSFP 插槽，每個運算托盤共八個。
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Atomic Claim 780/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0576
Claim: SemiAnalysis 認為後者，也就是每顆 GPU 配 2 個 800G OSFP cages 的方案，會是更普遍的 deployment assumption。
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Connecting GPUs in the Scale-Out InfiniBand Network
Broadly, there are three flavors of scale-out deployments for Vera Rubin NVL72. We have InfiniBand-based clusters which employ the NVIDIA Quantum series of switches, NVIDIA Ethernet-based clusters employing Spectrum series switches and lastly, non-Nvidia Ethernet such as Tomahawk-based, Cisco Silicon One or Teralynx-based Ethernet switches.
Some Ethernet-based clusters deployed by hyperscalers will use AECs for NIC-to-TOR and switch-to-switch connections, while other Ethernet-based clusters using only optical interconnects will usually adopt a multi-plane and multi-rail networking architecture. What is particularly noteworthy about Vera Rubin NVL72 deployments, however, is that it is the first Nvidia GPU generation where we will be seeing some Co-Packaged-Optics (CPO) deployments in the scale-out backend network.
Atomic Claim 781/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0615
Claim: 以 InfiniBand 為基礎的 VR NVL72 scale-out 選項使用 Nvidia Quantum 交換器。
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Atomic Claim 782/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0616
Claim: Nvidia Ethernet 的 VR NVL72 scale-out 選項使用 Spectrum 交換器。
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Atomic Claim 783/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0617
Claim: 第三類則是非 Nvidia Ethernet 方案。
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Atomic Claim 784/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0618
Claim: VR NVL72 的非 Nvidia Ethernet scale-out 選項包含採用 Tomahawk 的交換器。
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Atomic Claim 785/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0619
Claim: 第三類也包含 Cisco Silicon One。
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Atomic Claim 786/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0620
Claim: 採用 Teralynx 的 Ethernet 交換器，是 VR NVL72 的非 Nvidia scale-out 選項。
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Atomic Claim 787/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0580::SPLIT01
Claim: 部分 hyperscaler 的 Ethernet 叢集將使用 AEC 連接 NIC 與 TOR。
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Atomic Claim 788/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0580::SPLIT02
Claim: 部分 hyperscaler 的 Ethernet 叢集將使用 AEC 連接交換器與交換器。
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Atomic Claim 789/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0581
Claim: 其他只使用 optical interconnects 的 Ethernet-based clusters，通常會採 multi-plane、multi-rail networking architecture。
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Atomic Claim 790/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0582
Claim: 原文預期：Vera Rubin NVL72 是第一個會在 scale-out backend network 中看到部分 Co-Packaged-Optics deployments 的 Nvidia GPU generation。
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While there are both InfiniBand and Spectrum-X based clusters, the InfiniBand-based Quantum X800-34XX series of switches is more popular with Neoclouds than with hyperscalers. For InfiniBand, there are two deployment types—the first is the Quantum X800-Q3400 with pluggable optics and the second is the Quantum X800-Q3450 CPO-based switch that use co-packaged Optical Engines (OE) instead of pluggable transceivers.
Atomic Claim 791/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0624
Claim: 雖然同時有 InfiniBand 與 Spectrum-X cluster，但 InfiniBand-based Quantum X800-34XX series switches 在 Neoclouds 中比在 hyperscalers 中更普遍。
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Atomic Claim 792/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0585
Claim: 對 InfiniBand 而言有兩種 deployment types；第一種是 Quantum X800-Q3400，使用 pluggable optics。
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Atomic Claim 793/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0586
Claim: 第二種是 Quantum X800-Q3450 CPO-based switch，使用 co-packaged Optical Engines，而不是 pluggable transceivers。
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The Quantum X800-Q3400 is logically a multi-plane switch combining 4 Quantum-3 ASICs into a single switch box. This multi-plane “topology” is abstracted away and as far as network engineers are concerned, the Q3400 is a single switch with 144 ports—or a “little boy” switch.
Atomic Claim 794/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0627
Claim: 關於 InfiniBand：這種 multi-plane「topology」被抽象化；對 network engineers 而言，Q3400 就是一台 144-port switch，也就是文中所稱的「little boy」switch。
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Atomic Claim 795/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0587
Claim: Quantum X800-Q3400 在 logical 上是一個 multi-plane switch，把 4 顆 Quantum-3 ASICs 整合在單一 switch box 內。
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The InfiniBand architecture for the HGX Rubin NVL8 server is therefore effectively a single-plane, 8-rail network consisting of one 800G uplink from each HGX Rubin NVL8 GPU to a leaf switch.
Atomic Claim 796/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0590
Claim: 因此，HGX Rubin NVL8 server 的 InfiniBand architecture，實際上相當於 single-plane、8-rail network；每顆 HGX Rubin NVL8 GPU 各有一條 800G uplink 連到 leaf switch。
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For the Vera Rubin NVL72 deployment however, there are two 800G OSFP cages per GPU for a total of 1.6T per GPU bandwidth. Having two 800G logical ports per GPU is advantageous because it allows multi-plane network deployments without complex fiber management—by splitting one logical GPU two ways to two different leaf switches. As such, larger network clusters can be built with two 800G logical ports than if only one 1.6T logical port were used.
The maximum number of hosts that can be supported using a switch of k ports on an L-layer is:
Atomic Claim 797/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0591
Claim: 但在 Vera Rubin NVL72 deployment 中，每顆 GPU 有 2 個 800G OSFP cages，因此每顆 GPU 合計 bandwidth 為 1.6T。
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Atomic Claim 798/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0592::SPLIT01
Claim: 在 VR NVL72 每顆 GPU 配置兩個 800G 邏輯埠的架構中，一個邏輯 GPU 可連接兩台不同的 leaf 交換器。
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Atomic Claim 799/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0592::SPLIT02
Claim: VR NVL72 每顆 GPU 配置兩個 800G 邏輯埠的架構，可在無需複雜光纖管理的情況下部署多平面網路。
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Atomic Claim 800/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0593
Claim: 因此，相較只使用 1 個 1.6T logical port，使用 2 個 800G logical ports 可以建立更大的 network clusters。
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Illustratively, consider two hypothetical VR NVL deployments with 1.6T and 800G logical ports respectively. A 1-plane, 3-layer network with one 1.6T logical port achieves only a maximum cluster size of 93,312 GPUs:
Atomic Claim 801/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0596
Claim: 在原文所述假設情境中，1-plane、3-layer network 若使用單一 1.6T logical port，maximum cluster size 僅為 93,312 顆 GPUs。
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(2\left(\frac{\frac{115{,}200}{1{,}600}}{2}\right)^3 = 2\left(\frac{72}{2}\right)^3 = 93,312)
Atomic Claim 802/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0597
Claim: 在原文所述假設情境中，上述 93,312 GPUs 的計算式為：(2\left(\frac{\frac{115{,}200}{1{,}600}}{2}\right)^3 = 2\left(\frac{72}{2}\right)^3 = 93,312)。
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By one 1.6T logical port, we mean that the two 800G OSFP cages connected to each GPU are connected to a single, dual-port 1.6T transceiver at the leaf layer because the two 800G ports are effectively performing the function of one 1.6T port—and hence the term “logical”.
Atomic Claim 803/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0598
Claim: 所謂 1 個 1.6T logical port，是指每顆 GPU 連接的 2 個 800G OSFP cages，在 leaf layer 接到單一 dual-port 1.6T transceiver；因為兩個 800G ports 實際共同執行一個 1.6T port 的功能，所以稱為 logical。
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To scale beyond the maximum cluster size of 93,312 GPUs, a 2-plane network can be deployed in which each of the two 800G OSFP cages supporting a GPU are linked to separate leaf switches on different network planes. This allows you to build a 186,624-GPU cluster size and even scale up to 746,496-GPU cluster sizes:
Atomic Claim 804/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0599
Claim: 在原文所述假設情境中，要超過 93,312 顆 GPU 的 maximum cluster size，可以部署 2-plane network：每顆 GPU 的兩個 800G OSFP cages 分別連到不同 network planes 上的 leaf switches。
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Atomic Claim 805/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0600::EPI01
Claim: 在假設的雙平面、800G 埠 VR NVL 部署中，圖示配置可建立 186,624 顆 GPU 的叢集。
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Atomic Claim 806/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0600::EPI02
Claim: 在假設的 800G 埠 VR NVL 部署中，依來源的網路假設，可擴展至 746,496 顆 GPU。
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(2\left(\frac{\frac{115{,}200}{800}}{2}\right)^3 = 2\left(\frac{144}{2}\right)^3 = 746,496)
Atomic Claim 807/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0601
Claim: 在原文所述假設情境中，746,496 GPUs 的計算式為：(2\left(\frac{\frac{115{,}200}{800}}{2}\right)^3 = 2\left(\frac{144}{2}\right)^3 = 746,496)。
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We think the second cluster with two switch planes will likely be the more prevalent reference architecture for Vera Rubin NVL72 InfiniBand deployments.
Atomic Claim 808/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0602
Claim: SemiAnalysis 認為，採 2 個 switch planes 的第二種 cluster，可能會成為 Vera Rubin NVL72 InfiniBand deployments 更常見的 reference architecture。
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Aside from the X800-Q3400 air-cooled switch, NVIDIA will also offer a CPO version, the X800-Q3450, containing the same 144 ports of 800G. Each switch box consists of four 28.8T Quantum-3 Switch ASICs for a total of 115.2T per box switching capacity. When used in conjunction with the VR NVL72 servers, the signal from the NIC at the leaf layer is split four ways—200G each way—to each switch ASIC within the box.
Such a configuration bears logical equivalence to a 4-plane network architecture.
Atomic Claim 809/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0603::SPLIT01
Claim: Nvidia 將提供 CPO 版本的 X800-Q3450，與氣冷 X800-Q3400 並列。
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Atomic Claim 810/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0603::SPLIT02
Claim: X800-Q3450 將有 144 個 800G 埠，與 X800-Q3400 相同。
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Atomic Claim 811/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0604
Claim: 每個 switch box 包含 4 顆 28.8T Quantum-3 Switch ASICs，每 box 總 switching capacity 為 115.2T。
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Atomic Claim 812/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0605
Claim: 搭配 VR NVL72 servers 時，leaf layer 的 NIC signal 會分成 4 路，每路 200G，分別送到 box 內各顆 switch ASIC。
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Atomic Claim 813/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0606
Claim: VR NVL72 的 Quantum 交換器將連線扇出為四條 200G 路徑，在邏輯上等同四平面網路。
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Ethernet-Based Cluster Deployments
Although InfiniBand has been the more popular network architecture for previous NVIDIA chips such as the H100 and GB200, NVIDIA is aggressively pushing out Spectrum Ethernet-based networks and have introduced various switch SKUs:
Atomic Claim 814/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0645
Claim: 在 H100 與 GB200 平台過去較普遍採用 InfiniBand 之後，Nvidia 正在推廣 Spectrum Ethernet 網路。
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- SN6600, a 102.4T liquid-cooled switch;
Atomic Claim 815/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0609
Claim: SN6600 是 102.4T liquid-cooled switch。
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Atomic Claim 816/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT01
Claim: SN6800 包含四顆 ASIC。
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Atomic Claim 817/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT02
Claim: SN6800 的 radix 為 2048。
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Atomic Claim 818/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT03
Claim: SN6800 提供 409.6T 交換頻寬。
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Atomic Claim 819/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT04
Claim: SN6800 是多平面 CPO 交換器。
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Atomic Claim 820/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT05
Claim: SN6800 提供 512 個 800G 埠。
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- SN6810, a high-radix 102.4T CPO switch with three further deployment options: 512 ports of 200G, 256 ports of 400G and 128 ports of 800G.
Atomic Claim 821/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0611::SPLIT01
Claim: SN6810 是高 radix 的 102.4T CPO 交換器。
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Atomic Claim 822/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0611::SPLIT02
Claim: SN6810 支援 512 個 200G 埠的部署選項。
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Atomic Claim 823/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0611::SPLIT03
Claim: SN6810 支援 256 個 400G 埠的部署選項。
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Atomic Claim 824/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0611::SPLIT04
Claim: SN6810 支援 128 個 800G 埠的部署選項。
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For the SN6600 switch, the scale-out reference architecture is an 8-plane network where each GPU fans out eight ways to eight different planes. This is similar to the reference architecture for the 8-plane scale-out network using SN6810 switches.
Atomic Claim 825/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0612
Claim: 對 SN6600 而言，scale-out reference architecture 是 8-plane network，每顆 GPU 分成 8 路連到 8 個不同 planes。
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Atomic Claim 826/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0613
Claim: 這與使用 SN6810 switches 的 8-plane scale-out reference architecture 類似。
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We think that the SN6800 switch with 512 ports of 800G will be quite attractive to Neoclouds because it simplifies deployments. Similar to the X800-Q3400 scale-out network, an SN6800 scale-out network could consist of two switch planes though the SN6800 enables a much larger feasible scale-out world size.
Atomic Claim 827/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0614
Claim: SemiAnalysis 認為，具有 512 個 800G ports 的 SN6800 對 Neoclouds 會相當有吸引力，因為它能簡化 deployments。
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Atomic Claim 828/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0615
Claim: 類似 X800-Q3400 scale-out network，SN6800 的 scale-out network 也可能採 2 個 switch planes，但 SN6800 可支援更大的 feasible scale-out world size。
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For a 512-port switch, we can connect up to 131,072 GPUs with two layers of switches or a ludicrous 33,554,432 GPUs on 3 layers.
Atomic Claim 829/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0616::SPLIT01
Claim: 使用 512 埠交換器時，兩層交換器最多可連接 131,072 顆 GPU。
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Atomic Claim 830/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0616::SPLIT02
Claim: 使用 512 埠交換器時，三層交換器最多可連接 33,554,432 顆 GPU。
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(2\left(\frac{512}{2}\right)^2 = 131,072)
(2\left(\frac{512}{2}\right)^3 = 33,554,432)
What advantages do CPO switches such as the SN6800 deliver for Neoclouds like Coreweave and Lambda when it comes to large-scale cluster deployments?
The first reason is that a significant amount of power can be saved by eliminating most of the transceiver content. If we compare the power consumption of one 800G DR4 optical transceiver (16-17W) to the power required by optical engines (OEs) and external light source (ELS) modules to deliver an equivalent 800G of bandwidth in the scale-out network, we see an average ~70% reduction in power used for optical transceivers.
Taking a step back, this would translate to 10% in savings for the total networking equipment power consumption in a 3-Layer HGX Rubin NVL8 cluster. This reduction in networking equipment power consumption is however relatively insignificant and amounts to only ~1% of total cluster power consumption because the server’s power budget dominates the equation.
Atomic Claim 831/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0659
Claim: 把單顆 800G DR4 optical transceiver 的 16–17W 功耗，與在 scale-out network 中用 optical engines（OE）及 external light source（ELS）modules 提供等效 800G bandwidth 的功耗相比，optical transceivers 相關 power 平均可降低約 70%。
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Atomic Claim 832/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0619
Claim: 第一個理由是：移除大部分 transceiver content，可以節省大量 power。
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Atomic Claim 833/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0622
Claim: 拉到整體系統看，這相當於 3-layer HGX Rubin NVL8 cluster 的 total networking equipment power consumption 節省約 10%。
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Atomic Claim 834/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0623
Claim: 不過，這個 networking equipment power reduction 相對有限，只約占 total cluster power consumption 的 1%，因為 server power budget 才是主要部分。
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The second benefit is a reduction in cost stemming from eliminating almost all transceivers. There is even more room for price reduction if we are looking at NVIDIA LinkX transceivers, which tend to be priced at significant premium to their generic equivalent. If we compare total networking costs for a 3-Layer network with and without CPO-based switches in the scale-out domain, we see an average of ~75% reduction in transceiver costs.
However, as with the power savings above, such cost savings tend not to move the needle dramatically considering the full cluster costs.
Atomic Claim 835/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0624
Claim: CPO 的第二項優勢是降低成本，主要來自幾乎移除所有 transceivers。
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Atomic Claim 836/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0625
Claim: 若比較 NVIDIA LinkX transceivers，降價空間可能更大，因為 LinkX 相較 generic equivalents 通常具有顯著 premium。
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Atomic Claim 837/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0627
Claim: 比較 scale-out domain 使用與不使用 CPO-based switches 的 3-layer network，採用 CPO 後 transceiver cost 平均約可降低 75%。
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Atomic Claim 838/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0628
Claim: SemiAnalysis 判斷，模型中的 CPO 收發器成本節省對叢集總成本的影響有限。
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Increased overall network reliability is another compelling point. Transceivers can be unreliable, with a large cluster certain to have ongoing link flaps. Meta’s study presented at ECOC showed strong reliability results over 15M 400G port-device hours, which is about equivalent 15 CPO switches tested for 11 months in a lab. It is an encouraging start—but we think this point could get stronger with more in-field test deployments.
Atomic Claim 839/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0629
Claim: 提升整體 network reliability 是採用 CPO 的另一項重要優勢。
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Atomic Claim 840/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0630
Claim: 關於 Ethernet：Transceivers 可能存在可靠性問題。
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Atomic Claim 841/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0631
Claim: 在大型 cluster 中，持續發生 link flaps 幾乎是不可避免的。
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Atomic Claim 842/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0632
Claim: Meta 在 ECOC 發表的研究顯示，經過 1,500 萬個 400G port-device hours 測試後，CPO 顯示出良好的可靠性；這約等同於 15 台 CPO switches 在實驗室中測試 11 個月。
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Atomic Claim 843/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0633
Claim: SemiAnalysis 認為 Meta 的 CPO 可靠性測試令人鼓舞，但仍希望看到更多實際部署證據。
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The last factor in favor of adoption of CPO is the fact that some of Nvidia’s CPO switch SKUs contain the integrated fiber shuffle and can simplify the installation and maintenance of multi-plane network architectures.
Recall that the SN6800 contains four Switch ASICs in a multi-plane configuration connected to ports via an integrated fiber shuffle, delivering 409.6T aggregate bandwidth, while the SN6810 uses one Switch ASIC, but without any integrated fiber shuffle, to deliver 102.4T aggregate bandwidth.
Atomic Claim 844/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0675
Claim: SN6810 使用 1 顆 Switch ASIC。
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Atomic Claim 845/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0634
Claim: 支持採用 CPO 的最後一項因素，是 Nvidia 部分 CPO switch SKUs 內建 integrated fiber shuffle。
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Atomic Claim 846/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0635
Claim: 這種 integrated fiber shuffle 可以簡化 multi-plane network architecture 的安裝與維護。
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Atomic Claim 847/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0636::SPLIT01
Claim: SN6800 在多平面配置中包含四顆交換 ASIC。
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Atomic Claim 848/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0636::SPLIT02
Claim: SN6800 透過整合式 fiber shuffle 將 ASIC 連接至埠。
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Atomic Claim 849/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0636::SPLIT03
Claim: SN6800 提供 409.6T 總頻寬。
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Atomic Claim 850/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0637::SPLIT02
Claim: SN6810 沒有整合式 fiber shuffle。
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Atomic Claim 851/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0637::SPLIT03
Claim: SN6810 提供 102.4T 總頻寬。
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Atomic Claim 852/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-networking-2
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在兩層網路情境中，採用 CPO 相較未採用 CPO，網路功耗變動為 -15%。
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Atomic Claim 853/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-networking-3
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在三層網路情境中，採用 CPO 相較未採用 CPO，網路功耗變動為 -10%。
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Atomic Claim 854/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-optical transceivers-2
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在兩層網路情境中，採用 CPO 相較未採用 CPO，光收發器功耗變動為 -78%。
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Atomic Claim 855/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-optical transceivers-3
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在三層網路情境中，採用 CPO 相較未採用 CPO，光收發器功耗變動為 -64%。
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Atomic Claim 856/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-switches-2
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在兩層網路情境中，採用 CPO 相較未採用 CPO，交換器功耗變動為 +22%。
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Atomic Claim 857/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-switches-3
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在三層網路情境中，採用 CPO 相較未採用 CPO，交換器功耗變動為 +23%。
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Atomic Claim 858/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-total-2
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在兩層網路情境中，採用 CPO 相較未採用 CPO，總功耗變動為 -1%。
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Atomic Claim 859/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-total-3
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在三層網路情境中，採用 CPO 相較未採用 CPO，總功耗變動為 -1%。
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Atomic Claim 860/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-networking-2
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在兩層網路情境中，採用 CPO 相較未採用 CPO，網路資本成本變動為 -18%。
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Atomic Claim 861/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-networking-3
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在三層網路情境中，採用 CPO 相較未採用 CPO，網路資本成本變動為 -9%。
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Atomic Claim 862/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-optical transceivers-2
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在兩層網路情境中，採用 CPO 相較未採用 CPO，光收發器資本成本變動為 -80%。
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Atomic Claim 863/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-optical transceivers-3
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在三層網路情境中，採用 CPO 相較未採用 CPO，光收發器資本成本變動為 -68%。
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Atomic Claim 864/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-switches-2
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在兩層網路情境中，採用 CPO 相較未採用 CPO，交換器資本成本變動為 +72%。
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Atomic Claim 865/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-switches-3
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在三層網路情境中，採用 CPO 相較未採用 CPO，交換器資本成本變動為 +81%。
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Atomic Claim 866/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-total-2
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在兩層網路情境中，採用 CPO 相較未採用 CPO，總資本成本變動為 -2%。
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Atomic Claim 867/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-total-3
Claim: 2 月的 Rubin NVL8 HGX neocloud InfiniBand 模型估計，在三層網路情境中，採用 CPO 相較未採用 CPO，總資本成本變動為 -1%。
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Large-scale cluster deployments where cluster sizes exceed 100k GPUs typically utilize multi-plane network architectures because single-plane network architectures do not have enough logical ports at current switch generations to support larger networks without resorting to a high number of switch layers of 3 or more layers.
Atomic Claim 868/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0638
Claim: 超過 10 萬顆 GPU 的大型 cluster 通常採用 multi-plane network architecture，因為現世代 switch 的 single-plane architecture 沒有足夠 logical ports；若要支援更大 network，否則通常必須增加到 3 層以上的 switch layers。
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Recall from above that a Vera Rubin NVL72 cluster built with Q3400-X800 switches at 1.6T logical ports per GPU cannot scale beyond the maximum cluster size of 93,312 GPUs. Even if future switch generations continue to double the maximum possible switching capacity per switch box, the per GPU bandwidth is also expected to double, which means that the effective logical port count in a cluster network is unlikely to change.
Atomic Claim 869/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0639
Claim: 以 Q3400-X800 switches 建構、每顆 GPU 使用 1.6T logical port 的 Vera Rubin NVL72 cluster，最大規模無法超過 93,312 顆 GPU。
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Atomic Claim 870/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0640
Claim: 即使未來每一代 switch 的單一 switch box 最大 switching capacity 繼續倍增，每顆 GPU 的 bandwidth 也預期會同步倍增，因此 cluster network 的有效 logical port 數量可能不會明顯改變。
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What this means is that deployment of large-scale GPU clusters will continue to require multi-plane network architectures. Do note however that multi-plane networking architectures are not limited by size and we have also seen NVIDIA reference architecture deployments with multi-plane clusters that are significantly below 100k GPUs each.
Atomic Claim 871/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0641
Claim: 這表示大型 GPU cluster 的部署未來仍會需要 multi-plane network architecture。
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Atomic Claim 872/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0642
Claim: 不過，multi-plane networking architecture 並不是只有大型 cluster 才會使用。
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Atomic Claim 873/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0643
Claim: SemiAnalysis 觀察到，Nvidia 參考多平面叢集的 GPU 數量遠低於 100,000 顆。
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In multi-plane network architectures using the SN6600 switch instead of the CPO switch, each GPU fans out to multiple switch boxes using fiber shuffles. This requires customers to deploy shuffle boxes, patch panels and unwieldy octopus cables outside the switch box that introduce complexity in installation and maintenance.
Atomic Claim 874/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0644
Claim: 在使用 SN6600 switch、而非 CPO switch 的 multi-plane network architecture 中，每顆 GPU 會透過 fiber shuffles fan out 到多個 switch boxes。
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Atomic Claim 875/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0645::SPLIT01
Claim: SN6600 多平面網路要求客戶在交換器機箱外部署 shuffle box。
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Atomic Claim 876/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0645::SPLIT02
Claim: SN6600 多平面網路要求客戶在交換器機箱外部署配線面板。
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Atomic Claim 877/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0645::SPLIT03
Claim: SN6600 多平面網路要求客戶在交換器機箱外部署 octopus 纜線。
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Atomic Claim 878/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0645::SPLIT04
Claim: 外部 shuffle box、配線面板與 octopus 纜線，使 SN6600 多平面網路的安裝與維護更複雜。
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Some of Nvidia’s CPO SKUs—such as the SN6800 and Q3450—contain such a fiber shuffle within the switch box, with each optical engine fanning out to different logical ports. They therefore deliver higher aggregate bandwidth—409.6T and 115.2T respectively—than is possible with a switch box based on a single Switch ASIC.
Atomic Claim 879/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0686
Claim: 所討論的多 ASIC、整合 shuffle 的交換器 SN6800 與 Q3450，分別提供 409.6T 與 115.2T 總頻寬，高於單 ASIC 交換器。
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Atomic Claim 880/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0646::SPLIT01
Claim: Nvidia 的 SN6800 將 fiber shuffle 整合在交換器機箱內。
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Atomic Claim 881/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0646::SPLIT02
Claim: Nvidia 的 Q3450 將 fiber shuffle 整合在交換器機箱內。
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Atomic Claim 882/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0646::SPLIT03
Claim: 在這些整合 shuffle 的 CPO SKU 中，每個光引擎扇出至不同的邏輯埠。
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For the SN6800 CPO switch, even though the bandwidth engine responsible for converting electrical to optical signals scales from 1.6T to 3.2T or 2x compared to the SN6600 switch, each 3.2T OE within the SN6800 switch box is split into four 800G logical ports that fan out within the box itself and exit the front panel through fiber connectors. This allows a single 1.6T GPU to fan out to two independent switch planes.
In fact, the SN6800 switch box consists of four ASICs, which is similar to the X800-Q3400 switch box.
Atomic Claim 883/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0649::SPLIT01
Claim: SN6800 CPO 交換器將電轉光引擎頻寬，由 SN6600 的 1.6T 加倍至 3.2T。
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Atomic Claim 884/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0649::SPLIT02
Claim: 每個 SN6800 的 3.2T 光引擎在機箱內分成四個 800G 邏輯埠。
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Atomic Claim 885/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0649::SPLIT03
Claim: SN6800 在內部扇出的光引擎埠，透過光纖連接器從前面板引出。
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Atomic Claim 886/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0650
Claim: 在 SN6800 參考網路中，具備 1.6T scale-out 連線的 GPU，可扇出至兩個獨立的交換平面。
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Atomic Claim 887/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0651::SPLIT01
Claim: SN6800 交換器機箱包含四顆 ASIC。
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Atomic Claim 888/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0651::SPLIT02
Claim: 四 ASIC 的 SN6800 交換器機箱，在架構上與 X800-Q3400 相似。
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As the per GPU bandwidth continues to scale to 3.2T, it is not hard to imagine a 4-plane network using SN6800 switches, where each 3.2T GPU is split four ways to connect to four different switch boxes at 800G per link.
Atomic Claim 889/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0652
Claim: 在原文所述假設情境中，隨著每顆 GPU bandwidth 提升到 3.2T，可以設想使用 SN6800 switches 的 4-plane network：每顆 3.2T GPU 分成 4 路，以每條 800G link 連到 4 個不同 switch boxes。
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There are strong parallels between the X800-Q3400 switch and a CPO switch in that both facilitate high-radix, multi-plane networking architectures while encasing within the box complex cabling that saves customers on the hassle of cable management.
Atomic Claim 890/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0653
Claim: X800-Q3400 switch 與 CPO switch 有明顯相似性：兩者都能支援 high-radix、multi-plane networking architecture。
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Atomic Claim 891/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0654
Claim: X800-Q3400 與所比較的 Nvidia CPO 交換器，都將複雜纜線配置封裝在交換器機箱內。
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Outside of the NVIDIA ecosystem, the main switch ASIC players are Broadcom, which will be manufacturing the Tomahawk 6 and Tomahawk 6 CPO ASICs, as well as Cisco, which recently announced the G300 102.4T ASIC. There are two flavors of hyperscaler backend network deployments:
Atomic Claim 892/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT01
Claim: Broadcom 是 Nvidia 生態系以外的主要交換 ASIC 業者。
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Atomic Claim 893/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT02
Claim: Cisco 是 Nvidia 生態系以外的主要交換 ASIC 業者。
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Atomic Claim 894/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT03
Claim: Broadcom 將製造 Tomahawk 6 ASIC。
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Atomic Claim 895/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT04
Claim: Broadcom 將製造 Tomahawk 6 CPO ASIC。
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Atomic Claim 896/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT05
Claim: Cisco 最近公布了 102.4T G300 ASIC。
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- 8-plane “flat” network utilizing the full 512 switch radix;
Atomic Claim 897/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0657
Claim: 關於 Ethernet：第一種是 8-plane「flat」network，使用完整 512 switch radix。
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- Single plane network with 1.6T OSFP cages at the NIC.
Atomic Claim 898/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0658
Claim: 第二種 hyperscaler backend deployment 是 single-plane network，NIC 端使用 1.6T OSFP cages。
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For Meta, we think the VR NVL72 deployments will comprise only of non-scheduled fabric (NSF) clusters built using Tomahawk 6-based Minipack-4 OCP Rack 102.4T switches in each datacenter. While Meta will be using optics to connect all the switches within its cluster, it will use 1.6T AECs for NIC-to-TOR connections once 1.6T AECs become broadly available in the market. We expect the 1.6T AEC ramp to happen in the second half of calendar year 2026.
Atomic Claim 899/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0659
Claim: SemiAnalysis 認為，Meta 的 VR NVL72 deployments 將只採用 non-scheduled fabric（NSF）clusters，並在每個 datacenter 使用以 Tomahawk 6 為基礎的 Minipack-4 OCP Rack 102.4T switches。
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Atomic Claim 900/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0660::SPLIT01
Claim: SemiAnalysis 預期 Meta 將使用光學互連，連接其 VR NVL72 叢集內的所有交換器。
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Atomic Claim 901/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0660::SPLIT02
Claim: SemiAnalysis 預期，在 1.6T AEC 廣泛供應後，Meta 將用其連接 NIC 與 TOR。
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Atomic Claim 902/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0661
Claim: SemiAnalysis 預期 1.6T AEC 將在 2026 年下半年開始 ramp。
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The catch is that 102.4T Minipack-4 switches may not be shipped in time for Vera Rubin NVL72 rack deployments, and if this were to be the case, some NSF clusters will be shipped using 51.2T Minipack-3 switches instead. This means that gearboxes within the AECs will have to be used to convert 200G per lane SerDes speed at the NIC to 100G per lane SerDes speed at the switch.
Atomic Claim 903/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0662
Claim: 102.4T Minipack-4 交換器可能無法及時出貨，以配合 Meta 的 VR NVL72 機櫃部署。
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Atomic Claim 904/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0663
Claim: 如果 102.4T Minipack-4 switches 無法及時出貨，部分 NSF clusters 將改用 51.2T Minipack-3 switches。
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Atomic Claim 905/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0664
Claim: 這表示 AEC 內的 gearboxes 必須把 NIC 端每 lane 200G 的 SerDes speed，轉換成 switch 端每 lane 100G 的 SerDes speed。
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Meta will not be the only hyperscaler using 1.6T AECs for its VR200 deployments. We think xAI will use 1.6T AECs for both NIC-to-TOR and switch-to-switch connectivity at the leaf, spine and core layers. It will be a single-plane network replacing most 1.6T transceivers at the switch boxes—and this can give Credo plenty of pricing power.
Atomic Claim 906/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0665
Claim: 原文預期：Meta 不會是唯一在 VR200 deployments 採用 1.6T AEC 的 hyperscaler。
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Atomic Claim 907/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0666::SPLIT01
Claim: SemiAnalysis 預期 xAI 的 VR200 部署將使用 1.6T AEC 連接 NIC 與 TOR。
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Atomic Claim 908/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0666::SPLIT02
Claim: SemiAnalysis 預期 xAI 的 VR200 部署將使用 1.6T AEC 連接 leaf 層的交換器。
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Atomic Claim 909/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0666::SPLIT03
Claim: SemiAnalysis 預期 xAI 的 VR200 部署將使用 1.6T AEC 連接 spine 層的交換器。
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Atomic Claim 910/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0666::SPLIT04
Claim: SemiAnalysis 預期 xAI 的 VR200 部署將使用 1.6T AEC 連接 core 層的交換器。
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Atomic Claim 911/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0667::SPLIT01
Claim: 提出的 xAI 1.6T AEC 網路將採用單平面架構。
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Atomic Claim 912/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0667::SPLIT02
Claim: 提出的 xAI AEC 網路將取代交換器端大多數 1.6T 收發器。
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Atomic Claim 913/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0667::SPLIT03
Claim: 提出的 xAI AEC 網路可能讓 Credo 取得相當大的定價能力。
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Hyperscaler Customization and Assembly Logistics
Customization
For GB300, although the reference design has four ConnectX-8 NICs for the backend network and one Bluefield-3 for frontend network, most hyperscalers have their own design and alternative networking configurations, especially for Bluefield-3. Beside networking configuration, the power delivery modules, the local NVMe storage, and the management module are also highly customized and differentiated across customers.
Atomic Claim 914/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0668
Claim: GB300 reference design 的 backend network 配置 4 張 ConnectX-8 NIC。
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Atomic Claim 915/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0669::SPLIT01
Claim: GB300 參考設計使用一個 BlueField-3 處理前端網路。
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Atomic Claim 916/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0669::SPLIT02
Claim: 大多數 hyperscaler 有自己的 GB300 網路配置，尤其是 BlueField-3 的替代方案。
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Atomic Claim 917/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0670::SPLIT01
Claim: GB300 供電模組高度客製化，且客戶之間差異明顯。
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Atomic Claim 918/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0670::SPLIT02
Claim: GB300 本地 NVMe 儲存裝置高度客製化，且客戶之間差異明顯。
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Atomic Claim 919/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0670::SPLIT03
Claim: GB300 管理模組高度客製化，且客戶之間差異明顯。
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For example, for some racks, even Amazon is deploying ConnectX-8 in GB300s in many cases. Also, most hyperscalers are deploying their in-house DPU instead of Bluefield-3 for frontend networking. The power delivery module and management modules in GB300 are also highly customized as every customer has differing preferences for these modules. As such, the front half of GB300 is highly customizable with each hyperscalers’ design differing from each other significantly.
Atomic Claim 920/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0671
Claim: 例如在部分 racks 中，Amazon 在許多 GB300 deployments 也會採用 ConnectX-8。
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Atomic Claim 921/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0672
Claim: 多數 hyperscalers 在 frontend networking 會部署自研 DPU，而不是 BlueField-3。
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Atomic Claim 922/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0673::SPLIT01
Claim: 由於客戶偏好不同，GB300 供電模組高度客製化。
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Atomic Claim 923/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0673::SPLIT02
Claim: 由於客戶偏好不同，GB300 管理模組高度客製化。
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Atomic Claim 924/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0674
Claim: 因此，GB300 的前半部具有高度客製化能力，不同 hyperscaler 的設計彼此差異很大。
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For VR NVL72, although some level of customization is still available, there are a lot more limitations on the form factor. Given the modular and the cableless design of VR NVL72, the customized modules at the front of the chassis must match the form factor and dimension of Nvidia’s reference design. The modules available for customization are power delivery, Bluefield-4, and management modules. We expect most hyperscaler customers to adopt their in-house DPU instead of Bluefield-4.
Given the limitation on form factor and dimensions, hyperscalers are redesigning the board layout and module form factor of their in-house DPU to match that of Bluefield-4. For the power delivery modules and management, some customers are also looking to combine them. Amazon does have a JBOK / Nitro Box NIC version for VR NVL72.
Atomic Claim 925/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0675
Claim: VR NVL72 雖然仍保留一定程度的客製化空間，但在 form factor 上的限制比 GB300 更多。
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Atomic Claim 926/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0676
Claim: 由於 VR NVL72 採用 modular 與 cableless design，chassis 前方的客製化 modules 必須符合 Nvidia reference design 的 form factor 與尺寸。
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Atomic Claim 927/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0677::SPLIT01
Claim: VR NVL72 允許在參考設計的外形與尺寸限制內，客製化供電模組。
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Atomic Claim 928/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0677::SPLIT02
Claim: VR NVL72 允許在參考設計的外形與尺寸限制內，客製化 BlueField-4 模組。
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Atomic Claim 929/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0677::SPLIT03
Claim: VR NVL72 允許在參考設計的外形與尺寸限制內，客製化管理模組。
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Atomic Claim 930/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0678
Claim: SemiAnalysis 預期多數 hyperscaler 客戶會採用自研 DPU，而不是 BlueField-4。
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Atomic Claim 931/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0679
Claim: 受到 form factor 與尺寸限制，hyperscalers 正重新設計自研 DPU 的 board layout 與 module form factor，使其符合 BlueField-4 的規格。
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Atomic Claim 932/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0680
Claim: 部分 VR NVL72 客戶正在考慮整合供電模組與管理模組。
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Atomic Claim 933/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0681
Claim: Amazon 為 VR NVL72 提供一種 JBOK / Nitro Box NIC 版本。
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Assembly Automation and Logistics
At CES 2026, Jensen mentioned that with the streamlined cableless design and automation assembly process, compute tray assembly time has significantly reduced from 2 hours to 5 minutes from Blackwell to Rubin. There are only three L10 level compute tray assembly partners with automation capability for the Rubin platform—Foxconn, Quanta, and Wistron.
Atomic Claim 934/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0683
Claim: Jensen 在 CES 2026 表示，cableless design 配合自動化 assembly，使 compute-tray 組裝時間從 Blackwell 的兩小時縮短為 Rubin 的五分鐘。
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Atomic Claim 935/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0684::SPLIT01
Claim: Foxconn is one of the only three Rubin L10 compute-tray assembly partners with automation capability.
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Atomic Claim 936/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0684::SPLIT02
Claim: Quanta is one of the only three Rubin L10 compute-tray assembly partners with automation capability.
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Atomic Claim 937/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0684::SPLIT03
Claim: Wistron 是僅有三家具備自動化能力的 Rubin L10 運算托盤組裝合作夥伴之一。
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At L6, board level PCBA, Wistron and Foxconn are the main supplier of Blackwell and Rubin. For L10, Blackwell had lots of different compute tray manufacturers as they buy the Bianca boards from Nvidia to sell to their clients. For Rubin, there are only three suppliers that have the capability to do automation of Rubin compute tray. For smaller ODM or OEM, they either have their compute tray made at the three automation suppliers mentioned above or they will do it in-house without automation.
Although not as efficient, compute tray assembly without automation should be much easier compared to Blackwell as well given the seamless modular design. Then at L11, the various ODMs/OEMs assemble the compute tray into the rack.
Atomic Claim 938/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0685::SPLIT01
Claim: Wistron 是 Blackwell 的主要 L6 板級 PCBA 供應商。
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Atomic Claim 939/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0685::SPLIT02
Claim: Wistron 是 Rubin 的主要 L6 板級 PCBA 供應商。
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Atomic Claim 940/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0685::SPLIT03
Claim: Foxconn is a main L6 board-level PCBA supplier for Blackwell.
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Atomic Claim 941/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0685::SPLIT04
Claim: Foxconn is a main L6 board-level PCBA supplier for Rubin.
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Atomic Claim 942/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0686::SPLIT01
Claim: Blackwell 有許多不同的 L10 運算托盤製造商。
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Atomic Claim 943/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0686::SPLIT02
Claim: Blackwell L10 製造商向 Nvidia 購買 Bianca 板，再出售給其客戶。
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Atomic Claim 944/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0687
Claim: 對 Rubin 而言，只有 3 家供應商具備自動化組裝 Rubin compute tray 的能力。
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Atomic Claim 945/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0688
Claim: 較小型的 ODM 或 OEM，要嘛把 compute tray 交由前述 3 家具備 automation capability 的供應商製造，要嘛自行以非自動化方式組裝。
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Atomic Claim 946/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0689
Claim: SemiAnalysis 預期，受惠於 seamless modular design，Rubin 非自動化 compute-tray assembly 也會比 Blackwell 容易許多。
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Atomic Claim 947/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0690
Claim: 接著在 L11 階段，各 ODM / OEM 會把 compute tray 組裝進 rack。
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VR NVL72 TCO: BoM and Power Budget Analysis
The VR NVL72 Component BoM and Power Budget Model provides a detailed analysis on the BoM and the Power Budget of the rack system.
The VR NVL72 is more expensive on a per-GPU capital cost basis, ~45% higher vs GB300s and ~14-15% higher vs the MI4XX given a higher server cost on a per GPU basis. This results in a higher Capital Cost of Ownership (TCO). For example VR NVL 72 Hyperscaler Arista has a capital cost of 2.86 per hour per GPU over a 4 year useful life.
Our TCO Model runs on a 4y useful life for the purpose of calculating capital cost per hour to reflect a conservative business case, but most Neoclouds and Hyperscalers will use a 5-6y depreciation period and we think it is best to look at EBIT margins using this depreciation period. Our preferred yardstick is Project IRR, which is agnostic to the chosen depreciation period.
Atomic Claim 948/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0692::SPLIT01
Claim: 在來源模型中，VR NVL72 每顆 GPU 的資本成本較 GB300 高約 45%。
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Atomic Claim 949/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0692::SPLIT02
Claim: 在來源模型中，VR NVL72 每顆 GPU 的資本成本較 MI4XX 高約 14–15%。
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Atomic Claim 950/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0692::SPLIT03
Claim: 來源將 VR NVL72 每顆 GPU 較高的資本成本，歸因於每顆 GPU 分攤的伺服器成本較高。
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Atomic Claim 951/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0693
Claim: 因此，VR NVL72 的 Capital Cost of Ownership（TCO）較高。
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Atomic Claim 952/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0694
Claim: 例如，以 4 年 useful life 計算，採用 Arista networking 的 VR NVL72 Hyperscaler 部署，其 capital cost 為每顆 GPU 每小時 3.28 美元；相較之下，MI4XX Hyperscaler 為 2.86 美元。
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Atomic Claim 953/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0696::SPLIT01
Claim: 依來源所述，大多數 neocloud 與 hyperscaler 將採用 5–6 年的折舊年限。
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Atomic Claim 954/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0696::SPLIT02
Claim: SemiAnalysis 建議，以 neocloud 與 hyperscaler 普遍採用的 5–6 年折舊年限評估 EBIT 利潤率。
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Atomic Claim 955/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BOM-BF4
Claim: 可見的 VR NVL72 BOM 數量欄列出，每個機櫃配置 18 個 BlueField-4 模組。
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Atomic Claim 956/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BOM-MID
Claim: 可見的 VR NVL72 BOM 數量欄列出，每個機櫃配置 18 塊 PCB 中板。
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Atomic Claim 957/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BOM-ORCHID
Claim: 可見的 VR NVL72 BOM 數量欄列出，每個機櫃配置 72 塊 Orchid 板。
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Atomic Claim 958/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BOM-STRATA
Claim: 可見的 VR NVL72 BOM 數量欄列出，每個機櫃配置 36 塊 Strata 板。
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However, one advantage for Nvidia’s VR SOCAMM option is that NVIDIA directly procures memory, allowing them to negotiate long-term agreements, volume-preferential terms with memory suppliers and most importantly, VVIP pricing. We think this will shield end customers from spikes in memory costs as we outline in our AI server apocalypse note, and is another example of how, as the Central Bank of AI, Nvidia is effectively hedging DRAM prices for all of its customers.
Atomic Claim 959/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0698::SPLIT01
Claim: Nvidia 直接採購 VR SOCAMM 選項所需的記憶體。
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Atomic Claim 960/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0698::SPLIT02
Claim: 直接採購記憶體，使 Nvidia 能與記憶體供應商協商長期協議。
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Atomic Claim 961/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0698::SPLIT03
Claim: 直接採購記憶體，使 Nvidia 能與記憶體供應商協商大量採購優惠條件。
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Atomic Claim 962/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0698::SPLIT04
Claim: 直接採購記憶體，使 Nvidia 能與記憶體供應商協商 VVIP 價格。
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Atomic Claim 963/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0699
Claim: SemiAnalysis 認為，這種 NVIDIA 直接採購 memory 的模式能降低終端客戶受到 memory cost spikes 衝擊的程度。
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By contrast, AMD is much more exposed to DRAM price increases as it has about double the amount of DRAM, with about 55 TB per rack of LPDDR5 and 55 TB per rack of DDR5.
For AMD’s Helios rack scale system, AMD sells the GPU/board and does procure the LPDDR5 memory, but it does not procure DDR5 DRAM for rack compute trays; rack assemblers/ODMs source and integrate DDR5 memory. This leaves buyers of AMD’s racks more exposed because AMD is only able to potentially “hedge” the LPDDR5 portion via long-term contracts leaving the DDR5 portion completely exposed. Having double the DRAM content also nearly doubles the overall exposure.
Atomic Claim 964/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0701::SPLIT01
Claim: 來源判斷，AMD 更容易受到 DRAM 漲價影響，因為其機櫃的 DRAM 用量約為兩倍。
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Atomic Claim 965/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0701::SPLIT02
Claim: 來源估計，AMD 機櫃的 DRAM 用量約為 Nvidia 替代方案的兩倍。
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Atomic Claim 966/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0701::SPLIT03
Claim: AMD Helios 每個機櫃約有 55TB LPDDR5。
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Atomic Claim 967/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0701::SPLIT04
Claim: AMD Helios 每個機櫃約有 55TB DDR5。
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Atomic Claim 968/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0702::SPLIT01
Claim: AMD 銷售 Helios 機櫃級系統的 GPU／板卡。
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Atomic Claim 969/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0702::SPLIT02
Claim: AMD 採購 Helios 的 LPDDR5 記憶體。
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Atomic Claim 970/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0702::SPLIT03
Claim: AMD 不採購 Helios 機櫃運算托盤的 DDR5 DRAM。
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Atomic Claim 971/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0703
Claim: AMD Helios 機櫃組裝商／ODM 自行採購並整合運算托盤的 DDR5 記憶體。
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Atomic Claim 972/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0704::SPLIT01
Claim: 來源判斷，AMD 機櫃買家更容易受到記憶體漲價影響。
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Atomic Claim 973/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0704::SPLIT02
Claim: AMD 可能只能透過長期合約，對沖 LPDDR5 部分的價格風險。
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Atomic Claim 974/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0704::SPLIT03
Claim: 在所述 AMD 採購模式下，DDR5 部分仍完全暴露於價格變動。
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Atomic Claim 975/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0705
Claim: 在來源比較中，AMD Helios 機櫃約兩倍的 DRAM 用量，使其對記憶體價格變動的曝險接近兩倍。
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Helios memory costs are more likely to be passed through or re-priced by assemblers and therefore exhibit greater hikes in a memory upcycle. Therefore, we model lower memory price hikes for VR and GB compared to MI4XX below. Our MI400 rack assumptions reflect 6.77/GB for Nvidia, embedding volume discount structures vs the market contract price of $10.63/GB but reflecting the slack of volume economics vs NVIDIA.
Atomic Claim 976/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0706
Claim: 在 memory upcycle 中，Helios 的 memory costs 更可能被 assemblers 轉嫁或重新定價，因此價格漲幅可能更大。
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Atomic Claim 977/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0707
Claim: 因此，SemiAnalysis 對 VR 與 GB 所建模的 memory price hikes，低於 MI4XX。
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Atomic Claim 978/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT01
Claim: 來源的 MI400 機櫃假設採用 AMD LPDDR 價格 $8.70/GB。
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Atomic Claim 979/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT02
Claim: 來源比較採用 Nvidia LPDDR 價格 $6.77/GB。
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Atomic Claim 980/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT03
Claim: 來源的 LPDDR 價格比較採用市場合約價 $10.63/GB。
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Atomic Claim 981/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT04
Claim: 模型中的 AMD 與 Nvidia LPDDR 價格，相較市場合約價已包含大量採購折扣。
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Atomic Claim 982/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT05
Claim: 來源將模型中的 AMD 與 Nvidia LPDDR 價差，解讀為反映 Nvidia 較大的採購規模效益。
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Our AI Memory Model expects significant increases in LPDDR5 and DDR5 contract prices into 2Q26 and beyond and we expect to make further revisions higher in total server capex.
Atomic Claim 983/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0709
Claim: SemiAnalysis AI Memory Model 預期 LPDDR5 contract prices 在 2Q26 及之後顯著上升。
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Atomic Claim 984/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0710::SPLIT01
Claim: SemiAnalysis Memory Model 預期，DDR5 合約價將在 2Q26 及之後顯著上漲。
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Atomic Claim 985/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0710::SPLIT02
Claim: SemiAnalysis 預期，隨著記憶體合約價上漲，將上修伺服器總 CapEx。
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NVIDIA’s 2300W configuration represents the Max-P configuration, while the efficiency optimized Max-Q configuration runs at 1800W. Regardless of which configuration Nvidia claims both can hit the same peak clocks and therefore achieve marketed 50 PFLOPS FP4 performance. While the underlying hardware is the same, the TCO implications are due to operating costs from different levels of power consumption.
Atomic Claim 986/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0711
Claim: NVIDIA 的 2300W configuration 是 Max-P，而以效率最佳化的 Max-Q configuration 則運作在 1800W。
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Atomic Claim 987/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0712
Claim: Nvidia 表示，不論採用 Max-P 或 Max-Q configuration，兩者都能達到相同的 peak clocks。
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Atomic Claim 988/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0713
Claim: 因此兩種 configuration 都可達到市場宣稱的 50 PFLOPS FP4 performance。
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Atomic Claim 989/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0714
Claim: 在相同的 Rubin 底層硬體下，Max-P 與 Max-Q 的 TCO 差異來自隨功耗變動的營運成本。
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Below we share detailed numbers on cost of servers, storage, networking, etc as well as what Nvidia plans to do with Groq.
Operating costs are similar for VR Max-P vs MI4XX given their comparable chip TDPs and given that most operating costs scale with respect to IT power requirements.
Atomic Claim 990/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0716
Claim: 由於 chip TDP 相近，而且多數 operating costs 會隨 IT power requirements 變動，因此 VR Max-P 與 MI4XX 的 operating costs 大致相近。
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VR Max-Q on the other hand, exhibits lower Operating costs relative to MI4XX given the lower chip TDP. For example a VR NVL 72 cluster deployed at a Hyperscaler with Arista networking would have a operating cost of $0.75 per gpu per hour, representing ~20% lower costs vs MI4XX deployed with a Hyperscaler with the same Arista networking. This highlights the advantages of the Max-Q configuration, particularly from an operating cost perspective, as the lower power TDP reduces rack-level power density for a meaningful cost savings over time.
Atomic Claim 991/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0717
Claim: 相較之下，VR Max-Q 因 chip TDP 較低，其 operating costs 低於 MI4XX。
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Atomic Claim 992/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0718
Claim: 例如，採用 Arista networking 的 VR NVL72 Hyperscaler cluster，operating cost 約為每顆 GPU 每小時 0.75 美元，比採用相同 Arista networking 的 MI4XX 約低 20%。
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Atomic Claim 993/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0719
Claim: 這凸顯 Max-Q configuration 在 operating cost 上的優勢：較低 TDP 會降低 rack-level power density，長期可帶來顯著成本節省。
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Atomic Claim 994/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-0-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，MI4XX／Arista／neocloud 的資本成本為每邏輯 GPU 小時 US$3.24。
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Atomic Claim 995/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-0-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，MI4XX／Arista／neocloud 的營運成本為每邏輯 GPU 小時 US$1.01。
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Atomic Claim 996/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-0-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，MI4XX／Arista／neocloud 的總 TCO 為每邏輯 GPU 小時 US$4.25。
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Atomic Claim 997/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-1-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，MI4XX／Arista／hyperscaler 的資本成本為每邏輯 GPU 小時 US$2.86。
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Atomic Claim 998/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-1-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，MI4XX／Arista／hyperscaler 的營運成本為每邏輯 GPU 小時 US$0.92。
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Atomic Claim 999/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-1-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，MI4XX／Arista／hyperscaler 的總 TCO 為每邏輯 GPU 小時 US$3.77。
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Atomic Claim 1000/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-2-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Arista／neocloud 的資本成本為每邏輯 GPU 小時 US$3.69。
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Atomic Claim 1001/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-2-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Arista／neocloud 的營運成本為每邏輯 GPU 小時 US$0.97。
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Atomic Claim 1002/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-2-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Arista／neocloud 的總 TCO 為每邏輯 GPU 小時 US$4.66。
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Atomic Claim 1003/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-3-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／neocloud 的資本成本為每邏輯 GPU 小時 US$3.94。
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Atomic Claim 1004/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-3-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／neocloud 的營運成本為每邏輯 GPU 小時 US$0.97。
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Atomic Claim 1005/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-3-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／neocloud 的總 TCO 為每邏輯 GPU 小時 US$4.91。
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Atomic Claim 1006/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-4-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Arista／hyperscaler 的資本成本為每邏輯 GPU 小時 US$3.28。
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Atomic Claim 1007/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-4-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Arista／hyperscaler 的營運成本為每邏輯 GPU 小時 US$0.88。
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Atomic Claim 1008/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-4-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Arista／hyperscaler 的總 TCO 為每邏輯 GPU 小時 US$4.16。
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Atomic Claim 1009/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-5-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／hyperscaler 的資本成本為每邏輯 GPU 小時 US$3.27。
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Atomic Claim 1010/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-5-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／hyperscaler 的營運成本為每邏輯 GPU 小時 US$0.88。
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Atomic Claim 1011/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-5-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-P 2300W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／hyperscaler 的總 TCO 為每邏輯 GPU 小時 US$4.15。
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Atomic Claim 1012/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-0-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，MI4XX／Arista／neocloud 的資本成本為每邏輯 GPU 小時 US$3.24。
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Atomic Claim 1013/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-0-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，MI4XX／Arista／neocloud 的營運成本為每邏輯 GPU 小時 US$1.01。
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Atomic Claim 1014/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-0-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，MI4XX／Arista／neocloud 的總 TCO 為每邏輯 GPU 小時 US$4.25。
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Atomic Claim 1015/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-1-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，MI4XX／Arista／hyperscaler 的資本成本為每邏輯 GPU 小時 US$2.86。
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Atomic Claim 1016/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-1-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，MI4XX／Arista／hyperscaler 的營運成本為每邏輯 GPU 小時 US$0.92。
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Atomic Claim 1017/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-1-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，MI4XX／Arista／hyperscaler 的總 TCO 為每邏輯 GPU 小時 US$3.77。
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Atomic Claim 1018/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-2-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Arista／neocloud 的資本成本為每邏輯 GPU 小時 US$3.69。
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Atomic Claim 1019/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-2-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Arista／neocloud 的營運成本為每邏輯 GPU 小時 US$0.83。
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Atomic Claim 1020/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-2-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Arista／neocloud 的總 TCO 為每邏輯 GPU 小時 US$4.51。
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Atomic Claim 1021/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-3-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／neocloud 的資本成本為每邏輯 GPU 小時 US$3.94。
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Atomic Claim 1022/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-3-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／neocloud 的營運成本為每邏輯 GPU 小時 US$0.83。
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Atomic Claim 1023/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-3-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／neocloud 的總 TCO 為每邏輯 GPU 小時 US$4.77。
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Atomic Claim 1024/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-4-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Arista／hyperscaler 的資本成本為每邏輯 GPU 小時 US$3.28。
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Atomic Claim 1025/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-4-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Arista／hyperscaler 的營運成本為每邏輯 GPU 小時 US$0.75。
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Atomic Claim 1026/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-4-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Arista／hyperscaler 的總 TCO 為每邏輯 GPU 小時 US$4.03。
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Atomic Claim 1027/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-5-CAPITAL_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／hyperscaler 的資本成本為每邏輯 GPU 小時 US$3.27。
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Atomic Claim 1028/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-5-OPERATING_COST
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／hyperscaler 的營運成本為每邏輯 GPU 小時 US$0.75。
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Atomic Claim 1029/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-5-TOTAL_TCO
Claim: 在 2026 年 2 月的 Max-Q 1800W 比較模型（資產年限 4 年）中，VR NVL72／Spectrum／hyperscaler 的總 TCO 為每邏輯 GPU 小時 US$4.02。
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Source: SemiAnalysis AI TCO Model
Source: SemiAnalysis AI TCO Model
The MI4XX currently has a performance per TCO advantage based on marketed dense FLOPS over VR. VR has a higher TCO per GPU compared to MI4XX, yet VR marketed PFLOPs are lower vs MI4XX resulting in a TCO per PFLOP disadvantage for the VR vs MI4XX.
Atomic Claim 1030/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0720
Claim: 以 marketed dense FLOPS 衡量，MI4XX 目前相較 VR 具有 performance-per-TCO 優勢。
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Atomic Claim 1031/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0721
Claim: VR 每顆 GPU 的 TCO 高於 MI4XX，但 marketed PFLOPs 又低於 MI4XX，因此 VR 在 TCO per PFLOP 上處於劣勢。
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NVIDIA is offering sparsity for FP4, marketing 50 PFLOPS of FP4, while AMD has opted to remove sparsity support since CDNA4 for inference dtypes. Harnessing the 50 PFLOPS sparse vs 35 PFLOPS dense drops the cost per perf in units of $/hr per Marketed PFLOP by 35%—a valid comparison if AI Labs can indeed successfully harness Sparse FP4 on the VR NVL72.
Atomic Claim 1032/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0722::SPLIT01
Claim: Nvidia 提供 FP4 稀疏性支援。
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Atomic Claim 1033/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0722::SPLIT02
Claim: Nvidia 宣傳的 sparse FP4 效能為 50 PFLOPS。
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Atomic Claim 1034/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0723
Claim: AMD 自 CDNA4 起，已選擇在 inference dtypes 移除 sparsity support。
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Atomic Claim 1035/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0724
Claim: 若 AI Labs 能在 VR NVL72 上有效利用 Sparse FP4，從 35 PFLOPS dense 提升到 50 PFLOPS sparse，可讓以每小時每 marketed PFLOP 計算的 cost/performance 降低約 35%。
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As always, one caveat is that this comparison is done based on a marketed dense PFLOP basis. Effective dense PFLOP (i.e. the real world chip throughput) can differ based on Model Flops Utilization % (MFU), and in general we have seen NVIDIA chip operate at a higher MFU % vs AMD chips, suggesting that performance per TCO based on effective dense PFLOPs could be better for NVIDIA systems vs AMD—however, MFU is dependent on actual workloads with no one-size-fits-all MFU % that is consistently applicable to either systems.
Atomic Claim 1036/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0726
Claim: Effective dense PFLOP，也就是真實世界 chip throughput，會隨 Model Flops Utilization（MFU）而不同。
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Atomic Claim 1037/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0727::SPLIT01
Claim: SemiAnalysis 通常觀察到，Nvidia 晶片運作時的 MFU 高於 AMD 晶片。
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Atomic Claim 1038/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0727::SPLIT02
Claim: 較高的實測 MFU 顯示，以有效 dense PFLOP 為基準，Nvidia 系統的每單位 TCO 效能可能優於 AMD。
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Atomic Claim 1039/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0727::SPLIT03
Claim: MFU 取決於實際工作負載；沒有單一 MFU 百分比能持續適用於任一系統。
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Indeed, real world use of FP4 Sparsity will probably not reach 50 PFLOPS but it will probably deliver better effective FLOPs than FP4 Dense, but we have yet to evaluate what that real-world performance could be. Running VR NVL72 on 1800W would probably mean lower FP4 Sparse FLOPs than on 2300W.
Atomic Claim 1040/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0728
Claim: 原文預期：在真實世界使用情境下，FP4 Sparsity 的實際 performance 很可能無法達到 50 PFLOPS。
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Atomic Claim 1041/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0729::SPLIT01
Claim: Sparse FP4 很可能提供比 dense FP4 更高的有效 FLOPs。
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Atomic Claim 1042/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0729::SPLIT02
Claim: SemiAnalysis 尚未評估 sparse FP4 可達到的實際效能。
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Atomic Claim 1043/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0730
Claim: 在原文所述假設情境中，VR NVL72 若以 1800W 運作，其 FP4 Sparse FLOPs 很可能低於 2300W configuration。
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Source: SemiAnalysis AI TCO Model
Source: SemiAnalysis AI TCO Model
Inference throughput too can diverge materially from marketed peak FLOPS, meaning spec-sheet compute does not directly translate into real-world token generation performance. While the B300 is rated at 4,500 Dense FP8 TFLOPs versus 5,000 Dense FP8 TFLOPs for MI355, implying a 10% theoretical compute disadvantage and with same marketed memory bandwidth of 8TB/s measured inference token throughput from our InferenceX benchmarks shows B300 delivering roughly 6.3x the performance at 100 interactivity for Deepseek R1, using 8k input tokens and 1k output tokens.
Atomic Claim 1044/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0772
Claim: B300 額定為 4,500 dense FP8 TFLOPs。
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Atomic Claim 1045/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0773
Claim: MI355 額定為 5,000 dense FP8 TFLOPs。
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Atomic Claim 1046/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0731
Claim: inference throughput 也可能和 marketed peak FLOPS 有顯著差異，因此規格表上的 compute performance 並不會直接轉化成真實世界的 token generation performance。
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Atomic Claim 1047/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0732::SPLIT03
Claim: B300 的額定 dense FP8 運算效能比 MI355 低 10%。
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Atomic Claim 1048/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0732::SPLIT04
Claim: B300 宣傳的記憶體頻寬為 8TB/s。
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Atomic Claim 1049/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0732::SPLIT05
Claim: MI355 宣傳的記憶體頻寬為 8TB/s。
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Atomic Claim 1050/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0732::SPLIT06
Claim: 在 Deepseek R1、8k 輸入 token、1k 輸出 token 與 interactivity 100 的條件下，SemiAnalysis InferenceX 測得 B300 的 token 吞吐量約為 MI355 的 6.3 倍。
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Given that total cost of ownership is only 1.75x higher, this results in a superior performance-per-TCO profile for B300 despite the more modest marketed figures. Such a wildly different result despite very similar specs underscores that real world performance is not dictated by peak FLOPS or memory bandwidth alone. Software and network capabilities are also major factors that contribute to training and token throughput in real workloads.
Atomic Claim 1051/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0733
Claim: 由於 total cost of ownership 只高約 1.75 倍，B300 即使 marketed figures 較保守，仍呈現更優的 performance-per-TCO profile。
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Atomic Claim 1052/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0734
Claim: B300／MI355 的 InferenceX 比較顯示，僅靠峰值 FLOPs 與記憶體頻寬，無法決定實際效能。
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Atomic Claim 1053/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0735::SPLIT01
Claim: 來源指出，除了峰值 FLOPs 與記憶體頻寬之外，軟體能力也是實際工作負載訓練效能與 token 吞吐量的重要影響因素。
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Atomic Claim 1054/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0735::SPLIT02
Claim: 來源指出，除了峰值 FLOPs 與記憶體頻寬之外，網路能力也是實際工作負載訓練效能與 token 吞吐量的重要影響因素。
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Rubin and MI4XX will ship with new microarchitectures, real world performance is especially difficult to predict without benchmarking like we do with InferenceX.
Atomic Claim 1055/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0736::SPLIT01
Claim: Rubin 將搭載新的微架構出貨。
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Atomic Claim 1056/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0736::SPLIT02
Claim: MI4XX 將搭載新的微架構出貨。
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Atomic Claim 1057/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0736::SPLIT03
Claim: Rubin 與 MI4XX 的新微架構，使得缺乏 InferenceX 等基準測試時，實際效能尤其難以預測。
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Notably, both operating modes share identical memory bandwidth specifications at 8TB/s. Yet, despite the parity in memory bandwidth inference performance still diverges materially.
Atomic Claim 1058/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0737
Claim: 2 月文章指出「兩種操作模式」都有 8TB/s 記憶體頻寬，但未釐清其指涉對象；前一段比較的是 B300 與 MI355。
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Atomic Claim 1059/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0738
Claim: 文章表示，即使記憶體頻寬相同，推論效能仍可能不同；其中「操作模式」的指涉對象仍不明確。
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Source: SemiAnalysis InferenceX
Groq LPU Decode Rack
Since Nvidia entered into a licensing agreement for Groq’s technology and hired Groq’s key people in December 2025, speculation has brewed on how exactly Nvidia will implement Groq’s technology. We believe that Nvidia will introduce a new LPU rack at GTC 2026. The LPU rack is designed to be used alongside Nvidia GPUs for inference.
Atomic Claim 1060/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0739::SPLIT01
Claim: Nvidia 在 2025 年 12 月簽訂 Groq 技術授權協議。
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Atomic Claim 1061/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0739::SPLIT02
Claim: Nvidia 在 2025 年 12 月聘用了 Groq 的關鍵人員。
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Atomic Claim 1062/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0739::SPLIT03
Claim: 隨後市場開始猜測 Nvidia 將如何實作 Groq 技術。
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Atomic Claim 1063/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0740
Claim: SemiAnalysis 預期 Nvidia 將在 GTC 2026 推出新的 LPU rack。
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Atomic Claim 1064/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0741
Claim: LPU rack 的設計目標，是在 inference workload 中與 Nvidia GPUs 搭配使用。
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With CPX being designed specifically for inference pre-fill, the LPU system is designed for inference decode given the LPU’s emphasis on higher bandwidth SRAM. This comes at the expense of total throughput so this LPU decode system could be positioned at serving requests that require very high tokens per second per user, with the user paying much higher $/token to compensate for higher cost to serve.
Atomic Claim 1065/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0742::SPLIT01
Claim: CPX 專為推論 prefill 設計。
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Atomic Claim 1066/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0742::SPLIT02
Claim: LPU 系統因著重更高頻寬的 SRAM，而針對推論 decode 設計。
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Atomic Claim 1067/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0743
Claim: 這會犧牲 total throughput，因此該 LPU decode system 可能定位於服務需要極高 tokens per second per user 的 requests。
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Atomic Claim 1068/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0744
Claim: 若 LPU decode system 定位於極高 tokens-per-second-per-user 的服務，使用者可能支付更高 $/token，以補償較高 serving cost。
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It will be designed to sit alongside Nvidia GPUs that handle decode for lower interactivity requests. We have shared more details of the system specification to Accelerator Model clients, where we highlight one part of the supply chain that could be a big beneficiary.
Atomic Claim 1069/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0745::SPLIT01
Claim: 提出的 LPU 系統將與 Nvidia GPU 並用。
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Atomic Claim 1070/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0745::SPLIT02
Some details we will share here is that there are 256 LPUs per rack and it is the 3rd generation Groq chip on Samsung 4nm (the 2nd generation is being skipped). We share an important supply chain detail that has an impact on growth and market share as well as topology in the Accelerator Model note.
Atomic Claim 1071/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0747
Claim: 2026 年 2 月文章提出的 LPU 機櫃，每個系統配置 256 顆 LPU。
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Atomic Claim 1072/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0748::SPLIT01
Claim: 提出的 LPU 機櫃使用第三代 Groq 晶片。
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Atomic Claim 1073/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0748::SPLIT02
Claim: 提出的第三代 Groq 晶片採用 Samsung 4nm。
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Atomic Claim 1074/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0748::SPLIT03
Claim: 第二代 Groq 晶片將被跳過。
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