SA Article Coverage Review · 2026-02-25_vera-rubin-extreme-co-design-an-evolution
Coverage Summary
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Coverage Review
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Vera Rubin – Extreme Co-Design: An Evolution from Grace Blackwell Oberon
At CES 2026, Nvidia officially announced in detail all 6 Rubin platform products: the Rubin GPU, Vera CPU, NVLink 6 Switch, ConnectX-9, BlueField-4, and Spectrum-6. VR NVL72 is the second generation of Nvidia’s rack scale Oberon architecture that takes the stage. With competition catching up on rack scale game, Trainium 3 in the Gen2 UltraServer, AMD MI450X Helios Racks, and Google’s TPU which was at rack scale even before GB200 ↗, Nvidia answers with “extreme co-design” supremacy. With extreme co-design, Nvidia takes rack scale integration to the next level. Rack system becomes a unit of compute, a single distributed accelerator, and Nvidia designs the system.
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Claim: Nvidia 發布 BlueField-4。
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開啟逐條審核
Atomic Claim 4/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0004
Claim: Nvidia 發布 ConnectX-9。
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開啟逐條審核
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Claim: Nvidia 發布 Spectrum-6。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
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Atomic Claim 8/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0007
Atomic Claim 9/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0008
Claim: Rack-scale 競爭持續升溫，包含 Gen2 UltraServer 中的 Trainium 3，以及 AMD MI450X Helios Racks。
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開啟逐條審核
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Source: Nvidia
For the Vera Rubin platform, Nvidia is asserting even more control over the system and rack level design. Rack scale integration and assembly have become more challenging, as every component is being pushed to the limit, whilst also optimizing for cost efficiency. VR NVL72 has a much more holistic design with a modular approach compared to Grace Blackwell for the purpose of integration efficiency and throughput.
Atomic Claim 13/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0013
Claim: 在 Vera Rubin 平台中，Nvidia 對 system 與 rack-level design 掌握更多控制權。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 14/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0014
Atomic Claim 15/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0015
Nvidia’s competitiveness strengthens with its extreme co-design supremacy. It is the only player with the best in class or close to the best in class silicon product offerings for all the major silicon contents in an Nvidia trail-blazed AI server system design. Nvidia offers the best accelerator, a SOTA scale up switch, the best NIC, and one of the best Ethernet networking switch, and a much improved purpose-designed CPU ↗. No other competitors have such a complete suite of integrated silicon products.
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Atomic Claim 19/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0019
In the sections below, we will discuss the 6 silicon products of the Vera Rubin platform at the silicon level. Then, we will discuss the rack and compute tray evolution from Grace Blackwell to Vera Rubin from the design perspective and the implication to components: cables, connectors, PCB, thermal, mechanical, and power.
Next, we will discuss the major networks of the VR NVL72 system, namely the scale up NVLink 6 network and the backend scale out network. We will discuss the logistical implications of much more limited hyperscaler customisation and the assembly supplier landscape.
Lastly, the report ends with a discussion on the TCO of the VR NVL72 system as well as the BoM and Power Budget estimate supporting the TCO analysis. Behind the paywall, we also provide readers with insight into Nvidia’s plans for their Groq IP. We will also cover some of the challenges with regards to HBM ramp for Micron, SK Hynix, and Samsung.
Atomic Claim 20/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0020
Today we are also launching the VR NVL72 Component BoM and Power Budget Model ↗. It provides a system-level bill of materials and power budget analysis for the VR NVL72 system covered in this article. This is important because various vendors and their shares of the subcomponents will drive whether they are winners or losers in the $500B Rubin buildout. The downstream impacts and dislocations in the market are large. The model covers:
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Atomic Claim 23/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0023
**Nvidia Compute Tray Content: **Strata module with Rubin GPU, Vera CPU, SOCAMM memory; BlueField-4; ConnectX-9
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Atomic Claim 25/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0025
Claim: Compute Tray content 包含 BlueField-4。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 26/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0026
Claim: Compute Tray content 包含 ConnectX-9。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
**NVLink System: **NVSwitch, NVLink backplane and cabling, associated connectors, host CPU management module
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Liquid Cooling Content: Coldplates, QDs, Manifolds
Atomic Claim 31/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0031
Claim: Liquid Cooling content 包含 Coldplates、QDs 與 Manifolds。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
**PCB, Substrate, and Materials Content: **key system boards, ABF substrates, CCL content
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Connectors: Paladin HD2 Board to Board Connectors, Paladin HD2 NVLink 6.0 Connectors
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Power Delivery Content: power shelves, busbars, VRMs, power delivery modules
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Mechanical Structure: chassis, loading mechanism, railkits, rack chassis
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Management modules: BMC
Atomic Claim 44/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0044
Networking: Transceivers, CX-9
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Please visit this self service portal ↗ to purchase the model. Contact sales@semianalysis.com for any questions regarding the product.
Extreme Co-design: 6 Silicon Product Offerings under the Rubin Platform - Chip Floorplans & Specifications
Source: SemiAnalysis, Nvidia
Rubin’s dense FP4 and FP8 FLOPs increase by roughly ~3.5× versus GB200, while FP16 FLOPs rise by a more modest ~1.6x, underscoring NVIDIA’s continued emphasis on FP4/FP8 as the primary scaling vector. On the memory side, HBM capacity remains flat from GB300, while HBM bandwidth scales more aggressively at ~2.8x. Overall, the architecture prioritizes bandwidth and low-precision compute.
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Source: SemiAnalysis, Nvidia
Rubin
Source: Nvidia
Rubin’s design is a logical evolution from Blackwell, with the move to a 3nm process and disaggregating I/O into chiplets while keeping the same basic structure of 2 reticle-sized dies with 8 stacks of HBM. 35 PFLOPS dense FP4 is a 3.5x improvement over Blackwell GB200, achieved by:
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Increasing SM count from 160 to 224
Atomic Claim 55/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0056
Doubling Tensor Core width in the SM to 32768 FP4 MACs/clock
Atomic Claim 56/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0057
Claim: SM 內的 Tensor Core width 加倍至每 clock 32,768 個 FP4 MACs。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Increasing clock speed 25% from 1.90GHz to 2.38GHz
Atomic Claim 57/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0058
Additionally, Nvidia claims up to an effective 50 PFLOPS of FP4 performance can be achieved with an updated 3rd generation Transformer Engine that replaces 2:4 structured sparsity from prior generations. We will detail this architectural feature for Rubin below.
Atomic Claim 58/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0059
Claim: 此外，Nvidia 宣稱，更新後的第三代 Transformer Engine 取代過去世代的 2:4 structured sparsity 後，可達最高有效 50 PFLOPS 的 FP4 效能。
Frame:NARY_RELATION· Mode:ATTRIBUTED· Mapping:PARTIAL
開啟逐條審核
Notably, the Tensor core width doubling only applies to FP4 and FP8, with BF16 and TF32 remaining the same as Blackwell, resulting in performance scaling only 1.6x of Blackwell. This architectural decision reflects NVIDIA’s belief that most training and inference workloads will move away from TF32 and BF16 and onto FP8 and FP4.
Atomic Claim 59/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0060
Claim: Rubin 的 Tensor Core width 加倍僅適用於 FP4 與 FP8。
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開啟逐條審核
Atomic Claim 60/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0061
Claim: Rubin 的 BF16 與 TF32 Tensor Core width 與 Blackwell 相同。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
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Atomic Claim 62/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0063
On the memory front, the move to HBM4 means double the bus width per stack, running at 10.8 GT/s for 22TB/s total bandwidth or 2.75x Blackwell at the same 288GB capacity as GB300. Memory bandwidth has been upgraded significantly from the original 13TB/s advertised at GTC 2025. In order to catch up to AMD MI450’s memory bandwidth, Nvidia requested much higher HBM4 pin speeds from the DRAM suppliers - well above the speeds that was in the JEDEC specification for HBM4.
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While Nvidia is targeting 22TB/s, we understand that memory suppliers are having challenges hitting Nvidia’s requirements and we see it likely that initial shipments will come in slightly below at closer to 20TB/s. We have discussed the implications to SK Hynix, Samsung, and Micron extensively for Accelerator and HBM model subscribers. ↗ Micron is well behind Samsung and Hynix and we believe they are effectively out of the picture for Rubin HBM4. ↗ We have more details on qualifications and pin speeds in the Accelerator and HBM model ↗
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Claim: 文章另有更多 qualification 細節。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:CLAIM_ONLY
開啟逐條審核
Atomic Claim 76/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0078
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Claim: Accelerator model 中另有 pin speed 資訊。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:CLAIM_ONLY
開啟逐條審核
The NVLink-C2C chiplet houses the SerDes for the Vera CPU connection, doubled in bandwidth to 1.8TB/s, while the larger NVLink 6 chiplet on the other end of the chip features 36 custom ‘400G’ SerDes links for 2x NVLink bandwidth to all 72 Rubin GPUs.
Atomic Claim 78/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0079
Claim: NVLink-C2C chiplet 內含連接 Vera CPU 的 SerDes，其 bandwidth 加倍至 1.8TB/s。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
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Transistor count has climbed 60% to 336 billion.
Atomic Claim 80/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0081
Claim: Transistor 數量增加 60% 至 3,360 億顆。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
A notable omission from Rubin is the mention of Sparse FLOPs. In previous generations, 2:4 structured sparsity was used to double marketing FLOPs numbers. However, adoption was minimal especially at low precisions due to accuracy losses from the rigid sparsity structure forcing half of the values to be zero. Programmers basically ignored structured sparsity as it was not useful, which caused hardware designs to change as well. Blackwell Ultra GB300 added 50% more dense FP4 while keeping sparse FP4 FLOPs the same, while AMD’s MI355X stopped supporting structured sparsity on MXFP8, MXFP6 and MXFP4 formats to save silicon area.
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Claim: 過去世代使用 2:4 structured sparsity，可讓行銷宣稱的 FLOPs 數字加倍。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
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Rubin’s adaptive compression engine in the improved Transformer Engine is a key feature to re-boost naturally sparser inference performance by doing dynamic computation of sparsity in-flight and eliminating zeros in the data stream without zeroing out non-zero values, thus maintaining model accuracy while still boosting performance. This is done automatically on existing models built for Blackwell without the need for a new programming model or specific optimizations. While models that utilize Post Training Quantization or Quantization Aware Training will be tuned to maximize adaptive compression speedups, they are not strictly needed to take advantage of dynamic compression.
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Claim: Rubin 改良版 Transformer Engine 中的 adaptive compression engine，可在運行中動態計算 sparsity 並移除 data stream 中的零值，而不把非零值強制歸零，因此能在維持模型 accuracy 的同時提升自然稀疏 inference workload 的效能。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
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Atomic Claim 91/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0092
Claim: 採用 Post Training Quantization 或 Quantization Aware Training 的模型，可以針對 adaptive compression 調校以最大化 speedup，但使用 dynamic compression 並不強制需要這些技術。
Frame:RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
This means the sparser the workload, the closer the performance will be to the 50 PFLOPS marketed peak performance. NVIDIA thus brands the 50 PFLOPS figure as FP4 Inference while the 35 PFLOPS FP4 Training number is for dense workloads. As accuracy is preserved, this allows the marketing team to claim 5x FLOPs for Rubin over GB200, comparing 50 PFLOPS dynamically compressed FP4 to 10 PFLOPS dense FP4. Whether actual GEMM performance reaches 50 PFLOPS depends on how many zeros are in the tensor. The more zeros, the closer it can reach. The less zeros in the tensor, the lower the speedup. Overall, we expect to see much greater traction for Rubin’s adaptive sparsity compression as opposed to structured sparsity thanks to the automatic implementation.
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Atomic Claim 93/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0094
Claim: 因此，NVIDIA 將 50 PFLOPS 數字標示為 FP4 Inference，而 35 PFLOPS FP4 Training 則對應 dense workloads。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
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With that said, many ML Systems engineer are still skeptical that this new form of sparsity will work well, and it is very possible that Nvidia’s 50 PFLOPS is purely marketing like prior generations
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Rubin’s chip level TDP increases up to 2,300W vs 1000-1400W for Blackwell. Supply chain rumors have indicated that there are 2 different “SKUs” with different power and performance profiles: a Max-P variant at 2,300W and a Max-Q variant at 1,800W. However, these are not distinct hardware SKUs but the 2 default power profiles that Nvidia is offering users based on their workload needs. Max-Q is what Nvidia believes offers the best performance per Watt. Max-P offers the greatest absolute performance though this would come with an efficiency penalty. Running the Max-P setting results in a 20% increase in rack power draw but the performance gain fall well short of this 20% power consumption increase.
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These power profiles are software managed. Users can also choose whatever max power draw they prefer (as long as it is no more than 2,300W per GPU) and this has been the case for previous GPU generations as well. Several hyperscalers and labs have chosen to run their GPUs at lower power to optimize for performance per Watt as well as taking into account power availability constraints.
Atomic Claim 107/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0108
Atomic Claim 108/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0109
Atomic Claim 109/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0110
Claim: 部分 hyperscalers 與 labs 選擇讓其 GPUs 以較低功耗運行，以最佳化 performance per Watt 並考量可用電力限制。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
For the mechanical structure of the Rubin package, upgrades have also been made with the addition of an upgraded heat spreader and a stiffener. This compares to Blackwell B200 and B300 packages that only have a heat spreader lid. The heat spreader lid allows more equal distribution of heat exiting the package. It also provides mechanical support for the package to prevent warpage.
Atomic Claim 110/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0111
Atomic Claim 111/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0112
Atomic Claim 112/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0113
Atomic Claim 113/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0114
For Rubin, the heat spreader lid is a module made up of two separate lids. Beside the heat spreader lid, a stiffener is added to the package structure to provide even more mechanical support to avoid warpage. At the surface of the heat spreader lid, there will also be a layer of electroplated gold. The reason for this is to prevent corrosion from liquid metal TIM2, which is between the heat spreader lid and the cold plate.
Atomic Claim 114/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0115
Atomic Claim 115/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0116
Atomic Claim 116/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0117
Atomic Claim 117/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0118
Claim: 此設計是為避免位於 heat spreader lid 與 cold plate 之間的 liquid metal TIM2 造成腐蝕。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Vera
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
NVIDIA was aggressive on the CPU front ↗, with Vera doubling performance over Grace by moving to a 3nm reticle-sized compute die and disaggregating the memory controllers and I/O into chiplets. Core count increases from 72 to 88, with 91 cores printed on die to leave redundancy for yield improvement. These cores mark the return of NVIDIA’s custom ARM CPU designs, with the ‘Olympus’ core now supporting SMT multi-threading for a total of 176 processing threads. L3 cache also received a 40% capacity bump to 162MB. Memory bus width doubled to 1024-bit and speed increased to 9600MT/s for 2.5x bandwidth, while maximum capacity tripled to 1.5TB with 8 SOCAMM modules. The NVLink-C2C to the Rubin GPUs also doubled in bandwidth to 1.8TB/s. PCIe6 and CXL3.1 are now supported as well. All this results in transistor count increasing 2.2x to 227 billion.
Atomic Claim 118/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0120
Atomic Claim 119/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0121
Atomic Claim 120/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0122
Atomic Claim 121/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0123
Atomic Claim 122/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0124
Claim: 連接 Rubin GPUs 的 NVLink-C2C bandwidth 也加倍至 1.8TB/s。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 123/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0125
Atomic Claim 124/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0126
Claim: 上述改動使 transistor count 增加 2.2 倍至 2,270 億顆。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
NVLink 6 Switch
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
While the rack-level switching bandwidth has doubled, the number of NVLink Switch chips per rack has also doubled to 36, with each switch tray now housing 4 Switch chips. This means the new NVLink 6 Switch chip has the same 28.8T bandwidth as NVLink5 Switch, with half the number of ports but running at double the rate using ‘400G’ bi-directional SerDes. This allows the high bandwidth switch design to remain as a single monolithic die, saving on design complexity. The layout remains the same as NVIDIA’s previous switches, with 2 sides for IO and a central logic section crossbar and 3.6 TFlop SHARP in-network compute acceleration.
Atomic Claim 125/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0127
Atomic Claim 126/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0128
Atomic Claim 127/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0129
Atomic Claim 128/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0130
Atomic Claim 129/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0131
ConnectX-9
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
The ConnectX-9 is largely iterative from ConnectX-8, with the same 800G networking bandwidth and 48-lane PCIe6 switch capability. However, CX-9 now supports 800G Ethernet with 4x200G PAM4 SerDes, compared to CX-8 that only supported it on InfiniBand. For the Rubin platform, NVIDIA is doubling the number of NICs per GPU to achieve 2x scale-out bandwidth.
Atomic Claim 130/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0132
Claim: ConnectX-9 大致是 ConnectX-8 的迭代版，維持相同的 800G networking bandwidth 與 48-lane PCIe6 switch capability。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 131/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0133
Atomic Claim 132/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0134
BlueField-4
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
BlueField-4’s design departs significantly from BlueField-3. Instead of doing a bespoke tapeout with compute and networking, NVIDIA simply reuses their large Grace CPU die, co-packaged with a ConnectX-9 die to make an 800G DPU with massive compute capabilities. 128GB of LPDDR5 feeds the Grace CPU at half the bandwidth of regular Grace. That is 4x the memory capacity of BlueField-3. BlueField-4 can also function as a storage controller, with four BF-4 chips in each Context Memory Storage system.
Atomic Claim 133/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0135
Claim: BlueField-4 的設計與 BlueField-3 有顯著差異。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 134/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0136
Atomic Claim 135/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0137
Atomic Claim 136/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0138
Claim: 此 memory capacity 是 BlueField-3 的 4 倍。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 137/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0139
Claim: BlueField-4 也可作為 storage controller，每個 Context Memory Storage system 配置 4 顆 BF-4。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Spectrum-6
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
While not part of the Rubin NVL72 rack, Spectrum-6 CPO enables even larger scale-out clusters with its doubled radix. The design retains the same features as Spectrum-5, with 8 IO chiplets surrounding the main switch die. 102.4T switching bandwidth is achieved with 512x 200G SerDes. 32 3.2T optical engines on the package convert these electrical signals to optical links, each with a detachable fiber connector. The SN6810 features one of these chips, while the SN6800 houses four, multiplexed together to create a 409.6T switch box. There will also be a non-CPO version with pluggable OSFP cages in the SN6600. The non-CPO version will be more common in our view.
Atomic Claim 138/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0140
Claim: 雖然不屬於 Rubin NVL72 rack，Spectrum-6 CPO 透過加倍 radix，可支援更大型的 scale-out cluster。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 139/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0141
Atomic Claim 140/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0142
Atomic Claim 141/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0143
Claim: Package 上的 32 個 3.2T optical engines 會把這些 electrical signals 轉為 optical links，每個 optical engine 都配有可拆式 fiber connector。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 142/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0144
Atomic Claim 143/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0145
Atomic Claim 144/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0146
Atomic Claim 145/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0147
Rubin Oberon Rack: NVL72 not NVL144 nor NVL36
Since the announcement of GB200 at Nvidia GTC 2024, the concept of an AI server system has shifted from a chassis to a rack scale system. In our GB200 article ↗, we discussed the evolution of Nvidia AI server form factor from HGX (8 GPU per node) to Oberon (NVL72 rack scale). While the HGX form factor still exists, the majority of Nvidia’s Blackwell GPUs are integrated in the Oberon form factor. Rubin will also be offered in both HGX and Oberon systems.
Atomic Claim 146/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0148
Atomic Claim 147/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0149
Atomic Claim 148/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0150
Atomic Claim 149/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0151
The key difference between the Blackwell and Rubin Oberon architecture is the number of SKUs offered to customers. As Blackwell Oberon was the first ever mass deployment of a rack scale solution with rack power density over 100KW for the GB200 NVL72 SKU, many datacenters did not have the infrastructure ready to support 100kw+ per rack. Nvidia offered two SKUs of Blackwell Oberon: GB200 NVL72 and GB200 NVL36x2. The latter being a lower density SKU offered for customers who did not have the infra ready to handle the thermals of a single high density rack. We discussed the difference between the two form factors in the GB200 article ↗. ↗
Atomic Claim 150/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0152
Atomic Claim 151/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0156
Atomic Claim 152/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0153
Claim: Blackwell Oberon 是首個大規模部署、rack power density 超過 100KW 的 rack-scale solution；GB200 NVL72 發布時，許多 datacenters 尚未準備好支援每 rack 100kW 以上的基礎設施。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 153/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0154
Unlike Blackwell, Rubin is only offered in the VR NVL72 SKU. The set up is very similar to that of GB200/GB300 NVL72. Each VR NVL72 system consists of:
Atomic Claim 154/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0157
Atomic Claim 155/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0158
Claim: 其系統配置與 GB200／GB300 NVL72 非常相近。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 156/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0159
Atomic Claim 157/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0160
36 Vera CPUs
Atomic Claim 158/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0161
36 NVLink 6 Switch ASICs
Atomic Claim 159/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0162
Claim: 每套系統包含 36 顆 NVLink 6 Switch ASICs。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
On a side note, VR NVL72 was initially known as VR NVL144 as Jensen math ↗ from GTC 2025 defined the number of GPU as the number of GPU compute die in system (with 2 compute dies per package and 72 Rubin packages per Oberon rack = 144 compute die). The naming was changed back to VR NVL72 to represent the 72 Rubin GPU packages in the system in late December. This was right before CES 2026 where the naming was officially confirmed as VR NVL72.
Atomic Claim 160/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0163
Atomic Claim 161/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0164
Atomic Claim 162/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0165
CPX Form Factor
Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
Although Nvidia initially planned to integrate the CPX accelerator into the VR NVL72 rack, the current development suggests that CPX will only be offered as a standalone rack as we detailed in our article introducing Nvidia ↗CPX ↗. To recap Rubin-era system planning in our previous CPX article, Nvidia initially contemplated three VR NVL72 configurations:
Atomic Claim 163/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0166
Atomic Claim 164/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0166::SPLIT02
Atomic Claim 165/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0167
VR NVL72 (Regular): Standard Oberon VR NVL72 without CPX
Atomic Claim 166/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0168
VR NVL72 CPX (Integrated): Rubin GPU and Rubin CPX within the same compute tray
Atomic Claim 167/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0169
VR NVL72 CPX (Dual Rack): Rubin CPX deployed in a separate rack alongside the VR NVL72 rack
Atomic Claim 168/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0170
The standalone/dedicated rack direction materially changes the deployment calculus. A dual-rack approach allows hyperscalers to scale prefill and decode capacity independently, optimize datacenter power envelopes, and reduce system-level failure domains versus tightly coupled trays. More importantly, it formalizes architectural disaggregation between inference prefill (compute-bound) and decode (bandwidth-bound).
Atomic Claim 169/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0172
Claim: Dual-rack 架構讓 hyperscalers 可以獨立擴充 prefill 與 decode capacity、最佳化 datacenter power envelope，並相較 tightly coupled trays 降低 system-level failure domains。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 170/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0173
Rubin CPX was originally architected as a GDDR7-based accelerator optimized for prefill, based on three key considerations:
Atomic Claim 171/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0174
Prefill is primarily FLOPs-limited, not bandwidth-limited, making HBM less indispensable.
Atomic Claim 172/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0175
HBM’s increased bandwidth is structurally underutilized in prefill.
Atomic Claim 173/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0176
GDDR7 offers materially lower cost per GB and avoids the need for 2.5D packaging,
Atomic Claim 174/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0177
However, Nvidia began exploring HBM-equipped variants for prefill, either via modified CPX configurations or through lower memory spec (such as using HBM3E) Rubin deployments dedicated to prefill, which we noted ↗ this way back in early December last year ↗ in our Accelerator & HBM model ↗.
Atomic Claim 175/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0178
We also think a lot this shift is driven by evolving memory economics. **Conventional DRAM pricing has risen sharply: **As DDR pricing increases, the relative premium of HBM compresses because pricing is more locked down in long term contracts, narrowing the cost gap between a GDDR-based CPX and lower-spec HBM configurations, therefore eliminating a lot of the cost benefits GDDR offers relative to performance. While memory bandwidth is not as important for pre-fill compare to decode, it is still necessary.
Atomic Claim 176/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0180
Atomic Claim 177/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0181
Atomic Claim 178/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0182
Atomic Claim 179/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0183
Atomic Claim 180/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0184
Atomic Claim 181/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0185
Compute Tray Redesign
One of the major changes with VR NVL72 is within the compute tray. This redesign of the compute tray is centered around simplifying assembly, namely eliminating cables from the compute tray as cables have been the major point of failure of GB200/300 assembly. As Jensen put it at CES 2026, the cableless design reduces the compute tray assembly time from 2 hours to 5 minutes. To achieve this, the VR NVL72 compute tray adopts a modular design with the modules connecting to each via board-to-board connectors.
Atomic Claim 182/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0186
Claim: VR NVL72 的一項主要變化發生在 compute tray。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 183/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0187
Claim: compute tray redesign 的核心是簡化 assembly，尤其是移除 compute tray 內的 cables，因 cables 一直是 GB200/300 assembly 的主要故障點。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 184/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0188
Claim: Jensen 在 CES 2026 表示，cableless design 可把 compute tray assembly time 從 2 小時縮短至 5 分鐘。
Frame:ATTRIBUTE· Mode:ATTRIBUTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 185/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0189
Claim: 為達成此目標，VR NVL72 compute tray 採 modular design，各 modules 之間以 board-to-board connectors 連接。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
To understand the compute tray of VR NVL72 we must first understand the 6 modules that make up the VR NVL72 compute tray:
Atomic Claim 186/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0190
Claim: 要理解 VR NVL72 的 compute tray，需要先掌握構成該 VR NVL72 compute tray 的 6 個 modules。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Strata Module x 2
Orchid Module x4
Compute Tray Midplane x 1
Atomic Claim 187/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0191
Claim: 其中包含 1 個 Compute Tray Midplane。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Power Delivery Module x 1
Atomic Claim 188/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0192
Claim: 關於 compute tray：其中包含 1 個 Power Delivery Module。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
BlueField-4 Module x 1
Atomic Claim 189/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0193
Claim: 其中包含 1 個 BlueField-4 Module。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
System Management Module x 1
Atomic Claim 190/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0194
Claim: 關於 compute tray：其中包含 1 個 System Management Module。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
We break down these components costs and all the subcomponent costs in the Nvidia VR NVL72 BoM and Power Budget Model ↗.
Atomic Claim 191/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0195
Strata
Strata Module, Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
Atomic Claim 192/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0196
Bianca Module. Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
Situated at the back of the chassis, the Strata module of VR NVL72 is the equivalent of the Bianca board of GB200/300. It houses two Rubin GPUs and one Vera CPU. Unlike Bianca, the LPDDR5X memory for Vera is socketed via SOCAMM module. 8 SOCAMM sockets are placed on the left and right of Vera. Two SOCAMM modules of different capacities are offered, 192GByte and 128GByte, for a maximum of 1,534GByte and a minimum of 1,024GByte per Vera. The Connect-X NICs mezzanine module is also taken off the Strata module as CX-9 is moved to the front of the chassis. Under the cableless design, all the cable connector ports are also removed and replaced by Paladin HD2 board-to-board connectors at the bottom of the module. On the other side, the same set of Paladin HD2 backplane connectors as GB200 and GB300 are identically placed at the back of the module connecting to the NVLink 6 Switches via the NVLink backplane.
Atomic Claim 193/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0197
Claim: VR NVL72 的 Strata module 位於 chassis 後方，相當於 GB200/300 的 Bianca board。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 194/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0198
Atomic Claim 195/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0202
Claim: 關於 Strata board：Connect-X NICs mezzanine module 也從 Strata module 移除，因為 CX-9 被移到 chassis 前方。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 196/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0203
Claim: 在 cableless design 下，所有 cable connector ports 都被移除，改由 module 底部的 Paladin HD2 board-to-board connectors 取代。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 197/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0204
Orchid
Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
The Orchid Module houses two ConnectX-9 NICs, two 800G transceiver cages, and one E1.S module slot. Four Orchid modules sit at the front of the chassis. With two Orchid modules stacked on top of each other, they occupy the front left and front right chassis space. At the end of the module there is one Paladin HD2 board-to-board connector that mates with the connector on the midplane. The Orchid module is slim and long, allowing the PCIe 6 signal to travel from the midplane to the CX-9 NICs at the front of the chassis.
Atomic Claim 198/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0205
Claim: Orchid Module 內含 2 顆 ConnectX-9 NICs、2 個 800G transceiver cages，以及 1 個 E1.S module slot。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 199/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0206
Claim: 關於 Orchid board：Chassis 前方共配置 4 個 Orchid modules。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 200/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0207
Claim: 關於 Orchid board：兩個 Orchid modules 上下堆疊，分別占據 chassis 前方左側與右側空間。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 201/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0208
Claim: Module 尾端有 1 個 Paladin HD2 board-to-board connector，可與 midplane 上的 connector 對接。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 202/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0209
Midplane
Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
The midplane acts as a bridge for the PCIe signal between the two Strata modules and the modules at the front of the chassis. The midplane module is vertically placed across the middle of the chassis with Paladin HD2 board-to-board connector on both sides of the module. Strata modules connect to one side of the midplane while the Orchid modules, the BlueField-4 module, the PDB module, and the management modules connects to the other side.
Atomic Claim 203/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0210
Atomic Claim 204/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0211
Claim: midplane module 垂直置於 chassis 中央，module 兩側都配置 Paladin HD2 board-to-board connector。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 205/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0212
Claim: Strata modules 連接至 midplane 的一側；Orchid modules、BlueField-4 module 與 PDB module 則連接另一側。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 206/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0213
BlueField-4
Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
The BlueField-4 DPU sits in center of the front of the chassis between the left-side Orchid module and the management module. As mentioned in the sections above, BlueField-4 is made up of a Grace CPU and a CX-9 NIC. The module also comes with 128GByte of on board LPDDR5x, 512Gbyte of on board pluggable SSD and an integrated AST2600 BMC from Aspeed. In the reference design of the VR NVL72 compute tray, BlueField-4 acts as a DPU providing up to 800Gb/s of front end networking capability. However, just like BlueField-3, BlueField-4 will only be adopted by a handful of customers, namely CoreWeave and other smaller Neoclouds customers who have less customization capability. For most hyperscalers’ deployments, the BlueField-4 module will be replaced with their in-house frontend networking module or simply with a CX-9 which is cheaper.
Atomic Claim 207/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0214
Claim: BlueField-4 DPU 位於 chassis 前方中央，介於左側 Orchid module 與 management module 之間。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 208/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0215
Claim: 如前述，BlueField-4 由 Grace CPU 與 1 顆 CX-9 NIC 組成。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 209/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0216
Atomic Claim 210/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0217
Claim: 在 VR NVL72 compute tray 的 reference design 中，BlueField-4 作為 DPU，可提供最高 800Gb/s frontend networking capability。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 211/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0218
Claim: 與 BlueField-3 類似，BlueField-4 預期只會被少數客戶採用，例如 CoreWeave 與其他 customization 能力較低的小型 Neoclouds 客戶。
Frame:COMPARISON· Mode:EXPECTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 212/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0219
Claim: 多數 hyperscalers 部署時，BlueField-4 module 預期會被自研 frontend networking module 取代，或直接改用成本較低的 CX-9。
Frame:COMPARISON· Mode:EXPECTED· Mapping:COMPLETE
開啟逐條審核
Speaking of BlueField-4, it is important to discuss the new offering Jensen highlighted at CES earlier this year: ICMS, or Inference Context Memory Storage — a platform that we hear may be rebranded to “CMX” at GTC. ICMS, or CMX, introduces a third, entirely separate network dedicated solely to context memory. CMX is a purpose-built KV cache fabric. As long-context inference pushes context windows toward millions of tokens and agentic concurrency scales across users and services, the current memory hierarchy used to store KVcache begins to look insufficient.
Atomic Claim 213/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0220
Claim: 在討論 BlueField-4 時，Jensen 於 CES 提出了 ICMS（Inference Context Memory Storage）平台。
Frame:ATTRIBUTE· Mode:ATTRIBUTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 214/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0220::SPLIT02
Claim: SemiAnalysis 聽聞 ICMS（Inference Context Memory Storage）平台可能在 GTC 改名為「CMX」。
Frame:ATTRIBUTE· Mode:RUMORED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 215/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0223
KV cache grows linearly with sequence length and multiplicatively with workload parallelism, quickly expanding beyond what any single tier of memory was designed to hold. GPU HBM, while unmatched in bandwidth and latency, is not enough on its own to store KV especially for longer sequence length queries that are becoming popular between turns or tool calls. Host DRAM extends capacity but remains node-bound and limited in aggregate footprint and ultimately has limited capacity. Meanwhile, traditional shared storage—architected for durability rather than latency —has more access time and power overhead, making it unsuitable for participation in the decode loop.
Atomic Claim 216/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0224
Claim: KV cache 會隨 sequence length 線性成長，並隨 workload parallelism 乘數增加，很快超出單一 memory tier 原先能承載的容量。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 217/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0225
Atomic Claim 218/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0226
Claim: 雖然其 bandwidth 與 latency 無可匹敵，但單靠 HBM 仍不足以儲存 KV，尤其是 turn 之間或 tool calls 間越來越常見的長 sequence length query。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 219/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0227
Atomic Claim 220/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0228
Atomic Claim 221/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0229
Atomic Claim 222/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0230
As we noted in mid-January in our Memory Model note ↗, Nvidia’s ICMS inserts a new G3.5 tier between local SSD (G3) and shared storage (G4), optimized specifically for ephemeral, recomputable KV cache. The ICMS requires a dedicated networking layer designed exclusively for KV traffic. Wherever networking is used in this architecture, it is provisioned as a context memory network — isolated from general data movement and optimized for predictable decode latency.
Atomic Claim 223/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0233
The challenge with this is that the volumes of SSDs going to ICMS / CMX are quite overblown by the industry. We worked through the math in the Memory model ↗ and Tokenomics model ↗.
Atomic Claim 224/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0235
Claim: SemiAnalysis 已在 Memory model 與 Tokenomics model 中推導相關數學。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
BlueField-4 will be the silicon anchor of this third network. Positioned on the storage array, it terminates NVMe-oF and RDMA traffic at line rate and manages KV movement independently of host CPUs and GPUs. With 2×400G SerDes links providing 800Gb/s of bandwidth, integrated Grace CPU, and LPDDR, BlueField-4 would act as the controller for a distributed context memory fabric. In a preferred DGX-style configuration, a single BlueField-4 per tray may serve four Rubin processors, with the DPU dedicated purely to KV cache traffic and not shared with generic storage I/O.
Atomic Claim 225/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0236
Claim: BlueField-4 將成為第三套 network 的 silicon anchor。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 226/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0237
Claim: BlueField-4 可在 storage array 上以 line rate terminate NVMe-oF 與 RDMA traffic。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 227/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0238
Claim: BlueField-4 可獨立於 host CPUs 與 GPUs 管理 KV movement。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 228/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0239
Claim: BlueField-4 具備 2×400G SerDes links，可提供 800Gb/s bandwidth，並整合 Grace CPU。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 229/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0240
Claim: 搭配 LPDDR，BlueField-4 可作為 distributed context memory fabric 的 controller。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 230/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0241
Claim: 在偏好的 DGX-style configuration 中，每 tray 可配置 1 顆 BlueField-4 服務 4 顆 Rubin processors，且 DPU 專門處理 KV cache traffic，不與一般 storage I/O 共用。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
The new CMX/ICMS ecosystem will likely include leading storage providers such as Weka, DDN, Dell Technologies, NetApp, VAST Data, and others.
Atomic Claim 231/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0242
Power Delivery
The power delivery module sits above the BlueField-4 module. The module receives 50V power from the internal busbar cable. Then the current is stepped down to 12V with a modular power brick. Then, 12V current is delivered to the Orchid module, the BlueField-4 module, the management modules via smaller internal busbars.
Atomic Claim 232/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0248
Claim: Power delivery module 位於 BlueField-4 module 上方。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 233/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0249
Atomic Claim 234/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0250
Atomic Claim 235/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0251
Claim: 接著，12V current 透過較小型的 internal busbars 輸送到 Orchid module、BlueField-4 module 與 management modules。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
In the VR NVL72 Component BoM and Power Budget Model ↗ we have the breakdown of the power delivery content for BlueField, Strada board, and the rest of the rack’s components.
Atomic Claim 236/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0253
Atomic Claim 237/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0252
Atomic Claim 238/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0254
System Management
The management module is made up of multiple smaller management modules that fall under this category. These modules occupy a long slim space between the BlueField-4 module and the right-side Orchid modules. The management modules are the following:
Atomic Claim 239/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0256
Claim: 這些 modules 位於 BlueField-4 module 與右側 Orchid modules 之間的細長空間。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
System Management Module (SMM)
Trusted Platform Module (TPM)
Atomic Claim 240/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0259
Claim: 其中包含 Trusted Platform Module（TPM）。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Datacenter Secure Control Module (DC-SCM)
These modules provide management security functions over the compute tray. Hyperscalers usually have their own in-house management module design. Therefore, the management modules may be different for each end customer. Besides BlueField-4, the power delivery module and the management modules are the only other two components within the compute tray that Nvidia allows customization for. Some end customers are considering integrating the management modules into the power delivery module. Nevertheless, the modules need to follow the form factor that Nvidia provides so it can fit into the designated connector on the compute tray midplane.
Atomic Claim 241/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0261
Claim: 這些 modules 為 compute tray 提供 management 與 security functions。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 242/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0262
Claim: Hyperscalers 通常有自研 management module design。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 243/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0264
Claim: 除了 BlueField-4 外，power delivery module 與 management modules 是 compute tray 內唯二另外可由 Nvidia 允許客製化的元件。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 244/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0266
Claim: 不過，這些 modules 仍需遵循 Nvidia 提供的 form factor，才能裝入 compute tray midplane 上指定的 connector。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Compute Tray Topology
The compute tray topology of VR NVL72 is roughly similar to that of GB200 and GB300. The three main differences to Grace Blackwell are the connections between GPU and ConnectX NICs, the connections to the local NVMe storage, and the connection between the BlueField-4 and ConnectX-9.
Atomic Claim 245/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0267
Claim: VR NVL72 的 compute tray topology 大致類似 GB200 與 GB300。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 246/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0268
Atomic Claim 247/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0269
Atomic Claim 248/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0270
Claim: 相較 Grace Blackwell，VR NVL72 compute tray 的另一項主要差異，是 BlueField-4 與 ConnectX-9 之間的連接方式。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
Source: Nvidia VR NVL72 BoM and Power Budget Model ↗
Firstly, the connection between the GPU and the ConnectX NICs evolved from GB200 to GB300 then to Vera Rubin. For GB200, the GPU does not have direct access to the ConnectX-7. Instead, B200 connects to Grace CPU via C2C connection then the Grace CPU talks to the ConnectX-7 over PCIe 5. For GB300, Nvidia introduced NIC direct to ConnectX-8, which allows the B300 GPU to communicate directly with the ConnectX-8 NIC without going through the Grace CPU.
Atomic Claim 249/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0271
Claim: 首先，GPU 與 ConnectX NICs 之間的連接方式，從 GB200 到 GB300 再到 Vera Rubin 持續演進。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 250/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0272
Claim: 在 GB200 中，GPU 無法直接存取 ConnectX-7。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 251/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0273
Atomic Claim 252/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0274
Claim: 在 GB300 中，Nvidia 導入 NIC direct-to-ConnectX-8，使 B300 GPU 可不經 Grace CPU 直接與 ConnectX-8 NIC 溝通。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Essentially, this means ConnectX-8 has two hosts, Grace CPU and B300 GPU. This improves latency in the backend network. However, for VR NVL72, the direct connection between Rubin GPU and ConnectX-9 is reverted back to the same design as GB200, as Rubin does not have PCIe bandwidth for two Connect-9. Rubin connects to Vera via C2C link, then Vera will connect to ConnectX-9 via PCIe6 lanes.
Atomic Claim 253/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0276
Claim: ConnectX-8 的其中一個 host 是 Grace CPU。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 254/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0275
Claim: 這代表 ConnectX-8 實質上有兩個 hosts。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 255/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0277
Claim: ConnectX-8 的另一個 host 是 B300 GPU。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 256/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0278
Claim: 關於 compute tray：此設計可改善 backend network latency。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 257/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0279
Atomic Claim 258/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0280
Claim: Rubin 先透過 C2C link 連接 Vera，再由 Vera 透過 PCIe6 lanes 連接 ConnectX-9。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Secondly, the local NVMe storage for Rubin has been moved to a different location from that of NVMe storage in Grace Blackwell. Previously, local NVMe storage was managed by BlueField-3. For VR NVL72, the local NVMe storage is physically on the Orchid module managed by the ConnectX-9.
Atomic Claim 259/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0281
Atomic Claim 260/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0282
Claim: 過去 local NVMe storage 由 BlueField-3 管理。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 261/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0283
Claim: 在 VR NVL72 中，local NVMe storage 實體位於 Orchid module，並由 ConnectX-9 管理。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Source: Nvidia ↗, Nvidia VR NVL72 BoM and Power Budget Model ↗
Lastly, the BlueField-4 DPU is able to control the 8 ConnectX-9 backend NICs allowing for unified management of both front end north-south network & back end high speed East-West networks. This system, known as Advanced Secure Trusted Resource Architecture (Astra), thus takes the provisioning and monitoring load off of the host CPU. The only issue with this is that BlueField-4 is expensive, so we expect most hyperscale customers to deploy their in-house DPU solutions instead. We will discuss customization more in the later sections.
Atomic Claim 262/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0284
Claim: 最後，BlueField-4 DPU 可控制 8 顆 ConnectX-9 backend NICs，進而統一管理 frontend north-south network 與 backend high-speed East-West networks。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 263/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0285
Atomic Claim 264/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0286
Claim: 問題在於 BlueField-4 成本高，因此 SemiAnalysis 預期多數 hyperscale customers 會改部署自研 DPU solution。
Frame:ATTRIBUTE· Mode:EXPECTED· Mapping:PARTIAL
開啟逐條審核
Evolution from Blackwell
All of these modules in the VR NVL72 compute tray, while not exactly the same, are found in the compute tray of GB200/300. The only difference is the midplane module as it is a new component introduced to eliminate internal cables form the compute tray. Also, the modules at the front of the chassis (daughter modules) are much longer than their equivalent in Blackwell to connect the signal from the midplane to the front I/O ports via PCB. In the sections below we will discuss the cableless design, the changes in thermal design, and the changes in mechanical design in the compute tray.
Atomic Claim 265/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0287
Claim: VR NVL72 compute tray 中的這些 modules，都可在前代系統找到對應。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 266/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0288
Claim: 雖然並非完全相同，但這些 modules 也存在於 GB200/300 的 compute tray。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 267/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0289
Claim: 主要例外是 midplane module；它是新加入的元件，目的在移除 compute tray 內部 cables。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 268/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0290
Compute Tray Cableless Design
As mentioned above the VR NVL72 compute tray is designed around the cableless concept. As we discussed in our PCB Supercycle Core Research note in August last year ↗ as well as our recent Core Research note on Amphenol’s AI Content ↗, there are two reasons for this design. First, flyover cables present multiple different points of failure as they can easily be damaged during assembly. Second, the high-density design of VR NVL72 leaves limited space for cables to be routed.
Atomic Claim 269/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0292
Claim: SemiAnalysis 去年 8 月的 PCB Supercycle Core Research note，以及近期關於 Amphenol’s AI Content 的 Core Research note，都指出此設計有兩個主要原因。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 270/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0291
Claim: 如前述，VR NVL72 compute tray 是以 cableless concept 為核心設計。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 271/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0293
Claim: 第一，flyover cables 存在多個潛在 failure points，且在 assembly 過程中容易受損。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 272/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0294
Replacing Internal Cables with Board-to-Board Connectors
For the GB200/300, the most valuable cable that is exclusively supplied by Amphenol is the DensiLink OverPass cable set within the compute tray. This cable provides the ethernet connection between the CX-7/8 NIC and the OSFP cages. However, this cable is extremely vulnerable to scratches and damage of the cable termination during assembly, thereby creating many points of failure. There are also several other lower-end PCIe cables in use (MCIO and SlimSAS) that also suffer from the same points of failure. These cables involve many other suppliers as well – complicating procurement and vendor management. Given the delicate nature of the cable, workers must be extremely careful while placing the cables in a very dense and compact chassis, which prolongs assembly time.
Atomic Claim 273/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0295
Claim: 在 GB200/300 中，價值最高且由 Amphenol 獨家供應的 cable，是 compute tray 內的 DensiLink OverPass cable set。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 274/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0296
Atomic Claim 275/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0298
Although a cableless design might initially appear unfavorable for Amphenol, it is in fact a positive. Signals between the Strata module and the daughter modules still need a physical interconnect. In this architecture, those signals exit the Strata board through Amphenol’s PaladinHD2 board-to-board connectors. The signal is then routed through a PCB midplane sitting in the middle of the chassis. On the other side of the PCB midplane, the daughter modules connect to the PCB midplane via another set of Paladin HD2 B2B connectors. In our VR NVL72 Component BoM and Power Budget Model ↗ we have a detailed breakdown of Amphenol’s compute tray content in Vera Rubin NVL72. This is also discussed in more detail in our article on **Amphenol’s AI Content. ↗ **
Atomic Claim 276/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0301
Claim: 雖然 cableless design 初看似乎不利於 Amphenol，但實際上反而是利多。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 277/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0307
Atomic Claim 278/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0306
Claim: SemiAnalysis 的 VR NVL72 Component BoM and Power Budget Model 詳細拆解 Amphenol 在 Vera Rubin NVL72 compute tray 中的 content。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 279/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0302
Claim: 關於 Strata board：Strata module 與 daughter modules 之間的 signals 仍需要實體 interconnect。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 280/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0303
Claim: 在此架構中，signals 會透過 Amphenol 的 PaladinHD2 board-to-board connectors 從 Strata board 輸出。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 281/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0304
Atomic Claim 282/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0305
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Relocating ConnectX-9
To accommodate this cableless design, the CX-9 NICs, that would have been on the Strata modules, are relocated to the Orchid module (from the back half to the front half of the chassis) as illustrated in the diagram below.
Atomic Claim 283/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0308
Claim: 為配合 cableless design，原本會位於 Strata modules 的 CX-9 NICs 被移到 Orchid module，也就是從 chassis 後半部移到前半部。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
For the GB200/GB300, the PCIe signal distance between the GPU/CPU and the CX-7/8 is shorter than the Ethernet/InfiniBand signal distance between the CX-7/8 and the OSFP cages. Previously – having to transmit a 200G Ethernet/InfiniBand signal from the NIC in the back half of the compute tray to the OSFP cage in the front of the compute tray necessitated the use of flyover cables as the signal loss over PCB at 200Gbit/s (uni-directional) per lane is too high.
Atomic Claim 284/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0309
Atomic Claim 285/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0310
Claim: 過去若要把每 lane 200Gbit/s 單向的 200G Ethernet／InfiniBand signal，從 compute tray 後半部的 NIC 傳到 compute tray 前方的 OSFP cage，就必須使用 flyover cables，因為該速率下經 PCB 傳輸的 signal loss 過高。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
But now that the NIC is closer to the OSFP cage, the lower speed PCIe Gen6 signal (64Gbit/s per lane uni-directional) travels the longer distance. By making the PCIe Gen6 signal longer, the signal can travel over PCB given that PCIe Gen6 has better signal integrity than the higher speed 200G Ethernet/InfiniBand signal.
Atomic Claim 286/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0311
Atomic Claim 287/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0312
PCB vs Flyover Cables
Nevertheless, it is still challenging to drive a PCIe Gen6 signal over around 500mm of PCB distance from the Strata Module to the front of the Orchid Module. In addition to having high quality SerDes, proper signal integrity is still achievable by upgrading PCB materials.
Atomic Claim 288/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0313
Atomic Claim 289/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0314
First, we must understand why high-speed signals perform worse on PCB versus flyover cables. As SerDes rates increase, high-speed channels become increasingly constrained by insertion loss introduced by PCB traces, vias, dielectric materials and conductor roughness. Insertion loss is defined as the signal power that is lost as a signal is traveling through an interconnect channel.
Atomic Claim 290/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0315
Claim: 理解此問題的第一步，是了解高速 signal 在 PCB 上的表現為何劣於 flyover cables。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 291/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0316
Claim: 隨 SerDes rate 提高，高速 channels 越來越受到 PCB traces、vias、dielectric materials 與 conductor roughness 所造成的 insertion loss 限制。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 292/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0317
Claim: Insertion loss 定義為 signal 通過 interconnect channel 時損失的 signal power。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Source: Doosan, SemiAnalysis
The three main mechanisms contributing to insertion loss in a PCB channel are conductor loss from skin effect and copper surface roughness, dielectric loss from laminate absorption, and geometry loss from discontinuities such as vias and layer changes.
Atomic Claim 293/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0318
Claim: PCB channel 的三大 insertion loss 機制，分別是 skin effect 與 copper surface roughness 造成的 conductor loss、laminate absorption 造成的 dielectric loss，以及 vias／layer changes 等 discontinuities 造成的 geometry loss。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Source: DesignCon, Circuit Foil Luxembourg
Conductor loss is driven by copper surface roughness. As signals travel down the copper traces in the PCB, energy is lost due to the resistance in copper. At higher frequencies, the signal traveling through the copper crowds toward the surface of the trace, which is known as the skin effect. On top of the natural resistance of copper, if the surface is rough, the current will not travel along a uniform path incurring more resistance and loss.
Atomic Claim 294/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0319
Atomic Claim 295/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0320
Atomic Claim 296/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0321
Atomic Claim 297/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0322
Dielectric loss is driven by the energy absorption nature of the dielectric materials. Dielectric materials, resins and glass fiber cloth, provide insulation and mechanical reinforcement function for the PCB traces. At high frequency, high-speed signal doesn’t simply travel through the copper traces, the signal traves as an electromagnetic wave with electric field extending into the dielectric materials. As the signal propagates, the dielectric absorbs a portion of the energy and dissipates as heat, contributing to insertion loss. Dielectric loss scales with frequency, hence dielectric loss is a dominant limiter of signal performance of long reach PCB traces.
Atomic Claim 298/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0323
Atomic Claim 299/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0324
Claim: Dielectric materials、resins 與 glass fiber cloth 為 PCB traces 提供絕緣與機械強化功能。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 300/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0325
Atomic Claim 301/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0326
Claim: Signal 傳播時，dielectric 會吸收部分能量並以熱形式耗散，形成 insertion loss。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 302/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0327
Geometry loss describes the insertion loss incurred from abrupt structures of the PCB traces. Real PCB channels include many abrupt structures, such as vias and layer swaps. These are like bumps in a highway, and signals could reflect backward and be interrupted increasing insertion loss.
Atomic Claim 303/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0328
Claim: Geometry loss 指的是 PCB traces 中突變結構所造成的 insertion loss。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 304/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0331
Atomic Claim 305/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0330
Atomic Claim 306/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0329
Atomic Claim 307/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0332
Atomic Claim 308/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0333
Claim: Signals 可能向後反射並受到干擾，進而提高 insertion loss。
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開啟逐條審核
Another factor that affects signal performance is cross-talk. Given the increase in the number of I/Os per GPU, lane density in the PCB also increases. Cross-talk describes the scenario where the copper traces are too close to each other and the signal from one lane affects the signal in a neighboring lane. Some copper traces are designed for power as well. When the power lanes are too close to the signal lanes, noise from the power lanes can also modulate the signal as well.
Atomic Claim 309/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0334
Atomic Claim 310/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0335
Atomic Claim 311/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0336
Atomic Claim 312/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0337
Atomic Claim 313/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0338
In conclusion, insertion loss scales with signal frequency, and high-speed signal suffers more insertion loss from PCB than from fly over cables. Hence, as traditional CPU servers upgrade to higher signaling frequencies such as upgrading to newer PCIe generations, the CPU server design increases the adoption of fly over cables to compensate for insertion loss from the PCB. The alternative solution would be upgrading PCB materials, however, fly over cables are more cost effective and remain feasible for traditional server applications.
Atomic Claim 314/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0339
Claim: 總結而言，insertion loss 會隨 signal frequency 上升，而高速 signal 在 PCB 上承受的 insertion loss 高於 flyover cables。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 315/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0340
Atomic Claim 316/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0341
For VR NVL72, the design has turned toward cableless given the higher density and manufacturing complexity of AI server. The cost saved on improving higher manufacturing yields and assembly time reduction more than offsets the higher cost of the upgraded PCB materials. It is critical that all the factors that contribute towards insertion loss in the PCB are mitigated, hence PCB material upgrades are necessary for VR NVL72. We break down the cost by component here ↗.
Atomic Claim 317/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0342
Atomic Claim 318/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0343
Atomic Claim 319/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0344
Claim: 由於必須降低 PCB 中所有造成 insertion loss 的因素，因此 VR NVL72 必須升級 PCB materials。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 320/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0345
Claim: SemiAnalysis 另有依 component 拆解的成本資料。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:CLAIM_ONLY
開啟逐條審核
PCB Materials Upgrade and Area Growth
PCB content value in VR NVL72 will grow significantly compared to that of GB200/GB300. The two main drivers of this content growth are significant material upgrades and the notable increase of high-end PCB area and layers. Our VR NVL72 Component BoM and Power Budget Model ↗ has provides the $ content breakdown of high end CCL and PCB content for VR NVL72 vs GB200/GB300.
Atomic Claim 321/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0346
Atomic Claim 322/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0348
Atomic Claim 323/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0347
Source: VR NVL72 Component BoM and Power Budget Model ↗
On the material side, CCL content upgrades from M7 to M8/M9 drives material upgrades. Copper foil is upgraded to HVLP4 across the board for the main compute and networking boards. A glass fiber cloth upgrade is necessary to reduce dielectric loss, but whether quartz cloth (Q glass) is necessary remains a debate. Below let’s discuss the materials upgrade and the key considerations behind the adoption of each material.
Atomic Claim 324/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0349
Atomic Claim 325/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0350
Atomic Claim 326/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0351
Claim: 為降低 dielectric loss，需要升級 glass fiber cloth。
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開啟逐條審核
Atomic Claim 327/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0352
Claim: 是否有必要採用 quartz cloth (Q glass) 仍有爭議。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 328/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0353
Claim: 文章接著討論 materials upgrade，以及各種材料採用背後的關鍵考量。
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開啟逐條審核
The Table below shows the CCL classification and PCB specification of each main board in Blackwell versus Rubin.
Atomic Claim 329/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0354
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
The classification of CCL materials is determined by its dielectric constant (Dk) and dissipation factor (Df) at a given frequency. Insertion loss is lower at lower Dk and Df value. The common classification is anchored to the Megtron series from Panasonic as they have been setting the industry standard. When people describe the CCL as M7 classification it usually means it matches the same Dk and Df specifications as Megtron 7 of Panasonic.
Atomic Claim 330/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0355
Atomic Claim 331/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0356
Claim: Dk 與 Df 越低，Insertion loss 越低。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 332/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0357
Atomic Claim 333/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0358
Source: Panasonic
Copper foil content in Rubin is upgraded from HVLP2 to HVLP4 grade copper foil for the signal layers. As discussed earlier, due to the skin effect, smoother copper foil equals to lower insertion loss. HVLP is the classification of copper foil standing for Ultra-Low Profile Copper Foil. The higher the HVLP grade equals to lower surface roughness.
Atomic Claim 334/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0359
Atomic Claim 335/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0360
Claim: 如前述，受 skin effect 影響，copper foil 越平滑，insertion loss 越低。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 336/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0361
Claim: HVLP 是 copper foil 的分類，代表 Ultra-Low Profile Copper Foil。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 337/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0362
For the power layers, the additional layers in Strata compared to Blackwell are mostly power layers to accommodate more power going into the GPU. By adding more dedicated power layers, cross talk is reduced as power layers and signal layers are separated. Power layer copper foils are much thicker to insulate the current travelling through it.
Atomic Claim 338/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0363
Atomic Claim 339/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0364
Atomic Claim 340/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0365
The glass fiber cloth upgrade aims to reduce the dielectric constant of CCL. Beside glass fiber cloth, resin is also a key factor contributing to dielectric constant. To achieve a desirable dielectric constant, the CCL makers have their unique recipes to their formulation of the two dielectric materials in the CCL. Currently, debate around the CCL spec is around the adoption of Quartz cloth (Q glass).
Atomic Claim 341/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0366
Claim: 升級 glass fiber cloth 的目的，是降低 CCL dielectric constant。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 342/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0367
Claim: 除了 glass fiber cloth，resin 也是影響 dielectric constant 的關鍵因素。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 343/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0368
Atomic Claim 344/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0369
Claim: 目前 CCL spec 的主要爭議之一，是是否採用 Quartz cloth (Q glass)。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Quartz cloth is the next generation material that replaces the glass fiber cloth materials as the reinforcing layer, pushing dielectric constant even lower. Besides lower dielectric constant, quartz cloth also has the benefits of being stronger, more temperature resistance, and having a lower CTE. On the other hand, the cost is multiples higher than that of the highest-grade glass fiber cloth and is much harder to process at the PCB manufacturing level, leading to worse yield.
Atomic Claim 345/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0370
Claim: Quartz cloth 是下一代 reinforcement material，用來取代 glass fiber cloth，並進一步降低 dielectric constant。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 346/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0372
Claim: 除了較低 dielectric constant，quartz cloth 的耐溫性也更高。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 347/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0373
Claim: 除了較低 dielectric constant，quartz cloth 也具備較低 CTE。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 348/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0371
Claim: 除了較低 dielectric constant，quartz cloth 的強度也更高。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 349/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0375
Claim: Quartz cloth 在 PCB 製造端也更難加工，因此良率較差。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 350/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0374
Claim: 另一方面，quartz cloth 成本是 highest-grade glass fiber cloth 的數倍。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Within VR NVL72, Quartz is initially adopted for the Orchid board and the midplane to allow the longest distance PCIe Gen 6 signal traveling through these two boards with as little insertion loss as possible. However, given the cost of the Quartz cloth and the difficulty in Q cloth processing, Nvidia is currently exploring the option of downgrading back to glass fiber cloth. The final decision is pending on the signal performance with the downgraded glass fiber cloth.
Atomic Claim 351/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0376
Claim: 在 VR NVL72 中，Quartz 最初用於 Orchid board 與 midplane，以讓最長距離的 PCIe Gen 6 signal 通過這兩塊 boards 時，insertion loss 盡可能低。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 352/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0377
Claim: 但考量 Quartz cloth 成本與 Q cloth 加工難度，Nvidia 目前正評估降回 glass fiber cloth 的方案。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 353/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0378
Claim: 最終決策仍取決於降級使用 glass fiber cloth 後的 signal performance。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Beside material upgrade, the other driver of PCB content value is the increase of high end PCB area coverage. In Grace Blackwell, the only boards with high end material are the Bianca board with M7 grade CCL and the NVSwtich board with M8 grade CCL, leaving front half of the compute tray uncovered by high end PCB board. For VR NVL72, the Orchid board and the midplane board increases the high end PCB board area in the compute tray covering the front half of the chassis. With the Strata board bigger than the Bianca board and the extra peripheral boards in the compute tray, we estimate that the area of high end PCB board increases by ~2.3 times from GB300 to VR NVL72. As the tables shows, the Orchid board is the main contributor to the delta of total high-end PCB area between GB300 and VR NVL72 rack.
Atomic Claim 354/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0379
Atomic Claim 355/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0380
Claim: 在 Grace Blackwell 中，使用 high-end material 的 board 僅有採 M7 grade CCL 的 Bianca board，以及採 M8 grade CCL 的 NVSwtich board，因此 compute tray 前半部沒有 high-end PCB board。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 356/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0381
Claim: 在 VR NVL72 中，Orchid board 與 midplane board 覆蓋 chassis 前半部，使 compute tray 內 high-end PCB board area 增加。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 357/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0382
Atomic Claim 358/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0383
Claim: 依表格所示，Orchid board 是 GB300 與 VR NVL72 rack 總 high-end PCB area delta 的主要來源。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Our VR NVL72 Component BoM and Power Budget Model ↗ has provides the $ content breakdown of high end CCL and PCB content for VR NVL72 vs GB200/GB300.
Atomic Claim 359/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0384
Compute Tray: Thermal
VR NVL72 takes liquid cooling to the next level. The VR NVL72 compute tray is 100% liquid cooled, whereas GB200 and GB300 compute trays adopt a hybrid of 85% liquid cooling and 15% air cooling. As a result of this, fans are removed from the compute tray and the cold plate coverage increases to remove heat from the front half of the chassis. An internal manifold will be placed in the middle of the chassis to distribute inlet coolant to the various modules and to collect the outlet coolant. Each of the modules within the compute tray will have a cold plate module attached. Each cold plate module connects to the internal manifolds via MQD (a smaller form factor quick disconnect specification standard by Nvidia for compact area application within the compute tray).
Atomic Claim 360/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0385
Claim: VR NVL72 把 liquid cooling 推進到更高層級。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 361/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0386
Claim: VR NVL72 compute tray 採 100% liquid cooling。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 362/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0387
Claim: GB200 與 GB300 compute trays 採 85% liquid cooling＋15% air cooling 的 hybrid design。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 363/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0388
Claim: 因此，compute tray 中移除 fans，並擴大 cold plate coverage，以帶走 chassis 前半部的熱。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 364/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0389
Claim: 關於 compute tray：Chassis 中央會配置 internal manifold，負責把 inlet coolant 分配到不同 modules，並收集 outlet coolant。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 365/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0390
Claim: compute tray 內每個 module 都會安裝 cold plate module。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 366/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0391
Claim: 每個 cold plate module 透過 MQD 連接 internal manifolds；MQD 是 Nvidia 為 compute tray 內 compact-area application 制定的較小型 quick disconnect specification。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
The coolant enters the compute tray via UQD from the left rear side of the chassis. Then, the coolant enters the internal manifold via a tube, where the coolant is distributed to all the modules. The coolant collects the heat from the different modules and re-enters the internal manifold. Finally, the coolant exits the compute tray via UQD at the rear right side of the chassis.
Atomic Claim 367/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0392
Claim: Coolant 從 chassis 左後方透過 UQD 進入 compute tray。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 368/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0393
Claim: 關於 compute tray：接著 coolant 經 tube 進入 internal manifold，再由 manifold 分配至所有 modules。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 369/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0394
Claim: 關於 compute tray：Coolant 從不同 modules 吸收熱量後，再回到 internal manifold。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 370/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0395
Claim: 最後 coolant 從 chassis 右後方經 UQD 離開 compute tray。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Several upgrades are also made on the cold plate for VR NVL72. For each Strata module, the cold plate will be provided as a single module covering the entire Strata board including two Rubin GPUs, one Vera CPU, SOCAMM modules, and the various VRM components. The cold plate of the Rubin GPU is upgraded to a “micro-channel cold plate” (MCCP). Essentially, the pitch between the channels in the cold plate is reduced to to 100 micron from 150 micron. This increases the surface area and increases the thermal dissipation capacity of the cold plate. Also, there will be a layer of gold plated on the surface contacting the Rubin GPU. The reason for this is to prevent corrosion of the copper from the liquid metal Indium TIM2.
Atomic Claim 371/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0396
Claim: VR NVL72 的 cold plate 也有多項升級。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 372/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0397
Claim: 每個 Strata module 的 cold plate 會以單一 module 形式覆蓋整塊 Strata board，包含 2 顆 Rubin GPUs、1 顆 Vera CPU、SOCAMM modules 與各種 VRM components。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 373/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0398
Claim: Rubin GPU 的 cold plate 升級為「micro-channel cold plate」（MCCP）。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 374/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0399
Claim: cold plate 內 channels 的 pitch 從 150 micron 縮小至 100 micron。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 375/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0400
Claim: 這可增加 surface area，並提高 cold plate 的 thermal dissipation capacity。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 376/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0401
Atomic Claim 377/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0402
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Beyond the Strata module, the modules at the front of the Chassis will also have a cold plate module attached. Each Orchid module will have a cold plate module covering the CX-9, the E1.S SSD, the transceiver cages and the various VRMs. The cold plate and the board will be less than 0.5U tall as two Orchid modules are stacked on top of each other in a 1U chassis. Each pair of Orchid modules shares only a pair of QD from the manifold. There will be another set of manifolds that distribute the coolant to the top and the bottom cold plates for the pair of Orchid modules. In our VR NVL72 Component BoM and Power Budget Model ↗ we have the content for all the various thermal components including the cold plate modules, manifolds, and the Quick Disconnects.
Atomic Claim 378/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0413
Claim: VR NVL72 Component BoM and Power Budget Model 也涵蓋 Quick Disconnects。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 379/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0411
Claim: SemiAnalysis 的 VR NVL72 Component BoM and Power Budget Model 涵蓋所有 thermal components 的 content，包括 cold plate modules。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 380/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0403
Claim: 除了 Strata module，chassis 前方的 modules 也會安裝 cold plate module。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 381/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0412
Atomic Claim 382/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0405
Atomic Claim 383/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0406
Claim: 關於 compute tray：每個 Orchid module 也會配置 transceiver cages。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 384/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0404
Claim: 每個 Orchid module 都會配置 cold plate module 覆蓋 CX-9。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 385/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0407
Claim: 關於 compute tray：每個 Orchid module 也會配置各種 VRMs。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 386/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0408
Claim: 由於 1U chassis 中會上下堆疊兩個 Orchid modules，因此 cold plate 與 board 的高度都會低於 0.5U。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 387/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0409
Claim: 關於 compute tray：每一對 Orchid modules 只共用一對來自 manifold 的 QD。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 388/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0410
Claim: 另有一組 manifolds，負責把 coolant 分配到該對 Orchid modules 上下兩片 cold plates。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Previously, cold plates were assembled at the L10 assembly level where the various components are put into place in the chassis. Given the modular approach, the cold plates need to be more tightly integrated with the module itself. Hence, the cold plate will be attached at the L6 assembly level right after the PCBA process. This increases the assembly efficiency as the assembly at L10 is simplified to slotting in the completed modules into the corresponding connectors and quick disconnects.
Atomic Claim 389/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0414
Claim: 過去 cold plates 在 L10 assembly level 組裝，也就是把不同 components 裝入 chassis 的階段。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 390/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0415
Claim: 由於採 modular approach，cold plates 必須與 module 本身更緊密整合。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 391/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0416
Claim: 因此 cold plate 會在 PCBA process 之後、L6 assembly level 就先安裝。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 392/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0417
Claim: 這提高 assembly efficiency，因 L10 assembly 可簡化為把已完成的 modules 插入對應 connectors 與 quick disconnects。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Compute Tray: Power Delivery
At the compute tray level, 50VDC power enters the compute tray via the busbar clips at the back of the chassis. Then power travels to the middle of the chassis via the internal busbar cables. From the internal busbar cables, the power path is split into three destinations. The first and second path goes to the left and the right Strata Board, where the internal busbar cable feeds 50VDC power to the Strata Board directly. The third path goes to the power distribution module at the front of the chassis. The internal busbar cables will feed 50VDC power to a busbar device that travels under the PCB midplane to connect to the power distribution board (PDB) on the other side of the PCB midplane. This differs from Grace Blackwell, where 50VDC power goes directly to the PDB. Then, the PDB feeds 12VDC to all the boards in the compute tray.
Atomic Claim 393/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0418
Claim: 在 compute tray level，50VDC power 從 chassis 後方的 busbar clips 進入 compute tray。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 394/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0419
Atomic Claim 395/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0420
Atomic Claim 396/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0421
Claim: 第一與第二條路徑分別通往左右兩塊 Strata Board，internal busbar cable 直接把 50VDC power 送入 Strata Board。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 397/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0422
Claim: 關於 compute tray：第三條路徑通往 chassis 前方的 power distribution module。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 398/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0423
Atomic Claim 399/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0424
Atomic Claim 400/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0425
Claim: 接著 PDB 會向 compute tray 內所有 boards 提供 12VDC。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
50VDC enters the Strata Board via one of the 50V power connectors on both sides of the Strata board. 50VDC is stepped down to 12VDC by the IBC module at the bottom of the Strata Board. Then the 12VDC will be stepped down to 1VDC by the VRM before feeding into the Rubin GPU and Vera CPU. Strata directly receives 50VDC whereas the Bianca board of Grace Blackwell receives 12VDC from the PDB. As the Strata board draws around 4800W of power (equivalent to the TDP of half a general server rack) versus Bianca at 3000W, it is necessary to deliver power to the board at a higher voltage. The benefit of moving 50VDC-12VDC conversion closer is to the reduce current and increase transmission efficiency. 96 Amps at 50V has 17x lower power loss than 400A at 12V due to the quadratic relationship between power loss and current.
Atomic Claim 401/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0426
Claim: 50VDC 透過 Strata board 兩側其中一個 50V power connector 進入 Strata Board。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 402/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0427
Claim: 50VDC 由 Strata Board 底部的 IBC module 降壓為 12VDC。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 403/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0428
Atomic Claim 404/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0429
Claim: Strata 直接接收 50VDC，而 Grace Blackwell 的 Bianca board 則從 PDB 接收 12VDC。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 405/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0430
Claim: Strata board 約消耗 4,800W，約相當於半個 general server rack 的 TDP，高於 Bianca 的 3,000W，因此必須以更高電壓向 board 供電。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 406/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0431
Atomic Claim 407/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0432
We have the volume and ASP for all the power semis for the all the various VRMs contained in the VR NVL72 Component BoM and Power Budget Model ↗.
Atomic Claim 408/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0433
Nvidia’s Christmas Present: GB300 & B300 - Reasoning Inference, Amazon, Memory, Supply Chain
Dylan Patel ↗, Myron Xie ↗, and Daniel Nishball ↗
Atomic Claim 409/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0434
Claim: 該段署名為 Dylan Patel、Myron Xie 與 Daniel Nishball。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:CLAIM_ONLY
開啟逐條審核
·
2024年12月25日
Read full story ↗
Power sloshing between Vera and Rubin is still present, a feature carried over from GB300 that we covered in our article above. This enables more efficient power planning by sharing the 4800W provided amongst both GPU and CPU. In GPU demanding loads, 2300W goes to each GPU leaving 200W for the CPU. Vera can then dynamically boost to higher power when GPU demand drops to help minimize GPU idle time while not overprovisioning power.
Atomic Claim 410/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0435
Atomic Claim 411/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0436
Atomic Claim 412/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0437
Atomic Claim 413/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0438
For the modules at the front of chassis - CX-9,BlueField-4, and management - the PDB feeds 12VDC of power to each of the modules. 50VDC l down to 12VDC at the PDB then, via a coper busbar device, the PDB feeds 12VDC to its neighboring modules. The power connector of CX-9 is located near the Paladin HD2 at the top of the modules.
Atomic Claim 414/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0439
Claim: 對 chassis 前方的 modules——CX-9、BlueField-4 與 management——PDB 會各自提供 12VDC power。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 415/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0440
Atomic Claim 416/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0441
Compute Tray: Mechanical
The mechanical components of the VR NVL72 compute tray are slightly more sophisticated than that of the Grace Blackwell. At the front of the chassis, there is a mechanical structure that separates the front into three sections, with the left and right sections housing the Orchid modules and the middle sections housing the BlueField-4, the power delivery and the management modules. Each of the modules will also have a small metal chassis. The mechanical structure provides a simple guiding mechanism that guides the modules to a blind mate process with the midplane and the internal manifolds.
Atomic Claim 417/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0442
Claim: VR NVL72 compute tray 的 mechanical components 比 Grace Blackwell 稍微複雜。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 418/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0443
Claim: Chassis 前方有 mechanical structure 將前區分成三部分：左右兩區放置 Orchid modules，中間區放置 BlueField-4、power delivery 與 management modules。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 419/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0445
Source: Nvidia, SemiAnalysis
The midplane and the internal manifolds are shipped together as a module. The mechanical design of this module is shown in the picture above. These highlighted mechanical parts acts as a loading mechanism for the modules. These loading mechanisms ensure the modules are well connected to the Paladin connectors and the MQD by applying some force to the modules locking them in place.
Atomic Claim 420/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0446
Atomic Claim 421/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0447
Claim: 該 module 的 mechanical design 如文章圖片所示。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:CLAIM_ONLY
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Atomic Claim 422/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0449
Rack Level Infrastructure: Thermal
Beyond the redesigned fanless front chassis and the 100% liquid-cooled compute tray, the most notable point in the Vera Rubin cooling architecture discussion was Jensen’s comment on coolant/water warm temperatures and the use of chillers. For many (for Mr. Market more broadly!) the statement that Vera Rubin can operate with 45C inlet temperatures, potentially avoiding mechanical compressor-based chillers, was viewed as a major surprise for much of the cooling supplier ecosystem. We instead view this as a continuation of existing trends.
Atomic Claim 423/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0450
Claim: 除了重新設計的 fanless front chassis 與 100% liquid-cooled compute tray，Vera Rubin cooling architecture 最受關注的另一點，是 Jensen 對 coolant／water warm temperatures 與 chillers 使用的評論。
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Atomic Claim 424/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0451
Claim: 原文此處是未完整拆分的片段：「For many (for Mr.」。
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Atomic Claim 425/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0452
Claim: 原文此處是未完整拆分的片段：「Market more broadly!)」。
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Atomic Claim 426/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0453
Claim: Vera Rubin 可在 45°C inlet temperature 運作、可能不需要 mechanical compressor-based chillers 的說法，對許多 cooling supplier ecosystem 參與者而言是一大意外。
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Vera Rubin will be able to operate at a 45C inlet temperature, but Blackwell is already capable of operating with inlet water temperatures above 40C (see for example Supermicro’s DLC-2 system). Major system vendors such as Lenovo and HPE have also been discussing 100% liquid-cooled architectures operating at 45C since early 2025. In 2024, HPE announced an industrial cooling system based on full liquid cooling, and similar approaches have long been used before in HPC. Lenovo discussed the next generation of its Neptune liquid solution at the 2025 OCP Summit, which is fully liquid-cooled and also uses 45C water.
Atomic Claim 427/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0455
Claim: Vera Rubin 可在 45°C inlet temperature 運行。
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Atomic Claim 428/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0456
Claim: Blackwell 已能在 40°C 以上 inlet water temperature 運作，例如 Supermicro DLC-2 system。
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Atomic Claim 429/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0457
Atomic Claim 430/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0458
Claim: 2024 年，HPE 發布以 full liquid cooling 為基礎的 industrial cooling system。
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Atomic Claim 431/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0459
Atomic Claim 432/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0460
Source: HPE
Consider Schneider’s GB300 Reference Design 111, presented in September 2025, as another example. In this reference design, the datacenter uses a dual-loop architecture: a chilled-water loop dedicated to air cooling (feeding the fan walls) and a separate, higher-temperature loop dedicated to liquid cooling. On the liquid side, the TCS circulates coolant to the cold plates at roughly 40C and returns it at a higher temperature, while the CDU transfers that heat into the facility water loop, which can enter the CDU at approximately 37C.
Atomic Claim 433/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0461
Claim: Schneider 於 2025 年 9 月提出的 GB300 Reference Design 111 也是另一個案例。
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Atomic Claim 434/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0462
Claim: 在此 reference design 中，datacenter 採 dual-loop architecture：一套 chilled-water loop 專供 air cooling／fan walls，另一套較高溫的 loop 專供 liquid cooling。
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Atomic Claim 435/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0463
Claim: 在 liquid side，TCS 以約 40°C coolant 供給 cold plates，回水溫度則更高。
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Atomic Claim 436/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0464
Source: Schneider
So 45C cooling is not entirely new. Even with this capability, most operators deploying Blackwell are still designing for 20-30C water temperatures. As a rough approximation, current Blackwell inlet temperatures are around room temperature, with outlet temperatures in the 40-50C range. Only a small number of operators, such as Firmus, have removed chillers from the loop (even with systems like GB200) in favor of highly optimized economizer designs where climate permits. Avoiding the compression step in mechanical cooling can deliver meaningful energy efficiency gains.
Atomic Claim 437/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0466
Atomic Claim 438/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0467
Atomic Claim 439/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0468
Now, how does Nvidia cool this heat monster, given that Vera Rubin’s power consumption and heat generation is roughly double that of Blackwell? Before answering, it is worth adding another consideration. Warmer inlet temperatures, while improving energy efficiency, can make cooling more challenging as inlet temperatures approach the maximum outlet temperature (the system’s ceiling temperature) and the delta-T tightens. With less temperature differential, you need higher water/coolant flow to remove the same amount of heat. In Blackwell reference architectures, the ceiling temperature is around 65C (e.g. see the Vertiv GB200 NVL72 reference design).
Atomic Claim 440/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0470
Claim: 問題是：在 Vera Rubin power consumption 與 heat generation 約為 Blackwell 兩倍的情況下，Nvidia 要如何冷卻這個高熱負載系統？
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Atomic Claim 441/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0471
Claim: 在回答前，還需要加入另一項考量。
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Atomic Claim 442/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0475
Claim: 在 Blackwell reference architectures 中，ceiling temperature 約為 65°C，例如 Vertiv GB200 NVL72 reference design。
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Source: Vertiv
Although NVIDIA initially did not formally publish full specifications for Vera Rubin’s liquid cooling system, we believe the platform will support maximum coolant return temperatures up to 65C. This aligns with Nvidia’s warm-water operating envelope, and while the exact implication for delta-T depends on the chosen supply setpoint and flow control strategy, we can expect a slightly tighten delta-T. The pressure envelope is expected to be unchanged versus GB200, with maximum operating pressure of 72 psig (5 bar) and minimum burst pressure of 217 psig (15 bar), aligning with OCP’s MGX rack-level liquid-cooling specification.
Atomic Claim 443/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0476
Claim: 雖然 NVIDIA 起初未正式公布 Vera Rubin liquid cooling system 的完整 specification，SemiAnalysis 認為該平台會支援最高 65°C coolant return temperature。
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Atomic Claim 444/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0477
Atomic Claim 445/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0479
Claim: Pressure envelope 預期與 GB200 相同：maximum operating pressure 72 psig（5 bar）、minimum burst pressure 217 psig（15 bar），符合 OCP MGX rack-level liquid-cooling specification。
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
In practice, cooling follows straightforward physics. To cool a system, you must deliver sufficient water/coolant at the appropriate temperature and pressure through the loop. If you want to increase the cooling capacity of a CDU, you increase flow rate while managing pressure, which in this case implies around a 2.0-2.5x flow increase, depending on how far outlet temperatures are actually pushed by operators.
Atomic Claim 446/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0482
Nvidia has indicated that Vera Rubin increases liquid flow rate and achieves nearly double the thermal performance vs Blackwell, without increasing CDU pressure head or introducing additional cooling complexity or cost. Nvidia has achieved this by optimizing the entire hydraulic path. We expect larger quick disconnects to support higher flow, as well as updated manifolds and piping. As seen in the image below, vendor roadmaps suggest that, at least for the next generation of racks, 2 inch QDs should be sufficient to accommodate higher flow while staying within pressure and flow-velocity limits.
Atomic Claim 447/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0483
Claim: Nvidia 表示，Vera Rubin 提高 liquid flow rate，thermal performance 接近 Blackwell 的兩倍，同時不提高 CDU pressure head，也不增加額外 cooling complexity 或 cost。
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Atomic Claim 448/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0484
Atomic Claim 449/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0485
Claim: SemiAnalysis 預期會採更大的 quick disconnects 以支援更高 flow，並更新 manifolds 與 piping。
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Source: CoolIT
Procurement and Cooling Vendor Implications
The primary vendor implication of the updated cooling architecture and doubled power density relates to CDUs and the rack-to-CDU ratio. Today, a CDU can support around 10 GB200 racks. With a rack generating about 2x the heat, that ratio would need to decline unless CDU capacity increases, implying either more CDUs or higher-capacity CDUs. We believe most major operators expect to maintain a ratio of around 10 racks per CDU. As rack power density rises, this points to larger CDUs. Today, in-row CDUs offer cooling capacities up to roughly 2 MW, but we expect future facility CDUs to reach 3-6 MW. Delta currently leads in the CDU specialist segment, alongside Schneider Electric, Vertiv, and nVent. Foxconn and Quanta dominate the system integrator category.
Atomic Claim 450/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0487
Claim: 更新 cooling architecture 與加倍 power density 對供應商最主要的影響，在於 CDU 以及 rack-to-CDU ratio。
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Atomic Claim 451/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0488
Atomic Claim 452/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0489
Atomic Claim 453/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0490
Atomic Claim 454/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0491
Claim: 隨 rack power density 提高，這將推動更大型 CDU。
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Atomic Claim 455/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0492
Atomic Claim 456/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0493
Atomic Claim 457/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0494
Atomic Claim 458/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0495
Source: CoolIT
The shift from liquid + air to 100% liquid systems, combined with higher flow rates and greater cooling capacity, will require changes across the cooling stack. Fans and radiators used in L2A CDUs will become less critical over time. That said, L2A is likely to maintain meaningful share during the current upcycle, where deployment speed matters more than full optimization, though the long-term trajectory clearly favors L2L. High-density L2L systems will also require redesigns across much of the TCS. This includes updated manifolds, larger quick disconnects (Colder Products Company, Danfoss, Staubli, Parker Hannifin), gold-plated cold plates (AVC, Delta, Boyd, CoolIT, Auras) and, very critically, larger pumps capable of delivering the required water volume. Pump sizing is directly linked to power density and the heat that must be removed. Even manufacturers of motor and drive components used in these pumps, such as Allegro MicroSystems, could see their prospects change as either larger motors, more motors, or both are required. In summary, higher heat on the TCS loop likely increases content/MW for white-space cooling vendors. QDs should benefit most, alongside manifolds and cold plates, with CDUs also benefiting, though to a lesser extent.
Atomic Claim 459/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0497
Atomic Claim 460/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0498
Atomic Claim 461/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0499
Atomic Claim 462/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0500
Claim: 需要更新的項目包括 manifolds、更大型 quick disconnects（Colder Products Company、Danfoss、Staubli、Parker Hannifin）、gold-plated cold plates（AVC、Delta、Boyd、CoolIT、Auras），以及非常關鍵、能提供所需 water volume 的更大型 pumps。
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Atomic Claim 463/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0501
Claim: Pump sizing 直接取決於 power density 與需要移除的熱量。
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Atomic Claim 464/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0502
Claim: 即使是這些 pumps 所使用 motor、drive components 的製造商，例如 Allegro MicroSystems，也可能因需要更大的 motors、更多 motors，或兩者同時增加而改變其成長機會。
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Atomic Claim 465/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0503
Claim: 總結而言，TCS loop 熱負載提高，可能增加 white-space cooling vendors 的 content/MW。
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Atomic Claim 466/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0504
Claim: QDs 預期受益最大，manifolds 與 cold plates 也受益；CDUs 同樣受益，但程度較低。
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For the FWS layout, the headline implication is the potential for chiller-less designs. While we addressed this debate in a separate explanatory note for our core research and datacenter model subscribers, we reiterate that this is not entirely disruptive. Some operators are already running Blackwell systems without chillers in more AI-optimized designs, while others choose to retain chillers for workload flexibility, mixed-hall compatibility, redundancy, and reliability. Over the long term, we expect AI-optimized systems to make chillers less necessary, with content shifting from air-cooled chillers toward dry coolers or adiabatic towers. We currently estimate roughly 0.2M/MW for dry coolers or adiabatic towers. SPX Technologies, alongside BAC and Evapco, could benefit, while Johnson Controls, Carrier, and Trane may be challenged. Nonetheless, we expect this efficiency/flexibility trade-off to persist in the medium term and do not foresee a chiller downturn occurring overnight. See our Industrials Model for more details. ↗
Atomic Claim 467/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0505
Atomic Claim 468/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0507
Atomic Claim 469/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0508
Claim: 長期而言，SemiAnalysis 預期 AI-optimized systems 會降低對 chillers 的需求，content 會從 air-cooled chillers 轉向 dry coolers 或 adiabatic towers。
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Atomic Claim 470/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0509
Claim: SemiAnalysis 目前估計，air-cooled chiller content 約為每 MW 50 萬美元，而 dry coolers 或 adiabatic towers 約為每 MW 20 萬美元。
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Atomic Claim 471/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0510
Claim: SPX Technologies、BAC 與 Evapco 可能受益；Johnson Controls、Carrier 與 Trane 則可能面臨挑戰。
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Atomic Claim 472/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0511
Atomic Claim 473/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0512
Claim: 更多細節可參考 SemiAnalysis Industrials Model。
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Rack Level Infrastructure: Power Delivery
In the GB200 article from 2024 ↗, we discussed the previous evolution on power delivery from node level PSU (power supply unit) to centralized rack level power shelf. As VR NVL72 rack TDP reaches 180kW-220kW per rack from 120kW-140kW for GB200 and GB300, the power delivery infrastructure has evolved yet again. In the section below we will discuss the power delivery infrastructure at the rack level of the reference design and the power delivery at the compute tray level for VR NVL72.
Atomic Claim 474/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0513
Claim: 2024 年的 GB200 文章曾討論 power delivery 從 node-level PSU（power supply unit）演進到 centralized rack-level power shelf。
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Atomic Claim 475/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0514
Since the deployment of GB200, the main theme of the power delivery infrastructure evolution has been about transmission efficiency and power stability. Hyperscalers are developing power delivery infrastructure to address the challenges that comes with high density AI server racks with the roadmap set to 1MW per rack in the next couple of years. Hence, HVDC (high voltage direct current) power rack, BBU (battery back up units), CBU (capacitor backup units), liquid cooled busbar, and SST (solid state transformers) are being developed to increase transmission efficiency and power stability. These will be deployed by customers depending on their proprietary infrastructure designs. For more detail on this, we wrote about the challenge on the grid with AI training in this report. ↗
Atomic Claim 476/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0515
Atomic Claim 477/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0516
Claim: Hyperscalers 正開發新的 power delivery infrastructure，以處理 high-density AI server racks 的挑戰；未來幾年 roadmap 已指向每 rack 1MW。
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Atomic Claim 478/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0517
Claim: 因此，HVDC（high voltage direct current）power rack、BBU、CBU（capacitor backup units）與 liquid-cooled busbar 等技術都在發展。
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Atomic Claim 479/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0518
Atomic Claim 480/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0520
Claim: SemiAnalysis 另有報告討論 AI training 對電網造成的挑戰。
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
For the VR NVL72 reference design, the power delivery infrastructure at the rack level includes four 110kW power shelves. The VR NVL72 system has a TDP up to 220kW for the 2300W Rubin TDP SKU. The design with four 110kW power shelves is an N+1 redundancy approach. Each 110kW power shelf is 3U tall and includes six 18.3kW PSU with built in capacitors in the PSU. Each power shelf receives three phase 415VAC-480VAC of power from two 100A whips. The power shelves step down the power from 415VAC-480VAC to 50VDC and sends it to the busbar. Interestingly, the busbar of VR NVL72 is rated for 5000A+, which is much higher than that of Grace Blackwell at 2900A. Given the extremely high current and the lack of fans in the rack, the busbar has to be liquid cooled.
Atomic Claim 481/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0521
Claim: 在 VR NVL72 reference design 中，rack-level power delivery infrastructure 包含 4 個 110kW power shelves。
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Atomic Claim 482/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0522
Atomic Claim 483/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0524
Claim: 每個 110kW power shelf 高度為 3U。
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Atomic Claim 484/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0525
Claim: 每個 110kW power shelf 內含 6 個 18.3kW PSU，且 PSU 內建 capacitors。
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Atomic Claim 485/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0526
Claim: 每個 power shelf 從兩條 100A whips 接收三相 415VAC–480VAC power。
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Atomic Claim 486/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0527
Atomic Claim 487/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0528
Atomic Claim 488/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0529
Source: TE Connectivity, OCP 2025
For the hyperscale customers, they might choose to deploy a standalone power rack either in LVDC (low voltage direct current) or HVDC (high voltage direct current). Below we provide two possible scenarios of the power rack deployment for VR NVL72.
Atomic Claim 489/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0530
Claim: Hyperscale customers 可能選擇部署 standalone power rack，可採 LVDC（low voltage direct current）或 HVDC（high voltage direct current）。
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Atomic Claim 490/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0531
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
First, VR NVL72 rack with an HVDC power rack running at 800VDC (Nvidia Spec) or +/-400VDC (OCP Spec). Since the VR NVL72 rack busbar is still running at 50V and the compute tray can only take in 50V, the 800VDC from the power rack cannot be directly delivered to the busbar. There would still be DC-DC power shelves in the VR NVL72 rack. The DC-DC power shelves will step down the voltage of the current from 800VDC to 50VDC as demonstrated below.
Atomic Claim 491/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0532
Atomic Claim 492/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0533
Atomic Claim 493/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0534
Atomic Claim 494/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0535
Source: OCP, Meta, SemiAnalysis
Second, some customers, namely Meta, may look to integrate their network switch rack with BBU and CBU shelves for efficiency and peak shaving. This allows more CBU and BBU capacity that wouldn’t have been able to fit in the GPU rack. The BBU/CBU and switch rack will be connected to the GPU rack with 50V horizontal busbars. Meta calls this the high power rack, discussed at OCP.
Atomic Claim 495/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0536
Atomic Claim 496/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0537
Atomic Claim 497/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0538
Atomic Claim 498/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0539
We have more detailed power and architecture details in our VR NVL72 Component BoM and Power Budget Model ↗.
Atomic Claim 499/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0540
Claim: SemiAnalysis 另有更詳細的 power 資訊。
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開啟逐條審核
Atomic Claim 500/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0542
Claim: SemiAnalysis 另有 Power Budget Model。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:CLAIM_ONLY
開啟逐條審核
Atomic Claim 501/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0541
Networking: NVLink 6, Rubin Scale Out
NVIDIA’s gen-on-gen innovations are evolutionary and not revolutionary. With GPU scale-up and scale-out bandwidth doubling approximately every 18 months, the copper infrastructure in NVIDIA racks are being innovated to accommodate higher bandwidth workloads. Scale-up network infrastructure will eventually involve optics to build larger world sizes, but that is the topic of a separate article.
Atomic Claim 502/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0543
Atomic Claim 503/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0544
Atomic Claim 504/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0545
Claim: Scale-up network infrastructure 最終將導入 optics，以建立更大的 world size。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 505/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0546
Claim: 這是另一篇獨立文章的主題。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:CLAIM_ONLY
開啟逐條審核
The below table shows the evolution of scale-up and scale-out networking speeds. NVLink 6 used in Vera Rubin doubles NVLink bandwidth by implementing bi-directional signaling over the same number of copper cables - effectively delivering 4 Lanes of 200G per NVLink. Much more on this in the following sections.
Atomic Claim 506/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0547
Claim: 文章表格呈現 scale-up 與 scale-out networking speed 的演進。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 507/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0548
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Let’s step through key features of Rubin’s networking and the architectures that are likely to be built around Rubin scale-up and scale-out networks.
Atomic Claim 508/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0550
Bi-directional SerDes for Scale-Up
The doubling of bandwidth per logical GPU from NVLink 5 in GB300 NVL72 to NVLink 6 in Vera Rubin NVL72 are made possible by using a simultaneous bi-directional SerDes for the copper backplane instead of increasing the modulation or baud rate. Whereas NVLink 5 delivers 224G per electrical lane, NVLink 6.0 delivers 448G per electrical lane. Each electrical lane is one differential pair (DP) consisting of two conductors that carry equal magnitude, and opposite polarity signals.
Atomic Claim 509/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0551
Claim: 從 GB300 NVL72 的 NVLink 5 到 Vera Rubin NVL72 的 NVLink 6，每個 logical GPU bandwidth 加倍，關鍵是 copper backplane 改採 simultaneous bi-directional SerDes，而不是提高 modulation 或 baud rate。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 510/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0552
Atomic Claim 511/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0553
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
This gives rise to the engineering problem of ensuring that a clean signal can be received at either end of the wire because two signals sent in opposite directions over the same copper wire will superpose to form a composite signal that is different from the intended transmitting signal.
Atomic Claim 512/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0554
In optics, bidirectional interconnect can be achieved by integrating an optical circulator to a transceiver as discussed in our TPUv7 article ↗ published late last year. The circulator works by routing the inbound and outbound signal onto separate paths ↗, ensuring no overlaps between both at the photodiode receiver. Bidirectional interconnect is, however, much trickier in the copper domain. A circulator cannot be used as copper cables are linear transmission lines, which means that the inbound and outbound signals will be summed at the receiver through superposition. The receiver at each end of the copper wire therefore needs a mechanism to separate the local TX from the local RX.
Atomic Claim 513/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0555
Claim: 在 optics 領域，bidirectional interconnect 可透過把 optical circulator 整合進 transceiver 達成；SemiAnalysis 去年底的 TPUv7 文章曾討論此設計。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 514/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0556
Claim: Circulator 會把 inbound、outbound signals 導向不同路徑，確保兩者在 photodiode receiver 不重疊。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 515/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0557
Atomic Claim 516/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0558
Claim: copper cables 是 linear transmission lines，因此不能使用 circulator；inbound、outbound signals 會在 receiver 透過 superposition 相加。
Frame:RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 517/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0559
The solution to this problem is the use of a hybrid at each end of the wire. Without a hybrid, there will be self-interference at the local RX because both the local TX and local RX are being transmitted along the same wire:
Atomic Claim 518/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0560
Atomic Claim 519/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0561
B0+A0=BA0
An inverted copy of the local TX must therefore be generated at the local RX for proper echo cancellation:
Atomic Claim 520/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0562
Claim: 因此 local RX 必須產生 local TX 的 inverted copy，才能進行正確的 echo cancellation。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
B0+A0=BA0+(−A0)=B0
Atomic Claim 521/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0563
The diagram below illustrates this dynamic:
Atomic Claim 522/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0564
Claim: 文章下方示意圖說明此 dynamic。
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開啟逐條審核
Source: IEE Explore ↗
While bidirectional signaling is being used for short-reach (less than 5mm) die-to-die interconnect, what stands out is that NVIDIA has extended this technology to longer reach transmission over copper backplane with a reach of at least 1m.
Atomic Claim 523/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0565
Claim: Bidirectional signaling 已用於短距離（小於 5mm）的 die-to-die interconnect；值得注意的是，NVIDIA 已把此技術延伸到至少 1m reach 的 copper backplane 長距離傳輸。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
The challenge with bidirectional signaling is that echo cancellation must be precisely calibrated or slight delays in the generation of the local TX copy can cause link failure. However, if NVIDIA were to continue using the 200G SerDes, doubling the bandwidth would mean doubling the number of copper cables at the backplane, which is a tall order for several reasons.
Atomic Claim 524/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0566
Claim: Bidirectional signaling 的挑戰在於 echo cancellation 必須精準校準；local TX copy 生成若有輕微 delay，就可能造成 link failure。
Frame:ATTRIBUTE· Mode:HYPOTHETICAL· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 525/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0567
Cramming in approximately five thousand copper cables on the backplane at the Blackwell generation has introduced non-trivial reliability failure modes at scale. To double scale-up bandwidth while staying on regular 200G SerDes would require the backplane to double to ten thousand copper cables: only further increasing the manufacturing complexity and likelihood of failure of the system.
Atomic Claim 526/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0568
Atomic Claim 527/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0569
Blackwell Copper Backplane ↗, Source: Nvidia
Atomic Claim 528/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0570
NVIDIA could also opt to deploy wider racks instead as is the case of AMD’s Helios rack ↗, but this could affect the signal integrity on the PCB as electrical signals will have to traverse a longer path.
Atomic Claim 529/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0571
Atomic Claim 530/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0572
Scale-Up Network – NVLink 6
The bidirectional SerDes technology employed on the copper backplane is used for NVIDIA’s scale-up network. For Vera Rubin NVL72, the scale-up network continues to be rail-optimized with all-to-all connectivity between each GPU and switch ASIC in the scale-up domain.
Atomic Claim 531/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0573
Claim: copper backplane 所採用的 bidirectional SerDes technology 用於 NVIDIA 的 scale-up network。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 532/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0574
Claim: 在 Vera Rubin NVL72 中，scale-up network 仍採 rail-optimized design，scale-up domain 內每顆 GPU 與每顆 switch ASIC 之間都為 all-to-all connectivity。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Last year, we discussed NVIDIA’s GB200 scale-up architecture, which consists of 18 NVLink 5 Switch chips in a single rack for the NVL72 system.
Atomic Claim 533/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0575
GB200 Hardware Architecture - Component Supply Chain & BOM
Dylan Patel ↗, Wega Chu ↗, and 4 others
Atomic Claim 534/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0576
Claim: 該段作者包含 Dylan Patel、Wega Chu 與另外 4 位作者。
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開啟逐條審核
·
2024年7月17日
Read full story ↗
Although the NVLink 6 Switch used in the VR NVL72 system delivers the same per switch 28.8T aggregate bandwidth as NVLink 5 Switch, the SerDes speed on the NVLink 6 Switch is double the SerDes speed of NVLink 5 Switch but with the same number of DPs. As such, in order to deliver double the aggregate scale-up bandwidth required for NVLink 6, Vera Rubin NVL72 racks will contain double the number of NVLink Switches as compared to GB200 racks. This translates to four NVLink Switch chips per tray on 9 switch trays, or 36 NVLink Switch chips in each rack.
Atomic Claim 535/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0577
Atomic Claim 536/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0578
Claim: 因此，為提供 NVLink 6 所需的 2 倍 aggregate scale-up bandwidth，Vera Rubin NVL72 rack 的 NVLink Switch 數量會是 GB200 rack 的 2 倍。
Frame:COMPARISON· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 537/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0579
Each VR NVL72 Switch tray contains four NVLink 6 Switch ASICs and one system management module. The design of the Rubin NVLink 6 Switch tray is also simpler and relatively seamless compared to the first Oberon NVLink 5 Switch released for GB200 because Rubin NVLink 6 Switch trays will not use flyover cables. As such, all NVLink signals will run over the PCB.
Atomic Claim 538/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0580
Claim: 每個 VR NVL72 Switch tray 內含 4 顆 NVLink 6 Switch ASICs 與 1 個 system management module。
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開啟逐條審核
Atomic Claim 539/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0581
Atomic Claim 540/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0582
The NVLink 6 Switch board is liquid cooled and will be covered with a cold plate, which is a single module. Connected to the NVSwitch tray is the system management module (SMM) that comes with a CPU and acts as a host to the switch tray. The switch tray to SMM connection uses flyover cables, but this is the only flyover cable connection required in the entire Vera Rubin NVL72 system. Given that the PCIe connection is lower speed and the NVLink Switch tray contains relatively few modules, assembly of the switch tray is unlikely to be challenging.
Atomic Claim 541/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0583
Atomic Claim 542/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0584
Claim: NVLink 6 Switch board 會由單一 module 形式的 cold plate 覆蓋。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 543/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0585
Atomic Claim 544/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0586
Claim: switch tray 與 SMM 之間使用 flyover cables 連接。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 545/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0587
Claim: 這是整套 Vera Rubin NVL72 system 唯一需要的 flyover cable connection。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 546/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0588
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
The diagram below shows how the NVLink 6 signal traverses through the tray. Each of the green lines represents nine 400G logical ports of NVLink 6, or 18 TX/RX lanes of 200G. Because there is only 1 DP per lane using bidirectional SerDes, there are a total of 18 DPs between any connector and any switch for a total of 72 DPs per connector, which is the same as prior generation of NVLink 5 Switch Tray.
Atomic Claim 547/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0589
Atomic Claim 548/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0590
Atomic Claim 549/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0591
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
As previously explained, high speed signals require better PCB materials, especially for NVLink 6 which has much lower tolerance for insertion loss given the use of bidirectional signaling. The number of lanes between the PaladinHD2 connectors and the NVLink Switch also creates complexity for PCB design. Hence, the NVLink 6 Switch board PCB is upgraded to 32 layers with M8+ graded CCL - minimally LDK2 glass fiber cloth or potentially Quartz fiber cloth.
Atomic Claim 550/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0592
Claim: 如前述，高速 signals 需要更好的 PCB materials；尤其 NVLink 6 因採 bidirectional signaling，對 insertion loss 的容忍度更低。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:PARTIAL
開啟逐條審核
Atomic Claim 551/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0593
Atomic Claim 552/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0594
Claim: 因此，NVLink 6 Switch board PCB 升級為 32 layers、M8+ grade CCL，至少採 LDK2 glass fiber cloth，也可能採 Quartz fiber cloth。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
We have more details on the switch tray and various components in the VR NVL72 Component BoM and Power Budget Model ↗.
Atomic Claim 553/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0596
Atomic Claim 554/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0597
Claim: SemiAnalysis 另有 Power Budget Model。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:CLAIM_ONLY
開啟逐條審核
Zooming out, backplane copper cables are used to connect NVLink Switch trays to the GPU trays for the VR NVL72 system. Although the bandwidth doubles, with bi-directional SerDes, the number of cables required does not change from the GB300 backplane generation to the Vera Rubin NVL72 backplane generation. The number of connectors and the number of DPs per connector also does not change from Grace Blackwell NVL72 to VR NVL72.
Atomic Claim 555/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0598
Atomic Claim 556/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0600
Atomic Claim 557/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0601
Grace Blackwell NVL72 Scale-up Topology. Source: SemiAnalysis AI Networking Model ↗
Atomic Claim 558/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0602
Vera Rubin NVL72 Scale-up Topology. Source: SemiAnalysis AI Networking Model ↗
Atomic Claim 559/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0603
Claim: 此處展示 Vera Rubin NVL72 Scale-up Topology。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
While the VR NVL72 system features GPUs and scale-up switches that are connected by copper cables, the VR HGX system features servers consisting of eight Rubin GPUs and four NVLink Switch chips. The second meaningful difference between the NVL72 and HGX deployments is that the former has a scale-out bandwidth of 1.6T per GPU while the latter only has a scale-out bandwidth of 800G per GPU. How is it that all Rubin 200 deployments use CX-9 NICs even though some deployments have half the per GPU scale-out bandwidth?
Atomic Claim 560/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0604
Atomic Claim 561/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0605
Atomic Claim 562/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0606
The HGX Rubin NVL8 server consists of eight 800G CX-9 NIC packages – one NIC per GPU – which means that the scale-out bandwidth does not increase from its predecessor, the HGX B300 server. The Vera Rubin NVL72 deployment on the other hand doubles the per GPU scale-out bandwidth to 1.6T, but not by doubling the bandwidth per NIC. Rather, the “1.6T NIC” attached to each Rubin chip is comprised of two 800G CX-9 packages that is connected to the Vera CPU by PCIe Gen 6.0 lanes.
Atomic Claim 563/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0607
Atomic Claim 564/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0608
Claim: Vera Rubin NVL72 則把每顆 GPU scale-out bandwidth 加倍至 1.6T，但並非把單顆 NIC bandwidth 加倍。
Frame:COMPARISON· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Each compute tray on the VR NVL72 has eight 800G CX-9 NICs, but there are two possibilities for the number of OSFP cages - either one 1.6T OSFP cage per GPU for a total of 4 per compute tray, or two 800G OSFP cages per GPU for a total of 8 cages per compute tray. We think that the latter would be the more popular deployment assumption, and will be the base case for our discussion of scale-out networking architectures in later sections of the article.
Atomic Claim 565/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0610
Claim: VR NVL72 每個 compute tray 配置 8 顆 800G CX-9 NICs。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 566/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0611
Claim: OSFP cages 有兩種可能配置：每顆 GPU 1 個 1.6T OSFP cage、每個 compute tray 共 4 個；或每顆 GPU 2 個 800G OSFP cages、每個 compute tray 共 8 個。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 567/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0613
Claim: SemiAnalysis 也把後者作為文章後續 scale-out networking architecture 討論的 base case。
Frame:ATTRIBUTE· Mode:INFERRED· Mapping:COMPLETE
開啟逐條審核
Source: Nvidia VR NVL72 Component BoM and Power Budget Model
Connecting GPUs in the Scale-Out InfiniBand Network
Broadly, there are three flavors of scale-out deployments for Vera Rubin NVL72. We have InfiniBand-based clusters which employ the NVIDIA Quantum series of switches, NVIDIA Ethernet-based clusters employing Spectrum series switches and lastly, non-Nvidia Ethernet such as Tomahawk-based, Cisco Silicon One or Teralynx-based Ethernet switches. Some Ethernet-based clusters deployed by hyperscalers will use AECs for NIC-to-TOR and switch-to-switch connections, while other Ethernet-based clusters using only optical interconnects will usually adopt a multi-plane and multi-rail networking architecture. What is particularly noteworthy about Vera Rubin NVL72 deployments, however, is that it is the first Nvidia GPU generation where we will be seeing some Co-Packaged-Optics (CPO) deployments in the scale-out backend network.
Atomic Claim 568/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0614
Claim: 整體而言，Vera Rubin NVL72 有三類 scale-out deployment。
Frame:ATTRIBUTE· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 569/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0618
Atomic Claim 570/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0615
Claim: 第一類是 InfiniBand-based cluster，使用 NVIDIA Quantum 系列 switches。
Frame:RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 571/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0617
Atomic Claim 572/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0619
Atomic Claim 573/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0616
Atomic Claim 574/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0620
Atomic Claim 575/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0621
Claim: 部分由 hyperscalers 部署的 Ethernet-based clusters，會使用 AECs 做 NIC-to-TOR 與 switch-to-switch connections。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:COMPLETE
開啟逐條審核
Atomic Claim 576/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0622
Atomic Claim 577/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0623
Claim: Vera Rubin NVL72 特別值得注意之處，是它將成為第一個在 scale-out backend network 中出現 Co-Packaged-Optics（CPO）部署的 Nvidia GPU 世代。
Frame:NARY_RELATION· Mode:ASSERTED· Mapping:PARTIAL
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While there are both InfiniBand and Spectrum-X based clusters, the InfiniBand-based Quantum X800-34XX series of switches is more popular with Neoclouds than with hyperscalers. For InfiniBand, there are two deployment types – the first is the Quantum X800-Q3400 with pluggable optics and the second is the Quantum X800-Q3450 CPO-based switch that use co-packaged Optical Engines (OE) instead of pluggable transceivers.
Atomic Claim 578/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0624
Claim: 雖然同時有 InfiniBand 與 Spectrum-X cluster，但 InfiniBand-based Quantum X800-34XX series switches 在 Neoclouds 中比在 hyperscalers 中更普遍。
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Atomic Claim 579/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0625
Claim: InfiniBand 有兩種 deployment：Quantum X800-Q3400 使用 pluggable optics；Quantum X800-Q3450 則是 CPO-based switch，使用 co-packaged Optical Engines（OE）取代 pluggable transceivers。
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開啟逐條審核
The Quantum X800-Q3400 is logically a multi-plane switch combining 4 Quantum-3 ASICs into a single switch box, though we will dive into this equivalence later in the article. This multi-plane “topology” is abstracted away and as far as network engineers are concerned, the Q3400 is a single switch with 144 ports – or a “little boy” switch.
Atomic Claim 580/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0626
Claim: Quantum X800-Q3400 在邏輯上是 multi-plane switch，將 4 顆 Quantum-3 ASICs 組合在同一個 switch box。
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Atomic Claim 581/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0627
Claim: 關於 InfiniBand：這種 multi-plane「topology」被抽象化；對 network engineers 而言，Q3400 就是一台 144-port switch，也就是文中所稱的「little boy」switch。
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Source: SemiAnalysis AI Networking Model ↗
The InfiniBand architecture for the HGX Rubin NVL8 server is therefore effectively a single-plane, 8-rail network consisting of one 800G uplink from each HGX Rubin NVL8 GPU to a leaf switch.
Atomic Claim 582/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0628
Source: SemiAnalysis AI Networking Model ↗
For the Vera Rubin NVL72 deployment however, there are two 800G OSFP cages per GPU for a total of 1.6T per GPU bandwidth. Having two 800G logical ports per GPU is advantageous because it allows multi-plane network deployments without complex fiber management – by splitting one logical GPU two ways to two different leaf switches. As such, larger network clusters can be built with two 800G logical ports than if only one 1.6T logical port were used. In fact, as we have explained in multiple prior articles such as the networking sections of NVIDIA’s Optical Boogeyman ↗ and Microsoft’s AI Strategy Deconstructed ↗, this relationship is dictated by a simple formula for the maximum number of hosts that can be supported using a switch of k ports on an L-layer:
Atomic Claim 583/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0629
Atomic Claim 584/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0632
Atomic Claim 585/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0630
Atomic Claim 586/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0631
2(k2)L
Illustratively, consider two hypothetical VR NVL deployments with 1.6T and 800G logical ports respectively. A 1-plane, 3-layer network with one 1.6T logical ports achieves only a maximum cluster size of 93,312 GPUs, or:
Atomic Claim 587/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0633
Atomic Claim 588/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0634
2(115,2001,6002)3=2(722)3=93,312
Atomic Claim 589/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0635
Claim: 關於 InfiniBand：其公式為 2(115,2001,6002)3=2(722)3=93,312。
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開啟逐條審核
By one 1.6T logical port, we mean that the two 800G OSFP cages connected to each GPU are connected to a single, dual-port 1.6T transceiver at the leaf layer because the two 800G ports are effectively performing the function of one 1.6T port – and hence the term “logical”.
Atomic Claim 590/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0636
Source: SemiAnalysis AI Networking Model ↗
To scale beyond the maximum cluster size of 93,312 GPUs, a 2-plane network can be deployed in which each of the two 800G OSFP cages supporting a GPU are linked to separate leaf switches on different network plans. This allows you to build a 186,624-GPU cluster size as diagrammed below and even scale up to 746,496-GPU cluster sizes.
Atomic Claim 591/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0637
Atomic Claim 592/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0638
2(115,2008002)3=2(1442)3=746,496
Atomic Claim 593/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0639
Claim: 關於 InfiniBand：其公式為 2(115,2008002)3=2(1442)3=746,496。
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Source: SemiAnalysis AI Networking Model ↗
We think the second cluster with two switch planes will likely be the more prevalent reference architecture for Vera Rubin NVL72 InfiniBand deployments.
Atomic Claim 594/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0640
Claim: SemiAnalysis 認為，使用兩個 switch planes 的第二種 cluster，可能會成為 Vera Rubin NVL72 InfiniBand deployment 更普遍的 reference architecture。
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Aside from the X800-Q3400 air-cooled switch, NVIDIA will also offer a CPO version, which is the X800-Q3450 containing the same 144 ports of 800G. As pointed out earlier, what is unique about both switches is that each switch box consists of four 28.8T Quantum-3 Switch ASICs for a total of 115.2T per box switching capacity. When used in conjunction with the VR NVL72 servers, the signal from the NIC at the leaf layer is split four ways – 200G each way – to each switch ASIC within the box. Such a configuration bears logical equivalence to a 4-plane network architecture.
Atomic Claim 595/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0641
Claim: 除了 air-cooled X800-Q3400 switch，NVIDIA 也會提供 CPO 版本 X800-Q3450，同樣具備 144 個 800G ports。
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Atomic Claim 596/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0642
Claim: 兩種 switches 的特點是，每個 switch box 都由 4 顆 28.8T Quantum-3 Switch ASICs 組成，總 switching capacity 為每 box 115.2T。
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Atomic Claim 597/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0643
Claim: 搭配 VR NVL72 servers 時，leaf layer NIC 的 signal 會分成四路，每路 200G，分別進入 box 內各顆 switch ASIC。
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Atomic Claim 598/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0644
Claim: 關於 InfiniBand：這種 configuration 在邏輯上等同於 4-plane network architecture。
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Source: SemiAnalysis AI Networking Model ↗
Ethernet-Based Cluster Deployments
Although InfiniBand has been the more popular network architecture for previous NVIDIA chips such as the H100 and GB200, NVIDIA is aggressively pushing out Spectrum Ethernet-based networks and have introduced various switch SKUs:
Atomic Claim 599/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0645
SN6600, a 102.4T liquid-cooled switch;
Atomic Claim 600/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0646
SN6800, a 4 ASIC, 2048-radix 409.6T multi-plane CPO switch, offering 512 ports of 800G;
Atomic Claim 601/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0647
SN6810, a high-radix 102.4T CPO switch with three further deployment options: 512 ports of 200G, 256 ports of 400G and 128 ports of 800G.
Atomic Claim 602/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0648
For the SN6600 switch, the scale-out reference architecture is an 8-plane network where each GPU fans out eight ways to eight different planes. This is similar to the reference architecture for the 8-plane scale-out network using SN6810 switches.
Atomic Claim 603/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0649
Atomic Claim 604/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0650
Claim: 這與使用 SN6810 switches 的 8-plane scale-out network reference architecture 類似。
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Source: SemiAnalysis AI Networking Model ↗
We think that the SN6800 switch with 512 ports of 800G will be quite attractive to Neoclouds because it simplifies deployments. Similar to the X800-Q3400 scale-out network, an SN6800 scale-out network could consist of two switch planes though the SN6800 enables a much larger feasible scale-out world size.
Atomic Claim 605/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0651
Atomic Claim 606/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0652
Claim: 類似 X800-Q3400 scale-out network，SN6800 scale-out network 可由兩個 switch planes 組成，但 SN6800 可支援更大的 scale-out world size。
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開啟逐條審核
The diagram below shows what such a network could look like – though it only shows one of two planes as readers can deduce by the fact that we are only depicting 1x800G from each GPU. Note also that each SN6800 switch box consists of four ASICs, each with its own switch plane, which we will elaborate on later in the article.
Atomic Claim 607/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0653
Atomic Claim 608/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0654
Source: SemiAnalysis AI Networking Model ↗
For a 512-port switch, we can connect up to 131,072 GPUs with two layers of switches or a ludicrous 33,554,432 GPUs on 3 layers.
Atomic Claim 609/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0655
2(5122)2=131,072
2(5122)3=33,554,432
Atomic Claim 610/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0656
What advantages do CPO switches such as the SN6800 deliver for Neoclouds like Coreweave and Lambda when it comes to large-scale cluster deployments?
Atomic Claim 611/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0657
As discussed in our recent deep dive article on co-packaged optics, ↗ the first reason is that a significant amount of power can be saved by eliminating most of the transceiver content. If we compare the power consumption of one 800G DR4 optical transceiver (16-17W) to the power required by optical engines (OEs) and external light source (ELS) modules to delivery an equivalent 800G of bandwidth in the scale-out network, we see an average ~70% reduction in power used for optical transceivers. Taking a step back, this would translate to 10% in savings for the total networking equipment power consumption in a 3-Layer HGX Rubin NVL8 cluster. This reduction in networking equipment power consumption is however relatively insignificant and amounts to only ~1% of total cluster power consumption because the server’s power budget dominates the equation.
Atomic Claim 612/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0658
Claim: 如 SemiAnalysis 最近的 co-packaged optics deep dive 所述，第一個優勢是移除大部分 transceiver content，可節省大量 power。
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Atomic Claim 613/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0659
Claim: 把單顆 800G DR4 optical transceiver 的 16–17W 功耗，與在 scale-out network 中用 optical engines（OE）及 external light source（ELS）modules 提供等效 800G bandwidth 的功耗相比，optical transceivers 相關 power 平均可降低約 70%。
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Atomic Claim 614/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0660
Atomic Claim 615/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0661
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
The second benefit is a reduction in cost stemming from eliminating almost all transceivers. There is even more room for price reduction if we are looking at NVIDIA LinkX transceivers, which tend to be priced at significant premium to their generic equivalent. If we compare total networking costs for a 3-Layer network with and without CPO-based switches in the scale-out domain, we see an average of ~75% reduction in transceiver costs. However, as with the power savings above, such costs savings tend not to move the needle dramatically considering the full cluster costs.
Atomic Claim 616/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0662
Atomic Claim 617/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0663
Atomic Claim 618/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0664
Atomic Claim 619/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0665
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
We outline these calculations in more detail and discuss this topic at greater length in our CPO Book Report ↗.
Atomic Claim 620/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0666
Increased overall network reliability is another compelling point. Transceivers can be unreliable, with a large cluster certain to have ongoing link flaps. Meta’s study presented at ECOC ↗ showed strong reliability results over 15M 400G port-device hours, which is about equivalent 15 CPO switches tested for 11 months in a lab. It is an encouraging start – but we think this point could get stronger with more in field test deployments.
Atomic Claim 621/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0670
Atomic Claim 622/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0667
Atomic Claim 623/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0668
Atomic Claim 624/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0669
Atomic Claim 625/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0671
The last factor in favor of adoption of CPO that we would like to mention is the fact that some of Nvidia’s CPO switch SKUs contain the integrated fiber shuffle and can simplify the installation and maintenance of multi-plane network architectures. Recall that the SN6800 contains four Switch ASICs in a multi-plane configuration connected to ports via an integrated fiber shuffle, delivering 409.6T aggregate bandwidth, while the SN6810 uses one Switch ASIC, but without any integrated fiber shuffle, to deliver 102.4T aggregate bandwidth.
Atomic Claim 626/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0672
Atomic Claim 627/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0673
Atomic Claim 628/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0674
Claim: SN6800 以 multi-plane configuration 在同一 box 內配置 4 顆 Switch ASICs，透過 integrated fiber shuffle 連接 ports，aggregate bandwidth 達 409.6T。
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Atomic Claim 629/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0675
Claim: SN6810 使用 1 顆 Switch ASIC。
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Atomic Claim 630/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0676
But first, we will explain why we think multi-plane networking architectures are here to stay as an important preface.
Atomic Claim 631/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0677
Claim: SemiAnalysis 認為 multi-plane networking architecture 將長期存在。
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開啟逐條審核
Large-scale cluster deployments where cluster sizes exceed 100k GPUs typically utilize multi-plane network architectures because single-plane network architectures do not have enough logical ports at current switch generations to support larger networks without resorting to a high number of switch layers of 3 or more layers.
Atomic Claim 632/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0678
Recall from above that a Vera Rubin NVL72 cluster built with Q3400-X800 switches at 1.6T logical ports per GPU cannot scale beyond the maximum cluster size of 93,312 GPUs. Even if future switch generations continue to double the maximum possible switching capacity per switch box, the per GPU bandwidth is also expected to double, which means that the effective logical port count in a cluster network is unlikely to change.
Atomic Claim 633/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0679
Atomic Claim 634/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0680
What this means is that deployment of large-scale GPU clusters will continue to require multi-plane network architectures. Do note however that multi-plane networking architectures are not limited by size and we have also seen NVIDIA reference architecture deployments with multi-plane clusters that are significantly below 100k GPUs each.
Atomic Claim 635/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0681
Atomic Claim 636/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0682
Claim: 不過，multi-plane networking 並非只在超大型 cluster 才使用；SemiAnalysis 也觀察到 NVIDIA reference architecture 中，有遠低於 10 萬顆 GPUs 的 multi-plane cluster。
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開啟逐條審核
In multi-plane network architectures using the SN6600 switch instead of the CPO switch, each GPU fans out to multiple switch boxes using fiber shuffles. This requires customers to deploy shuffle boxes, patch panels and unwieldy octopus cables outside the switch box that introduce complexity in installation and maintenance.
Atomic Claim 637/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0683
Atomic Claim 638/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0684
Some of Nvidia’s CPO SKUs – such as the SN6800 and Q3450 –contain such a fiber shuffle within the switch box, with each optical engine fanning out to different logical ports. They therefore deliver higher aggregate bandwidth – 409.6T and 115.2T respectively than is possible with a switch box based on a single Switch ASIC.
Atomic Claim 639/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0685
Atomic Claim 640/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0686
Claim: 因此它們可提供更高 aggregate bandwidth，分別達 409.6T 與 115.2T，高於只用單顆 Switch ASIC 的 switch box。
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開啟逐條審核
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
For the SN6800 CPO switch, even though the bandwidth engine responsible for converting electrical to optical signals scales from 1.6T to 3.2T or 2x compared to the SN6600 switch, each 3.2T OE within the SN6800 switch box is split into four 800G logical ports that fan out within the box itself and exit the front panel through fiber connectors. This allows a single 1.6T GPU to fan out to two independent switch planes. In fact, the SN6800 switch box consists of four ASICs, which is similar to the X800-Q3400 switch box.
Atomic Claim 641/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0687
Atomic Claim 642/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0688
Atomic Claim 643/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0689
Claim: SN6800 switch box 實際由 4 顆 ASICs 組成，與 X800-Q3400 switch box 類似。
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Source: SemiAnalysis AI Networking Model ↗
As the per GPU bandwidth continues to scale to 3.2T, it is not hard to imagine a 4-plane network using SN6800 switches, where each 3.2T GPU is split four ways to connect to four different switch boxes at 800G per link.
Atomic Claim 644/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0690
In fact, if you have not already noticed – there are strong parallels between the X800-Q3400 switch (non-CPO) explained earlier in the article and a CPO switch in that both facilitate high-radix, multi-plane networking architectures while encasing within the box complex cabling that saves customers on the hassle of cable management.
Atomic Claim 645/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0691
Claim: X800-Q3400 non-CPO switch 與 CPO switch 有明顯相似處：兩者都支援 high-radix、multi-plane networking architecture，並把複雜 cabling 收納在 box 內，降低客戶 cable management 負擔。
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開啟逐條審核
Outside of the NVIDIA ecosystem, the main switch ASIC players are Broadcom, which will be manufacturing the Tomahawk 6 and Tomahawk 6 CPO ASICs, as well as Cisco, which recently announced the G300 102.4T ASIC. There are two flavors of hyperscaler backend network deployments:
Atomic Claim 646/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0692
Claim: 在 NVIDIA ecosystem 外，主要 switch ASIC 業者包括 Broadcom，其將生產 Tomahawk 6 與 Tomahawk 6 CPO ASICs；另有 Cisco，近期發布 G300 102.4T ASIC。
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Atomic Claim 647/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0693
Claim: hyperscaler backend network deployment 有兩種主要形式。
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8-plane “flat” network utilizing the full 512 switch radix;
Atomic Claim 648/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0694
Source: SemiAnalysis AI Networking Model ↗
Single plane network with 1.6T OSFP cages at the NIC.
Atomic Claim 649/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0695
Source: SemiAnalysis AI Networking Model ↗
For Meta, we think the VR NVL72 deployments will comprise only of non-scheduled fabric (NSF) clusters built using Tomahawk 6-based Minipack-4 OCP Rack 102.4T switches in each datacenter. While Meta will be using optics to connect all the switches within its cluster, it will use 1.6T AECs for NIC-to-TOR connections once 1.6T AECs become broadly available in the market. We expect the 1.6T AEC ramp to happen in the second half of calendar year 2026.
Atomic Claim 650/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0696
Claim: 對 Meta，SemiAnalysis 認為 VR NVL72 部署只會包含 non-scheduled fabric (NSF) clusters，並在各 datacenter 使用 Tomahawk 6-based Minipack-4 OCP Rack 102.4T switches。
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Atomic Claim 651/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0697
Atomic Claim 652/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0698
Source: SemiAnalysis AI Networking Model ↗
The catch is that 102.4T Minipack-4 switches may not be shipped in time for Vera Rubin NVL72 rack deployments, and if this were to be the case, some NSF clusters will be shipped using 51.2T Minipack-3 switches instead. This means that gearboxes within the AECs will have to be used to convert 200G per lane SerDes speed at the NIC to 100G per lane SerDes speed at the switch.
Atomic Claim 653/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0699
Claim: 風險在於 102.4T Minipack-4 switches 可能來不及在 Vera Rubin NVL72 rack deployment 時出貨。
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Atomic Claim 654/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0700
Claim: 若發生此情況，部分 NSF clusters 會改用 51.2T Minipack-3 switches 出貨。
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Atomic Claim 655/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0701
Meta will not be the only hyperscaler using 1.6T AECs for its VR200 deployments, however. We think xAI will use 1.6T AECs for both NIC-to-TOR and switch-to-switch connectivity at the leaf, spine and core layers. It will be a single-plane network replacing most 1.6T transceivers at the switch boxes – and this can give Credo plenty of pricing power.
Atomic Claim 656/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0702
Atomic Claim 657/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0703
Atomic Claim 658/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0704
Hyperscaler Customization and Assembly Logistics
Customization
For GB300, although the reference design has four ConnectX-8 NICs for the backend network and one Bluefield-3 for frontend network, most hyperscalers have their own design and alternative networking configurations, especially for Bluefield-3. Beside networking configuration, the power delivery modules, the local NVMe storage, and the management module are also highly customized and differentiated across customers.
Atomic Claim 659/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0705
Claim: 在 GB300 中，雖然 reference design 的 backend network 配置 4 顆 ConnectX-8 NICs、frontend network 配置 1 顆 Bluefield-3，但多數 hyperscalers 都有自研設計與替代 networking configurations，尤其是 Bluefield-3 部分。
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Atomic Claim 660/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0706
Atomic Claim 661/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0707
For example, for some racks, even Amazon is deploying ConnectX-8 in GB300s in many cases. Also, most hyperscalers are deploying their in-house DPU instead of Bluefield-3 for frontend networking. The power delivery module and management modules in GB300 are also highly customized as every customer has differing preferences for these modules. As such, the front half of GB300 is highly customizable with each hyperscalers’ design differing from each other significantly.
Atomic Claim 662/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0708
Claim: 例如，在部分 racks 中，Amazon 也會在許多 GB300 部署採用 ConnectX-8。
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Atomic Claim 663/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0709
Claim: 此外，多數 hyperscalers 在 frontend networking 會部署自研 DPU，而非 Bluefield-3。
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Atomic Claim 664/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0710
Atomic Claim 665/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0711
Claim: 因此，GB300 前半部具有高度 customization，不同 hyperscalers 的設計差異很大。
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
For VR NVL72, although some level of customization is still available, there are a lot more limitations on the form factor. Given the modular and the cableless design of VR NVl72, the customized modules at the front of the chassis must match the form factor and dimension of Nvidia’s reference design. The modules available for customization are power delivery, Bluefield-4, and management modules. We expect most hyperscaler customers to adopt their in-house DSP instead of Bluefield-4. Given the limitation on form factor and dimensions, hyperscalers are redesigning the board layout and module form factor of their in-house DPU to match that of Bluefield-4. For the power delivery modules and management, some customers are also looking to combine them. Amazon does have a JBOK / Nitro Box NIC version for VR NVL72
Atomic Claim 666/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0712
Atomic Claim 667/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0713
Claim: 由於 VR NVl72 採 modular 與 cableless design，chassis 前方的 customized modules 必須符合 Nvidia reference design 的 form factor 與 dimensions。
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Atomic Claim 668/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0714
Claim: 可客製化的 modules 包含 power delivery、Bluefield-4 與 management modules。
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Atomic Claim 669/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0715
Claim: SemiAnalysis 預期多數 hyperscaler customers 會採自研 DSP，而不是 Bluefield-4。
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Atomic Claim 670/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0716
Claim: 受 form factor 與 dimensions 限制，hyperscalers 正重新設計自研 DPU 的 board layout 與 module form factor，使其符合 Bluefield-4。
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Atomic Claim 671/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0717
Atomic Claim 672/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0718
Assembly Automation and Logistics
At CES 2026, Jensen mentioned that with the streamlined cableless design and automation assembly process, compute tray assembly time has significantly reduced from 2 hours to 5 minutes from Blackwell to Rubin. There are only three L10 level compute tray assembly partners with automation capability for the Rubin platform – Foxconn, Quanta, and Wistron.
Atomic Claim 673/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0719
Claim: Jensen 在 CES 2026 表示，透過簡化的 cableless design 與 automated assembly process，從 Blackwell 到 Rubin，compute tray assembly time 已由 2 小時大幅縮短至 5 分鐘。
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Atomic Claim 674/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0720
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
At L6, board level PCBA, Wistron and Foxconn are the main supplier of Blackwell and Rubin. For L10, Blackwell had lots of different compute tray manufacturers as they buy the Bianca boards from Nvidia to sell to their clients. For Rubin, there are only three suppliers that have the capability to do automation of Rubin compute tray. For smaller ODM or OEM, they either have their compute tray made at the three automation suppliers mentioned above or they will do it in-house without automation. Although not as efficient, compute tray assembly without automation should be much easier compared to Blackwell as well given the seamless modular design. Then at L11, the various ODMs/OEMs assemble the compute tray into the rack.
Atomic Claim 675/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0721
Atomic Claim 676/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0722
Claim: 在 L10 階段，Blackwell 有許多不同 compute tray manufacturers，因它們向 Nvidia 購買 Bianca boards 再出售給客戶。
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Atomic Claim 677/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0723
Claim: Rubin 則只有 3 家 suppliers 具備 Rubin compute tray automation 能力。
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Atomic Claim 678/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0724
Claim: 較小型 ODM／OEM 可以選擇由前述三家 automation suppliers 製造 compute tray，或自行在沒有 automation 的情況下組裝。
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Atomic Claim 679/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0725
Claim: 雖然效率較低，但受 seamless modular design 幫助，沒有 automation 的 compute tray assembly 也應比 Blackwell 容易許多。
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Atomic Claim 680/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0726
Claim: 到了 L11，各 ODM／OEM 再把 compute tray 組裝進 rack。
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VR NVL72 TCO: BoM and Power Budget Analysis
The VR NVL72 Component BoM and Power Budget Model ↗ provides a detailed analysis on the BoM and the Power Budget of the rack system.
Atomic Claim 681/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0727
Source: VR NVL72 Component BoM and Power Budget Model ↗
The VR NVL72 is more expensive on a per-GPU capital cost basis, ~45% higher vs GB300s and ~14-15% higher vs the MI4XX given a higher server cost on a per GPU basis. This results in a higher Capital Cost of Ownership (TCO). For example VR NVL 72 Hyperscaler Arista has a capital cost of 2.86 per hour per GPU over a 4 year useful life. Our TCO Model runs on a 4y useful life for the purpose of calculating capital cost per hour to reflect a conservative business case, but most Neoclouds and Hyperscalers will use a 5-6y depreciation period and we think it is best to look at EBIT margins using this depreciation period. Our preferred yardstick is Project IRR, which is agnostic to the chosen depreciation period.
Atomic Claim 682/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0728
Atomic Claim 683/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0730
Claim: 例如，VR NVL72 部署於 Hyperscaler、使用 Arista networking 時，在 4 年 useful life 下，每顆 GPU 每小時 capital cost 為 3.28 美元；MI4XX Hyperscaler 則為 2.86 美元。
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Atomic Claim 684/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0732
Claim: 多數 Neoclouds 與 Hyperscalers 會採 5–6 年 depreciation period；SemiAnalysis 認為評估 EBIT margin 時應使用這種折舊期間。
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However, one advantage for Nvidia’s VR SOCAMM option is that NVIDIA directly procures memory, allowing them to negotiate long-term agreements, volume-preferential terms with memory suppliers and most importantly, VVIP pricing. We think this will shield end customers from spikes in memory costs as we outline in our AI server apocalypse note ↗, and is another example of how, as the Central Bank of AI ↗, Nvidia is effectively hedging DRAM prices for all of its customers.
Atomic Claim 685/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0736
Atomic Claim 686/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0734
Claim: Nvidia VR SOCAMM option 的一項優勢，是 NVIDIA 直接採購 memory，因此能與 memory suppliers 談 long-term agreements、volume-preferential terms，以及最重要的 VVIP pricing。
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By contrast, AMD is much more exposed to DRAM price increases as it has about double the amount of DRAM, with about 55 TB per rack of LPDDR5 and 55 TB per rack of DDR5. For the AMD’s Helios rack scale system, AMD sells the GPU/board and does procure the LPDDR5 memory, but it does not procure DDR5 DRAM for rack compute trays; rack assemblers/ODMs source and integrate DDR5 memory. This leaves buyers of AMD’s racks more exposed because AMD is only able to potentially “hedge” the LPDDR5 portion via long-term contracts leaving the DDR5 portion completely exposed. Having double the DRAM content also nearly doubles the overall exposure.
Atomic Claim 687/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0739
Atomic Claim 688/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0738
Atomic Claim 689/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0737
Atomic Claim 690/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0740
Atomic Claim 691/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0741
Atomic Claim 692/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0742
Atomic Claim 693/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0743
Atomic Claim 694/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0744
Helios memory costs are more likely to be passed through or re-priced by assemblers and therefore exhibit greater hikes in a memory upcycle. Therefore, we model lower memory price hikes for VR and GB compared to MI4XX below. Our MI400 rack assumptions reflect 6.77/GB for Nvidia, embedding volume discount structures vs the market contract price of $10.63/GB but reflecting the slack of volume economics vs NVIDIA.
Atomic Claim 695/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0746
Atomic Claim 696/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0747
Our AI Memory Model ↗ expects significant increases in LPDDR5 and DDR5 contract prices into 2Q26 and beyond and we expect to make further revisions higher in total server capex.
Atomic Claim 697/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0748
Atomic Claim 698/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0749
Atomic Claim 699/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0750
NVIDIA’s 2300W configuration represents the Max-P configuration, while the efficiency optimized Max-Q configuration runs at 1800W. Regardless of which configuration Nvidia claims both can hit the same peak clocks and therefore achieve marketed 50 PFLOPS FP4 performance. While the underlying hardware is the same, the TCO implications are due to operating costs from different levels of power consumption.
Atomic Claim 700/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0751
Atomic Claim 701/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0752
Atomic Claim 702/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0753
Below we share detailed numbers on cost of servers, storage, networking, etc as well as what Nvidia plans to do with Groq.
Atomic Claim 703/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0755
Source: SemiAnalysis AI TCO Model ↗
Source: SemiAnalysis AI TCO Model ↗
Operating costs are similar for VR Max-P vs MI4XX given their comparable chip TDPs and given that most operating costs scale with respect to IT power requirements.
Atomic Claim 704/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0756
VR Max-Q on the other hand, exhibits lower Operating costs relative to MI4XX given the lower chip TDP. For example a VR NVL 72 cluster deployed at a Hyperscaler with Arista networking would have a operating cost of $0.75 per gpu per hour, representing ~20% lower costs vs MI4XX deployed with a Hyperscaler with the same Arista networking. This highlights the advantages of the Max-Q configuration, particularly from an operating cost perspective, as the lower power TDP reduces rack-level power density for a meaningful cost savings over time.
Atomic Claim 705/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0757
Atomic Claim 706/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0758
Claim: 例如 VR NVL72 cluster 部署在 Hyperscaler、使用 Arista networking 時，每顆 gpu 每小時 operating cost 約 0.75 美元，約比同樣使用 Arista networking 的 MI4XX Hyperscaler 低 20%。
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Atomic Claim 707/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0759
Claim: 這凸顯 Max-Q configuration 在 operating cost 上的優勢；較低 power TDP 可降低 rack-level power density，長期帶來有意義的成本節省。
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Source: SemiAnalysis AI TCO Model ↗
Source: SemiAnalysis AI TCO Model ↗
The MI4XX currently has a performance per TCO advantage based on marketed dense FLOPS over VR. VR has a higher TCO per GPU compared to MI4XX, yet VR marketed PFLOPs are lower vs MI4XX resulting in a TCO per PFLOP disadvantage for the VR vs MI4XX.
Atomic Claim 708/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0760
Atomic Claim 709/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0761
NVIDIA is offering sparsity for FP4, marketing 50 PFLOPS of FP4, while AMD has opsted to remove sparsity support since CDNA4 for inference dtypes. Harnessing the 50 PFLOPS sparse vs 35 PFLOPS dense drops the cost per perf in units of $/hr per Marketed PFLOP by 35% – a valid comparison if AI Labs can indeed successfully harness Sparse FP4 on the VR NVL72.
Atomic Claim 710/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0762
Atomic Claim 711/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0763
Atomic Claim 712/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0764
As always, one caveat is that this comparison is done based on a marketed dense PFLOP basis. Effective dense PFLOP (i.e. the real world chip throughput) can differ based on Model Flops Utilization % (MFU), and in general we have seen NVIDIA chip operate at a higher MFU % vs AMD chips, suggesting that performance per TCO based on effective dense PFLOPs could be better for NVIDIA systems vs AMD – however, MFU is dependent on actual workloads with no one-size-fits-all MFU % that is consistently applicable to either systems.
Atomic Claim 713/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0766
Claim: Effective dense PFLOP，也就是真實世界 chip throughput，會隨 Model Flops Utilization（MFU）而不同。
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Atomic Claim 714/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0767
Indeed, real world use of FP4 Sparsity will probably not reach 50 PFLOPS but it will probably deliver better effective FLOPs than FP4 Dense, but we have yet to evaluate what that real-world performance could be. Running VR NVL72 on 1800W would probably mean lower FP4 Sparse FLOPs than on 2300W.
Atomic Claim 715/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0768
Atomic Claim 716/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0769
Atomic Claim 717/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0770
Source: SemiAnalysis AI TCO Model ↗
Source: SemiAnalysis AI TCO Model ↗
Inference throughput too can diverge materially from marketed peak FLOPS, meaning spec-sheet compute does not directly translate into real-world token generation performance. While the B300 is rated at 4,500 Dense FP8 TFLOPs versus 5,000 Dense FP8 TFLOPs for MI355, implying a 10% theoretical compute disadvantage and with same marketed memory bandwidth of 8TB/s measured inference token throughput from our InferenceX ↗ benchmarks shows B300 delivering roughly 6.3x the performance at 100 interactivity for Deepseek R1, using 8k input tokens and 1k output tokens.
Atomic Claim 718/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0772
Atomic Claim 719/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0773
Atomic Claim 720/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0774
Atomic Claim 721/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0775
Atomic Claim 722/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0776
Claim: InferenceX 在 8k input、1k output tokens、100 interactivity 的 Deepseek R1 測試中，測得 B300 performance 約為對手的 6.3 倍。
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Given that total cost of ownership is only 1.75x higher, this results in a superior performance-per-TCO profile for B300 despite the more modest marketed figures. Such a wildly different result despite very similar specs underscores that real world performance is not dictated by peak FLOPS or memory bandwidth alone. Software and network capabilities are also major factors that contribute to training and token throughput in real workloads.
Atomic Claim 723/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0777
Rubin and MI4XX will ship with new microarchitectures, real world performance is especially difficult to predict without and benchmarking like we do with InferenceX.
Atomic Claim 724/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0780
Claim: Rubin 與 MI4XX 都會搭載新 microarchitecture，因此若沒有像 InferenceX 這樣的 benchmark，真實世界 performance 特別難預測。
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Notably, both operating modes share identical memory bandwidth specifications at 8TB/s. Yet, despite the parity in memory bandwidth inference performance still diverges materially.
Source: SemiAnalysis InferenceX ↗
Groq LPU Decode Rack
Since Nvidia acquired Groq entered into a licensing agreement for Groq’s technology and hired Groq’s key people December 2025, speculation has brewed on how exactly Nvidia will implement Groq’s technology. We believe that Nvidia will introduce a new LPU rack at GTC 2026. The LPU rack is designed to be used alongside Nvidia GPUs for inference.
Atomic Claim 725/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0783
Atomic Claim 726/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0784
Atomic Claim 727/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0785
With CPX being designed specifically for inference pre-fill, the LPU system is designed for inference decode given the LPU’s emphasis on higher bandwidth SRAM. This comes at the expense of total throughput so this LPU decode system could be positioned at serving requests that require very high tokens per second per user, with the user paying much higher $/token to compensate for higher cost to serve.
Atomic Claim 728/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0786
Atomic Claim 729/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0787
Atomic Claim 730/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0788
It will be designed to sit alongside Nvidia GPUs that handle decode for lower interactivity requests. We have shared more details of the system specification to Accelerator Model clients, where we highlight one part of the supply chain that could be a big beneficiary ↗.
Atomic Claim 731/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0789
Atomic Claim 732/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0790
Claim: SemiAnalysis 已向 Accelerator Model 客戶分享更多 system specification，並指出其中一個可能成為重大受益者的供應鏈環節。
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Some details we will share here is that there are 256 LPUs per rack and it is the 3rd generation Groq chip on Samsung 4nm (the 2nd generation is being skipped). We share an important supply chain detail that has an impact on growth and market share as well as topology in the Accelerator Model note. ↗
Atomic Claim 733/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0791
Atomic Claim 734/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0792
Atomic Claim 735/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0793
Atomic Claim 736/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0794
Atomic Claim 737/737 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0795
Claim: SemiAnalysis 在 Accelerator Model note 中分享一項重要供應鏈細節，該細節會影響 growth、market share 與 topology。
Frame:CLAIM_ONLY· Mode:ASSERTED· Mapping:CLAIM_ONLY
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