VR2-0550
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Networking: NVLink 6, Rubin Scale Out - Line hint:
643
Context Before
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Evidence
Let’s step through key features of Rubin’s networking and the architectures that are likely to be built around Rubin scale-up and scale-out networks
Context After
Bi-directional SerDes for Scale-Up
The doubling of bandwidth per logical GPU from NVLink 5 in GB300 NVL72 to NVLink 6 in Vera Rubin NVL72 are made possible by using a simultaneous bi-directional SerDes for the copper backplane instead of increasing the modulation or baud rate. Whereas NVLink 5 delivers 224G per electrical lane, NVLink 6.0 delivers 448G per electrical lane. Each electrical lane is one differential pair (DP) consisting of two conductors that carry equal magnitude, and opposite polarity signals.
② Atomic Claim
接下來文章逐步說明 Rubin networking 的關鍵 features，以及可能圍繞 Rubin scale-up／scale-out networks 建構的 architectures。
- Epistemic Mode:
EXPECTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"attribute": "SCALABILITY",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/Vera Rubin",
"label": "Rubin"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "接下來文章逐步說明 Rubin networking 的關鍵 features，以及可能圍繞 Rubin scale-up／scale-out networks 建構的 architectures。"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | Rubin | 04_knowledge_base/Vera Rubin |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。