VR2-0344
① SA Source
- Source: 開啟完整 SA 文章
- Section:
PCB vs Flyover Cables - Line hint:
441
Context Before
Another factor that affects signal performance is cross-talk. Given the increase in the number of I/Os per GPU, lane density in the PCB also increases. Cross-talk describes the scenario where the copper traces are too close to each other and the signal from one lane affects the signal in a neighboring lane. Some copper traces are designed for power as well. When the power lanes are too close to the signal lanes, noise from the power lanes can also modulate the signal as well.
In conclusion, insertion loss scales with signal frequency, and high-speed signal suffers more insertion loss from PCB than from fly over cables. Hence, as traditional CPU servers upgrade to higher signaling frequencies such as upgrading to newer PCIe generations, the CPU server design increases the adoption of fly over cables to compensate for insertion loss from the PCB. The alternative solution would be upgrading PCB materials, however, fly over cables are more cost effective and remain feasible for traditional server applications.
Evidence
It is critical that all the factors that contribute towards insertion loss in the PCB are mitigated, hence PCB material upgrades are necessary for VR NVL72
Context After
PCB Materials Upgrade and Area Growth
PCB content value in VR NVL72 will grow significantly compared to that of GB200/GB300. The two main drivers of this content growth are significant material upgrades and the notable increase of high-end PCB area and layers. Our VR NVL72 Component BoM and Power Budget Model ↗ has provides the $ content breakdown of high end CCL and PCB content for VR NVL72 vs GB200/GB300.
② Atomic Claim
由於必須降低 PCB 中所有造成 insertion loss 的因素，因此 VR NVL72 必須升級 PCB materials。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"attribute": "UNSPECIFIED_ATTRIBUTE",
"context_nodes": [
{
"id": "04_knowledge_base/Insertion loss",
"label": "insertion loss"
},
{
"id": "04_knowledge_base/VR NVL72",
"label": "VR NVL72"
}
],
"entity": {
"id": "04_knowledge_base/PCB",
"label": "PCB"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "由於必須降低 PCB 中所有造成 insertion loss 的因素，因此 VR NVL72 必須升級 PCB materials。"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | PCB | PCB |
| context_0 | insertion loss | 04_knowledge_base/Insertion loss |
| context_1 | VR NVL72 | 04_knowledge_base/VR NVL72 |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。