VR2-0123
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Vera - Line hint:
149
Context Before
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Evidence
Memory bus width doubled to 1024-bit and speed increased to 9600MT/s for 2.5x bandwidth, while maximum capacity tripled to 1.5TB with 8 SOCAMM modules
Context After
NVLink 6 Switch
② Atomic Claim
Memory bus width 加倍至 1024-bit、speed 提高至 9600MT/s，使 bandwidth 增加 2.5 倍；搭配 8 個 SOCAMM modules，maximum capacity 則提升 3 倍至 1.5TB。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"comparison_expression": "Memory bus width 加倍至 1024-bit、speed 提高至 9600MT/s，使 bandwidth 增加 2.5 倍；搭配 8 個 SOCAMM modules，maximum capacity 則提升 3 倍至 1.5TB。",
"entities": [
{
"id": "04_knowledge_base/SOCAMM",
"label": "SOCAMM"
}
],
"frame_type": "COMPARISON",
"metric": "BANDWIDTH",
"operator": "MULTIPLE_OF",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"1024",
"9600M",
"2.5",
"8",
"3",
"1.5TB"
],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| comparison_entity_0 | SOCAMM | SOCAMM |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。