clm_bacb8ad4140e4f409b8dbb89441b3a1e_r1

VR2-0273

① SA Source

• Source: 開啟完整 SA 文章
• Section: Compute Tray Topology
• Line hint: 369

Context Before

Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

Evidence

Instead, B200 connects to Grace CPU via C2C connection then the Grace CPU talks to the ConnectX-7 over PCIe 5

Context After

Essentially, this means ConnectX-8 has two hosts, Grace CPU and B300 GPU. This improves latency in the backend network. However, for VR NVL72, the direct connection between Rubin GPU and ConnectX-9 is reverted back to the same design as GB200, as Rubin does not have PCIe bandwidth for two Connect-9. Rubin connects to Vera via C2C link, then Vera will connect to ConnectX-9 via PCIe6 lanes.

Secondly, the local NVMe storage for Rubin has been moved to a different location from that of NVMe storage in Grace Blackwell. Previously, local NVMe storage was managed by BlueField-3. For VR NVL72, the local NVMe storage is physically on the Orchid module managed by the ConnectX-9.

② Atomic Claim

B200 先透過 C2C 連接 Grace CPU，再由 Grace CPU 透過 PCIe 5 與 ConnectX-7 溝通。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/NVIDIA B200",
        "label": "B200"
      },
      "role": "endpoint_or_system"
    },
    {
      "node": {
        "id": "04_knowledge_base/Chip-to-Chip Interconnect",
        "label": "C2C"
      },
      "role": "connected_entity"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVIDIA Grace",
        "label": "Grace CPU"
      },
      "role": "connected_entity"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe"
      },
      "role": "connected_entity"
    },
    {
      "node": {
        "id": "04_knowledge_base/ConnectX-7",
        "label": "ConnectX-7"
      },
      "role": "connected_entity"
    }
  ],
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "5",
      "7"
    ],
    "temporal_mentions": []
  },
  "relation_type": "CONNECTS_TO"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
endpoint_or_system	B200	04_knowledge_base/NVIDIA B200
connected_entity	C2C	04_knowledge_base/Chip-to-Chip Interconnect
connected_entity	Grace CPU	04_knowledge_base/NVIDIA Grace
connected_entity	PCIe	PCIe
connected_entity	ConnectX-7	ConnectX-7

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。