VR2-0131
① SA Source
- Source: 開啟完整 SA 文章
- Section:
NVLink 6 Switch - Line hint:
157
Context Before
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Evidence
The layout remains the same as NVIDIA’s previous switches, with 2 sides for IO and a central logic section crossbar and 3.6 TFlop SHARP in-network compute acceleration
Context After
ConnectX-9
② Atomic Claim
Layout 與 NVIDIA 過去的 switches 相同，兩側為 I/O，中間為 logic section crossbar，並配置 3.6 TFlop SHARP in-network compute acceleration。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"comparison_expression": "Layout 與 NVIDIA 過去的 switches 相同，兩側為 I/O，中間為 logic section crossbar，並配置 3.6 TFlop SHARP in-network compute acceleration。",
"entities": [
{
"id": "02_companies/NVDA",
"label": "NVIDIA"
}
],
"frame_type": "COMPARISON",
"metric": "COMPUTE_PERFORMANCE",
"operator": "EQUAL_TO",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"3.6"
],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| comparison_entity_0 | NVIDIA | NVDA |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。