VR2-0058
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Rubin - Line hint:
109
Context Before
Doubling Tensor Core width in the SM to 32768 FP4 MACs/clock
Evidence
Increasing clock speed 25% from 1.90GHz to 2.38GHz
Context After
Additionally, Nvidia claims up to an effective 50 PFLOPS of FP4 performance can be achieved with an updated 3rd generation Transformer Engine that replaces 2:4 structured sparsity from prior generations. We will detail this architectural feature for Rubin below.
Notably, the Tensor core width doubling only applies to FP4 and FP8, with BF16 and TF32 remaining the same as Blackwell, resulting in performance scaling only 1.6x of Blackwell. This architectural decision reflects NVIDIA’s belief that most training and inference workloads will move away from TF32 and BF16 and onto FP8 and FP4.
② Atomic Claim
關於 Rubin：Clock speed 提高 25%，由 1.90GHz 升至 2.38GHz。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "CLOCK_SPEED",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/Vera Rubin",
"label": "Rubin"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"25%",
"1.90GHz",
"2.38GHz"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"25%",
"1.90GHz",
"2.38GHz"
],
"value_text": "關於 Rubin：Clock speed 提高 25%，由 1.90GHz 升至 2.38GHz。"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | Rubin | 04_knowledge_base/Vera Rubin |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。