clm_ba13a934eb884404a03cbb8a0560faa6_r1

VR2-0593

① SA Source

• Source: 開啟完整 SA 文章
• Section: GB200 Hardware Architecture - Component Supply Chain & BOM
• Line hint: 717

Context Before

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

Evidence

The number of lanes between the PaladinHD2 connectors and the NVLink Switch also creates complexity for PCB design

Context After

We have more details on the switch tray and various components in the VR NVL72 Component BoM and Power Budget Model ↗.

Zooming out, backplane copper cables are used to connect NVLink Switch trays to the GPU trays for the VR NVL72 system. Although the bandwidth doubles, with bi-directional SerDes, the number of cables required does not change from the GB300 backplane generation to the Vera Rubin NVL72 backplane generation. The number of connectors and the number of DPs per connector also does not change from Grace Blackwell NVL72 to VR NVL72.

② Atomic Claim

PaladinHD2 connectors 與 NVLink Switch 之間的 lane 數量，也增加 PCB design 複雜度。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "additional_nodes": [],
  "frame_type": "RELATION",
  "object": {
    "id": "04_knowledge_base/PCB",
    "label": "PCB"
  },
  "predicate": "CONNECTS_TO",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "subject": {
    "id": "04_knowledge_base/NVLink",
    "label": "NVLink"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
subject	NVLink	NVLink
object	PCB	PCB

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。