VR2-0316
① SA Source
- Source: 開啟完整 SA 文章
- Section:
PCB vs Flyover Cables - Line hint:
419
Context Before
PCB vs Flyover Cables
Nevertheless, it is still challenging to drive a PCIe Gen6 signal over around 500mm of PCB distance from the Strata Module to the front of the Orchid Module. In addition to having high quality SerDes, proper signal integrity is still achievable by upgrading PCB materials.
Evidence
As SerDes rates increase, high-speed channels become increasingly constrained by insertion loss introduced by PCB traces, vias, dielectric materials and conductor roughness
Context After
Source: Doosan, SemiAnalysis
② Atomic Claim
隨 SerDes rate 提高，高速 channels 越來越受到 PCB traces、vias、dielectric materials 與 conductor roughness 所造成的 insertion loss 限制。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"attribute": "UNSPECIFIED_ATTRIBUTE",
"context_nodes": [
{
"id": "04_knowledge_base/PCB",
"label": "PCB"
},
{
"id": "04_knowledge_base/Via",
"label": "vias"
},
{
"id": "04_knowledge_base/Insertion loss",
"label": "insertion loss"
}
],
"entity": {
"id": "04_knowledge_base/SerDes",
"label": "SerDes"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "隨 SerDes rate 提高，高速 channels 越來越受到 PCB traces、vias、dielectric materials 與 conductor roughness 所造成的 insertion loss 限制。"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | SerDes | SerDes |
| context_0 | PCB | PCB |
| context_1 | vias | Via |
| context_2 | insertion loss | 04_knowledge_base/Insertion loss |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。