VR2-0591
① SA Source
- Source: 開啟完整 SA 文章
- Section:
GB200 Hardware Architecture - Component Supply Chain & BOM - Line hint:
711
Context Before

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Evidence
Context After

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
② Atomic Claim
因 bidirectional SerDes 每 lane 只需 1 DP,因此任一 connector 與任一 switch 間共有 18 DPs,每個 connector 共 72 DPs,與前代 NVLink 5 Switch Tray 相同。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"comparison_expression": "因 bidirectional SerDes 每 lane 只需 1 DP,因此任一 connector 與任一 switch 間共有 18 DPs,每個 connector 共 72 DPs,與前代 NVLink 5 Switch Tray 相同。",
"entities": [
{
"id": "04_knowledge_base/SerDes",
"label": "SerDes"
},
{
"id": "04_knowledge_base/NVLink5",
"label": "NVLink 5"
}
],
"frame_type": "COMPARISON",
"metric": "CONNECTOR_COUNT",
"operator": "EQUAL_TO",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"1",
"18",
"72",
"5 S"
],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
⑤ Human Review
請在 Properties 逐項確認:
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。