VR2-0292
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Compute Tray Cableless Design - Line hint:
387
Context Before
All of these modules in the VR NVL72 compute tray, while not exactly the same, are found in the compute tray of GB200/300. The only difference is the midplane module as it is a new component introduced to eliminate internal cables form the compute tray. Also, the modules at the front of the chassis (daughter modules) are much longer than their equivalent in Blackwell to connect the signal from the midplane to the front I/O ports via PCB. In the sections below we will discuss the cableless design, the changes in thermal design, and the changes in mechanical design in the compute tray.
Compute Tray Cableless Design
Evidence
As mentioned above the VR NVL72 compute tray is designed around the cableless concept. As we discussed in our PCB Supercycle Core Research note in August last year ↗ as well as our recent Core Research note on Amphenol’s AI Content ↗, there are two reasons for this design. First, flyover cables present multiple different points of failure as they can easily be damaged during assembly. Second, the high-density design of VR NVL72 leaves limited space for cables to be routed.
Context After
Replacing Internal Cables with Board-to-Board Connectors
For the GB200/300, the most valuable cable that is exclusively supplied by Amphenol is the DensiLink OverPass cable set within the compute tray. This cable provides the ethernet connection between the CX-7/8 NIC and the OSFP cages. However, this cable is extremely vulnerable to scratches and damage of the cable termination during assembly, thereby creating many points of failure. There are also several other lower-end PCIe cables in use (MCIO and SlimSAS) that also suffer from the same points of failure. These cables involve many other suppliers as well – complicating procurement and vendor management. Given the delicate nature of the cable, workers must be extremely careful while placing the cables in a very dense and compact chassis, which prolongs assembly time.
② Atomic Claim
SemiAnalysis 去年 8 月的 PCB Supercycle Core Research note，以及近期關於 Amphenol’s AI Content 的 Core Research note，都指出此設計有兩個主要原因。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
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"frame_type": "RELATION",
"object": {
"id": "02_companies/APH",
"label": "Amphenol’s"
},
"predicate": "DESIGNS",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"8"
],
"temporal_mentions": []
},
"subject": {
"id": "04_knowledge_base/PCB",
"label": "PCB"
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}④ Canonical Entity Mapping
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。