clm_4b9db025d14d4ee685254af2e505aa28_r1

VR2-0018

① SA Source

• Source: 開啟完整 SA 文章
• Section: Vera Rubin – Extreme Co-Design: An Evolution from Grace Blackwell Oberon
• Line hint: 27

Context Before

Source: Nvidia

For the Vera Rubin platform, Nvidia is asserting even more control over the system and rack level design. Rack scale integration and assembly have become more challenging, as every component is being pushed to the limit, whilst also optimizing for cost efficiency. VR NVL72 has a much more holistic design with a modular approach compared to Grace Blackwell for the purpose of integration efficiency and throughput.

Evidence

Nvidia offers the best accelerator, a SOTA scale up switch, the best NIC, and one of the best Ethernet networking switch, and a much improved purpose-designed CPU

Context After

In the sections below, we will discuss the 6 silicon products of the Vera Rubin platform at the silicon level. Then, we will discuss the rack and compute tray evolution from Grace Blackwell to Vera Rubin from the design perspective and the implication to components: cables, connectors, PCB, thermal, mechanical, and power.

Next, we will discuss the major networks of the VR NVL72 system, namely the scale up NVLink 6 network and the backend scale out network. We will discuss the logistical implications of much more limited hyperscaler customisation and the assembly supplier landscape.

② Atomic Claim

Nvidia 提供領先的 accelerator、SOTA scale-up switch、領先的 NIC、頂尖等級的 Ethernet networking switch，以及大幅改良的 purpose-designed CPU。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "02_companies/NVDA",
        "label": "Nvidia"
      },
      "role": "subject"
    },
    {
      "node": {
        "id": "04_knowledge_base/NIC",
        "label": "NIC"
      },
      "role": "design_target_or_context"
    },
    {
      "node": {
        "id": "04_knowledge_base/Ethernet",
        "label": "Ethernet"
      },
      "role": "design_target_or_context"
    },
    {
      "node": {
        "id": "04_knowledge_base/CPU",
        "label": "CPU"
      },
      "role": "design_target_or_context"
    }
  ],
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "DESIGNS"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
subject	Nvidia	NVDA
design_target_or_context	NIC	NIC
design_target_or_context	Ethernet	Ethernet
design_target_or_context	CPU	CPU

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。