VR2-0770
① SA Source
- Source: 開啟完整 SA 文章
- Section:
VR NVL72 TCO: BoM and Power Budget Analysis - Line hint:
971
Context Before
NVIDIA is offering sparsity for FP4, marketing 50 PFLOPS of FP4, while AMD has opsted to remove sparsity support since CDNA4 for inference dtypes. Harnessing the 50 PFLOPS sparse vs 35 PFLOPS dense drops the cost per perf in units of $/hr per Marketed PFLOP by 35% – a valid comparison if AI Labs can indeed successfully harness Sparse FP4 on the VR NVL72.
As always, one caveat is that this comparison is done based on a marketed dense PFLOP basis. Effective dense PFLOP (i.e. the real world chip throughput) can differ based on Model Flops Utilization % (MFU), and in general we have seen NVIDIA chip operate at a higher MFU % vs AMD chips, suggesting that performance per TCO based on effective dense PFLOPs could be better for NVIDIA systems vs AMD – however, MFU is dependent on actual workloads with no one-size-fits-all MFU % that is consistently applicable to either systems.
Evidence
Context After
Source: SemiAnalysis AI TCO Model ↗
② Atomic Claim
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"comparison_expression": "讓 VR NVL72 運行在 1,800W，很可能會比 2,300W 時有較低的 FP4 Sparse FLOPs。",
"entities": [
{
"id": "04_knowledge_base/VR NVL72",
"label": "VR NVL72"
},
{
"id": "04_knowledge_base/FP4",
"label": "FP4"
}
],
"frame_type": "COMPARISON",
"metric": "COMPUTE_PERFORMANCE",
"operator": "LESS_THAN",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"1,800W",
"2,300W"
],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| comparison_entity_0 | VR NVL72 | 04_knowledge_base/VR NVL72 |
| comparison_entity_1 | FP4 | FP4 |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。