clm_4444e755b3ae455c9a8059c4f5a7ef8e_r1

VR2-0079

① SA Source

• Source: 開啟完整 SA 文章
• Section: Rubin
• Line hint: 119

Context Before

On the memory front, the move to HBM4 means double the bus width per stack, running at 10.8 GT/s for 22TB/s total bandwidth or 2.75x Blackwell at the same 288GB capacity as GB300. Memory bandwidth has been upgraded significantly from the original 13TB/s advertised at GTC 2025. In order to catch up to AMD MI450’s memory bandwidth, Nvidia requested much higher HBM4 pin speeds from the DRAM suppliers - well above the speeds that was in the JEDEC specification for HBM4.

While Nvidia is targeting 22TB/s, we understand that memory suppliers are having challenges hitting Nvidia’s requirements and we see it likely that initial shipments will come in slightly below at closer to 20TB/s. We have discussed the implications to SK Hynix, Samsung, and Micron extensively for Accelerator and HBM model subscribers. ↗ Micron is well behind Samsung and Hynix and we believe they are effectively out of the picture for Rubin HBM4. ↗ We have more details on qualifications and pin speeds in the Accelerator and HBM model ↗

Evidence

The NVLink-C2C chiplet houses the SerDes for the Vera CPU connection, doubled in bandwidth to 1.8TB/s

Context After

Transistor count has climbed 60% to 336 billion.

A notable omission from Rubin is the mention of Sparse FLOPs. In previous generations, 2:4 structured sparsity was used to double marketing FLOPs numbers. However, adoption was minimal especially at low precisions due to accuracy losses from the rigid sparsity structure forcing half of the values to be zero. Programmers basically ignored structured sparsity as it was not useful, which caused hardware designs to change as well. Blackwell Ultra GB300 added 50% more dense FP4 while keeping sparse FP4 FLOPs the same, while AMD’s MI355X stopped supporting structured sparsity on MXFP8, MXFP6 and MXFP4 formats to save silicon area.

② Atomic Claim

NVLink-C2C chiplet 內含連接 Vera CPU 的 SerDes，其 bandwidth 加倍至 1.8TB/s。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "comparison_expression": "NVLink-C2C chiplet 內含連接 Vera CPU 的 SerDes，其 bandwidth 加倍至 1.8TB/s。",
  "entities": [
    {
      "id": "04_knowledge_base/NVLink-C2C",
      "label": "NVLink-C2C"
    },
    {
      "id": "04_knowledge_base/Chiplet architecture",
      "label": "chiplet"
    },
    {
      "id": "04_knowledge_base/NVIDIA Vera CPU",
      "label": "Vera CPU"
    },
    {
      "id": "04_knowledge_base/SerDes",
      "label": "SerDes"
    }
  ],
  "frame_type": "COMPARISON",
  "metric": "BANDWIDTH",
  "operator": "MULTIPLE_OF",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "1.8TB/s"
    ],
    "temporal_mentions": []
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
comparison_entity_0	NVLink-C2C	NVLink-C2C
comparison_entity_1	chiplet	04_knowledge_base/Chiplet architecture
comparison_entity_2	Vera CPU	04_knowledge_base/NVIDIA Vera CPU
comparison_entity_3	SerDes	SerDes

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。