2026-02-25_vera-rubin-extreme-co-design-an-evolution

Phase C–E 審查快照

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SA Article Coverage Review · 2026-02-25_vera-rubin-extreme-co-design-an-evolution

Coverage Summary

• Source: 開啟原始 SA 文章
• Atomic Claims: 1074
• Source blocks: 494
• Blocks with ≥1 Atomic Claim: 238
• Blocks without Atomic Claim: 256
• Unplaced Claims: 0

Coverage Review

本版依已封存的 Phase C–E 審查結果產生；Claim 按正式 Evidence 位置插入。
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Missing Claim Notes

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SA Full Text + Translation + Atomic Claims

Vera Rubin – Extreme Co-Design: An Evolution from Grace Blackwell Oberon

At CES 2026, Nvidia officially announced in detail all 6 Rubin platform products: the Rubin GPU, Vera CPU, NVLink 6 Switch, ConnectX-9, BlueField-4, and Spectrum-6. VR NVL72 is the second generation of Nvidia’s rack scale Oberon architecture that takes the stage. With competition catching up on rack scale game, Trainium 3 in the Gen2 UltraServer, AMD MI450X Helios Racks, and Google’s TPU which was at rack scale even before GB200 ↗, Nvidia answers with “extreme co-design” supremacy. With extreme co-design, Nvidia takes rack scale integration to the next level. Rack system becomes a unit of compute, a single distributed accelerator, and Nvidia designs the system.

CES 2026，Nvidia 正式完整公布 Rubin platform 六大產品：Rubin GPU、Vera CPU、NVLink 6 Switch、ConnectX-9、BlueField-4、Spectrum-6。VR NVL72 是 Nvidia rack-scale Oberon architecture 的第二代。當 Trainium 3 Gen2 UltraServer、AMD MI450X Helios Rack，以及甚至早在 GB200 之前就已做到 rack scale 的 Google TPU ↗ 都開始追上來，Nvidia 的回答是『extreme co-design』。透過 extreme co-design，Nvidia 把 rack-scale integration 再往前推一層：整個 rack system 變成一個 compute unit、一顆 distributed accelerator，而整套 system 都由 Nvidia 自己設計。

Atomic Claim 1/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT03

Claim: At CES 2026, Nvidia officially detailed NVLink 6 Switch as one of the six Rubin platform products.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 2/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT05

Claim: At CES 2026, Nvidia officially detailed BlueField-4 as one of the six Rubin platform products.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 3/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT04

Claim: At CES 2026, Nvidia officially detailed ConnectX-9 as one of the six Rubin platform products.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 4/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0003::SPLIT03

Claim: Google TPU was at rack scale even before GB200.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 5/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT06

Claim: At CES 2026, Nvidia officially detailed Spectrum-6 as one of the six Rubin platform products.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 6/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0001::SPLIT01

Claim: At CES 2026, Nvidia officially detailed Rubin GPU as one of the six Rubin platform products.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 7/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0005

Claim: 關於 Rubin：Rack system 被視為一個 compute unit，也就是單一 distributed accelerator。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 8/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0006

Claim: Nvidia 負責設計整個 system。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 9/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0003::SPLIT04

Claim: Nvidia answers the catching-up rack-scale competition with extreme co-design.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 10/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0002

Claim: VR NVL72 是 Nvidia rack-scale Oberon architecture 的第二代。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 11/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0002

Claim: Nvidia 發布 Vera CPU。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 12/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0003::SPLIT01

Claim: Trainium 3 is deployed in the Gen2 UltraServer as a rack-scale competitor.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 13/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0004

Claim: 透過 extreme co-design，Nvidia 將 rack-scale integration 推進到更高層級。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 14/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0003::SPLIT02

Claim: AMD MI450X Helios Racks are a rack-scale competitor.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia

For the Vera Rubin platform, Nvidia is asserting even more control over the system and rack level design. Rack scale integration and assembly have become more challenging, as every component is being pushed to the limit, whilst also optimizing for cost efficiency. VR NVL72 has a much more holistic design with a modular approach compared to Grace Blackwell for the purpose of integration efficiency and throughput.

Vera Rubin platform 上，Nvidia 對 system 與 rack-level design 的控制更進一步。Rack-scale integration、assembly 越來越困難，因為每個 component 都被推到極限，同時還得追求 cost efficiency。相較 Grace Blackwell，VR NVL72 採更 holistic、modular 的 design，目的就是提高 integration efficiency 與 throughput。

Atomic Claim 15/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0008

Claim: Vera Rubin rack-scale integration and assembly become more challenging as components are pushed to their limits while cost efficiency must also be optimized.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 16/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0009

Claim: 為提升 integration efficiency 與 throughput，VR NVL72 相較 Grace Blackwell 採用更 holistic、modular 的設計方式。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 17/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0007

Claim: 對 Vera Rubin platform，Nvidia 對 system 與 rack-level design 掌握更多控制權。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Nvidia’s competitiveness strengthens with its extreme co-design supremacy. It is the only player with the best in class or close to the best in class silicon product offerings for all the major silicon contents in an Nvidia trail-blazed AI server system design. Nvidia offers the best accelerator, a SOTA scale up switch, the best NIC, and one of the best Ethernet networking switch, and a much improved purpose-designed CPU ↗. No other competitors have such a complete suite of integrated silicon products.

Nvidia 的 competitiveness 因 extreme co-design 優勢進一步強化。它是目前唯一一家，在自己開創的 AI server system design 裡，幾乎所有主要 silicon content 都擁有 best-in-class 或接近 best-in-class product 的公司。Nvidia 有最強 accelerator、SOTA scale-up switch、最強 NIC、頂級 Ethernet networking switch，以及大幅改善、專為 AI system 設計的 CPU ↗。沒有其他 competitor 擁有這麼完整的一整套 integrated silicon portfolio。

Atomic Claim 18/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0012::SPLIT03

Claim: SemiAnalysis assesses: Nvidia 提供 best-in-class NIC。
Frame: NARY_RELATION · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 19/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0012::SPLIT01

Claim: SemiAnalysis assesses: Nvidia 提供 best-in-class accelerator。
Frame: CLAIM_ONLY · Mode: ATTRIBUTED · Mapping: CLAIM_ONLY
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Atomic Claim 20/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0014

Claim: SemiAnalysis assesses: 原文認為，沒有其他競爭者具備如此完整的一套 integrated silicon products。
Frame: CLAIM_ONLY · Mode: ATTRIBUTED · Mapping: PARTIAL
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Atomic Claim 21/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0010

Claim: SemiAnalysis assesses: Nvidia 的 competitiveness 因 extreme co-design 優勢而進一步增強。
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 22/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0011

Claim: SemiAnalysis assesses: 原文認為，Nvidia 是唯一在其 AI server system 所有主要 silicon content 上，都能提供 best-in-class 或接近 best-in-class silicon product 的業者。
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 23/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0012::SPLIT02

Claim: SemiAnalysis assesses: Nvidia 提供 SOTA scale-up switch。
Frame: CLAIM_ONLY · Mode: ATTRIBUTED · Mapping: CLAIM_ONLY
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Atomic Claim 24/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0013::SPLIT02

Claim: SemiAnalysis assesses: Nvidia 提供大幅改善且 purpose-designed 的 CPU。
Frame: NARY_RELATION · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 25/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0013::SPLIT01

Claim: SemiAnalysis assesses: Nvidia 提供 one of the best Ethernet networking switches。
Frame: NARY_RELATION · Mode: ATTRIBUTED · Mapping: COMPLETE
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In the sections below, we will discuss the 6 silicon products of the Vera Rubin platform at the silicon level. Then, we will discuss the rack and compute tray evolution from Grace Blackwell to Vera Rubin from the design perspective and the implication to components: cables, connectors, PCB, thermal, mechanical, and power.

以下各節會先從 silicon level 拆解 Vera Rubin platform 的六項 silicon product；接著從 design 角度分析 Grace Blackwell 到 Vera Rubin 的 rack、compute tray 演進，以及對 cable、connector、PCB、thermal、mechanical、power 等 component 的影響。

Next, we will discuss the major networks of the VR NVL72 system, namely the scale up NVLink 6 network and the backend scale out network. We will discuss the logistical implications of much more limited hyperscaler customisation and the assembly supplier landscape.

接著會討論 VR NVL72 的主要 network，包括 scale-up NVLink 6 network 與 backend scale-out network，也會說明 hyperscaler customization 大幅受限之後的 logistics implication，以及 assembly supplier landscape。

Lastly, the report ends with a discussion on the TCO of the VR NVL72 system as well as the BoM and Power Budget estimate supporting the TCO analysis. Behind the paywall, we also provide readers with insight into Nvidia’s plans for their Groq IP. We will also cover some of the challenges with regards to HBM ramp for Micron, SK Hynix, and Samsung.

最後，報告會以 VR NVL72 system 的 TCO 收尾，並提供支撐 TCO analysis 的 BoM 與 Power Budget estimate。Paywall 後也會分享 Nvidia 對 Groq IP 的規劃，以及 Micron、SK Hynix、Samsung 在 HBM ramp 上面臨的部分挑戰。

Today we are also launching the VR NVL72 Component BoM and Power Budget Model ↗. It provides a system-level bill of materials and power budget analysis for the VR NVL72 system covered in this article. This is important because various vendors and their shares of the subcomponents will drive whether they are winners or losers in the $500B Rubin buildout. The downstream impacts and dislocations in the market are large. The model covers:

今天我們也同步推出 VR NVL72 Component BoM and Power Budget Model ↗，針對本文所討論的 VR NVL72 system，提供 system-level bill of materials 與 power budget analysis。這很重要，因為各 vendor 在不同 subcomponent 的供應份額，將決定誰會成為 $500B Rubin buildout 的贏家或輸家；下游影響與市場 dislocation 都非常大。Model 涵蓋：

Atomic Claim 26/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0026

Claim: SemiAnalysis 預期，各 vendor 的 subcomponent share 將影響其在原文所述 $500B Rubin buildout 中的贏家／輸家地位。
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: PARTIAL
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**Nvidia Compute Tray Content: **Strata module with Rubin GPU, Vera CPU, SOCAMM memory; BlueField-4; ConnectX-9

Nvidia Compute Tray Content：包含 Rubin GPU、Vera CPU、SOCAMM memory 的 Strata module；BlueField-4；ConnectX-9。

Atomic Claim 27/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0029

Claim: Nvidia Compute Tray content 包含 Vera CPU。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 28/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0030

Claim: Nvidia Compute Tray content 包含 SOCAMM memory。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 29/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0032

Claim: Nvidia Compute Tray content 包含 ConnectX-9。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 30/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0028

Claim: Nvidia Compute Tray content 包含搭載 Rubin GPU 的 Strata module。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 31/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0031

Claim: Nvidia Compute Tray content 包含 BlueField-4。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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**NVLink System: **NVSwitch, NVLink backplane and cabling, associated connectors, host CPU management module

NVLink System：NVSwitch、NVLink backplane 與 cabling、相關 connector、host CPU management module。

Atomic Claim 32/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0034::SPLIT02

Claim: NVLink system 包含 cabling。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 33/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0034::SPLIT01

Claim: NVLink system 包含 NVLink backplane。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 34/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0033

Claim: NVLink system 包含 NVSwitch。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 35/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0036

Claim: NVLink system 包含 host CPU management module。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 36/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0035

Claim: NVLink system 也包含相關 connectors。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Liquid Cooling Content: Coldplates, QDs, Manifolds

Liquid Cooling Content：coldplate、QD、manifold。

Atomic Claim 37/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0038

Claim: Liquid Cooling content 包含 QDs。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 38/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0037

Claim: Liquid Cooling content 包含 Coldplates。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 39/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0039

Claim: Liquid Cooling content 包含 manifolds。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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**PCB, Substrate, and Materials Content: **key system boards, ABF substrates, CCL content

PCB、Substrate、Materials Content：主要 system board、ABF substrate、CCL content。

Atomic Claim 40/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0042

Claim: PCB、Substrate 與 materials content 包含 CCL content。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 41/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0041

Claim: PCB、Substrate 與 materials content 包含 ABF substrates。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 42/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0040

Claim: PCB、Substrate 與 materials content 包含關鍵 system boards。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Connectors: Paladin HD2 Board to Board Connectors, Paladin HD2 NVLink 6.0 Connectors

Connectors：Paladin HD2 board-to-board connector、Paladin HD2 NVLink 6.0 connector。

Atomic Claim 43/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0044

Claim: Connector content 包含 Paladin HD2 NVLink 6.0 connectors。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 44/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0043

Claim: Connector content 包含 Paladin HD2 Board-to-Board Connectors。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Power Delivery Content: power shelves, busbars, VRMs, power delivery modules

Power Delivery Content：power shelf、busbar、VRM、power delivery module。

Atomic Claim 45/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0048

Claim: Power Delivery content 包含 power delivery modules。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 46/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0045

Claim: Power Delivery content 包含 power shelves。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 47/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0046

Claim: Power Delivery content 包含 busbars。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 48/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0047

Claim: Power Delivery content 包含 VRMs。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Mechanical Structure: chassis, loading mechanism, railkits, rack chassis

Mechanical Structure：chassis、loading mechanism、railkit、rack chassis。

Atomic Claim 49/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0052

Claim: Mechanical Structure 包含 rack chassis。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 50/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0051

Claim: Mechanical Structure 包含 railkits。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 51/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0049

Claim: Mechanical Structure 包含 chassis。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 52/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0050

Claim: Mechanical Structure 包含 loading mechanism。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Management modules: BMC

Management Module：BMC。

Atomic Claim 53/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0053

Claim: Management modules 包含 BMC。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Networking: Transceivers, CX-9

Networking：transceiver、CX-9。

Atomic Claim 54/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0054

Claim: Networking content 包含 transceivers。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 55/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0055

Claim: Networking content 包含 CX-9。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

Please visit this self service portal ↗ to purchase the model. Contact sales@semianalysis.com for any questions regarding the product.

如需購買 model，請前往 self-service portal ↗；產品相關問題可聯絡 sales@semianalysis.com。

Extreme Co-design: 6 Silicon Product Offerings under the Rubin Platform - Chip Floorplans & Specifications

Source: SemiAnalysis, Nvidia

Rubin’s dense FP4 and FP8 FLOPs increase by roughly ~3.5× versus GB200, while FP16 FLOPs rise by a more modest ~1.6x, underscoring NVIDIA’s continued emphasis on FP4/FP8 as the primary scaling vector. On the memory side, HBM capacity remains flat from GB300, while HBM bandwidth scales more aggressively at ~2.8x. Overall, the architecture prioritizes bandwidth and low-precision compute.

Rubin 的 dense FP4、FP8 FLOPs 相較 GB200 約提升 3.5x，FP16 FLOPs 則較溫和、約提升 1.6x，凸顯 NVIDIA 仍把 FP4／FP8 當作主要 scaling vector。Memory 方面，HBM capacity 與 GB300 相同，但 HBM bandwidth 更積極擴張、約提升 2.8x。整體 architecture 明顯優先強化 bandwidth 與 low-precision compute。

Atomic Claim 56/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0048

Claim: Rubin HBM bandwidth increases about 2.8× over Blackwell.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 57/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0056::SPLIT02

Claim: 相較 GB200，Rubin 的 FP16 FLOPs 約提升 1.6 倍。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 58/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0056::SPLIT01

Claim: 相較 GB200，Rubin 的 dense FP4 與 FP8 FLOPs 約提升 3.5 倍。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 59/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0056::SPLIT03

Claim: SemiAnalysis 認為，這些 scaling differences 顯示 NVIDIA 持續將 FP4／FP8 作為主要 scaling vector。
Frame: NARY_RELATION · Mode: INFERRED · Mapping: COMPLETE
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Atomic Claim 60/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0058

Claim: Rubin architecture prioritizes bandwidth and low-precision compute.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 61/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0047

Claim: 記憶體方面，HBM capacity 與 GB300 相同。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Source: SemiAnalysis, Nvidia

Rubin

Source: Nvidia

Rubin’s design is a logical evolution from Blackwell, with the move to a 3nm process and disaggregating I/O into chiplets while keeping the same basic structure of 2 reticle-sized dies with 8 stacks of HBM. 35 PFLOPS dense FP4 is a 3.5x improvement over Blackwell GB200, achieved by:

Rubin design 是 Blackwell 很自然的演進：製程轉向 3nm，I/O 拆成 chiplet，但核心結構仍維持兩顆 reticle-size die + 8 stack HBM。Dense FP4 達 35 PFLOPS，相較 Blackwell GB200 提升 3.5x，主要透過以下方式達成：

Atomic Claim 62/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0051

Claim: Rubin 採用 3nm 製程。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 63/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0054

Claim: Rubin 採用 8 stacks HBM。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 64/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0053

Claim: Rubin 維持 2 個 reticle-sized dies 的基本架構。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 65/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0059

Claim: Rubin 的設計是從 Blackwell 邏輯演進而來。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 66/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0052

Claim: Rubin 將 I/O 拆分至 chiplets。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 67/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0061

Claim: Rubin 35 PFLOPS dense FP4 is a 3.5x improvement over Blackwell GB200.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Increasing SM count from 160 to 224

SM 數量從 160 增加到 224。

Atomic Claim 68/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0062

Claim: 關於 Rubin：SM 數量由 160 增加至 224。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Doubling Tensor Core width in the SM to 32768 FP4 MACs/clock

把 SM 內 Tensor Core width 加倍到每 clock 32,768 個 FP4 MAC。

Atomic Claim 69/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0063

Claim: Rubin doubles Tensor Core width within an SM to 32,768 FP4 MACs per clock.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Increasing clock speed 25% from 1.90GHz to 2.38GHz

Clock speed 從 1.90GHz 提高 25% 至 2.38GHz。

Atomic Claim 70/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0064

Claim: 關於 Rubin：Clock speed 提高 25%，由 1.90GHz 升至 2.38GHz。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Additionally, Nvidia claims up to an effective 50 PFLOPS of FP4 performance can be achieved with an updated 3rd generation Transformer Engine that replaces 2:4 structured sparsity from prior generations. We will detail this architectural feature for Rubin below.

此外，Nvidia 宣稱新版第三代 Transformer Engine 能讓 FP4 effective performance 最高達 50 PFLOPS，取代前幾代使用的 2:4 structured sparsity。下面會進一步拆解 Rubin 這項 architecture feature。

Atomic Claim 71/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0065::SPLIT01

Claim: 更新後的第 3 代 Transformer Engine 取代前代採用的 2:4 structured sparsity。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 72/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0065::SPLIT02

Claim: Nvidia 宣稱，使用更新後第 3 代 Transformer Engine 可使 FP4 有效效能最高達 50 PFLOPS。
Frame: NARY_RELATION · Mode: ATTRIBUTED · Mapping: COMPLETE
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Notably, the Tensor core width doubling only applies to FP4 and FP8, with BF16 and TF32 remaining the same as Blackwell, resulting in performance scaling only 1.6x of Blackwell. This architectural decision reflects NVIDIA’s belief that most training and inference workloads will move away from TF32 and BF16 and onto FP8 and FP4.

值得注意的是，Tensor Core width 加倍只適用 FP4、FP8；BF16、TF32 則與 Blackwell 相同，因此這兩種 precision 的 performance 只約為 Blackwell 的 1.6x。這反映 NVIDIA 的判斷：未來大多數 training、inference workload 會逐步離開 TF32／BF16，轉向 FP8／FP4。

Atomic Claim 73/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0062

Claim: Rubin BF16/TF32 performance increases 1.6× over Blackwell.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 74/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0061

Claim: Rubin BF16/TF32 Tensor Core width is unchanged from Blackwell.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 75/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0063

Claim: 此架構決策反映 NVIDIA 認為多數 training 與 inference workload 將逐步從 TF32、BF16 轉向 FP8 與 FP4。
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 76/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0060

Claim: Rubin doubles Tensor Core width over Blackwell only for FP4 and FP8.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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On the memory front, the move to HBM4 means double the bus width per stack, running at 10.8 GT/s for 22TB/s total bandwidth or 2.75x Blackwell at the same 288GB capacity as GB300. Memory bandwidth has been upgraded significantly from the original 13TB/s advertised at GTC 2025. In order to catch up to AMD MI450’s memory bandwidth, Nvidia requested much higher HBM4 pin speeds from the DRAM suppliers - well above the speeds that was in the JEDEC specification for HBM4.

Memory 方面，升級 HBM4 後，每 stack bus width 加倍，以 10.8 GT/s 運作，total bandwidth 達 22TB/s；在 capacity 與 GB300 同為 288GB 的情況下，bandwidth 約是 Blackwell 的 2.75x。這也比 GTC 2025 最初公布的 13TB/s 大幅上修。為了追上 AMD MI450 的 memory bandwidth，Nvidia 要求 DRAM supplier 提供遠高於原先 HBM4 JEDEC spec 的 pin speed。

Atomic Claim 77/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0065

Claim: Rubin HBM4 運行速率為 10.8 GT/s。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 78/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0067

Claim: Rubin’s specified 22TB/s HBM bandwidth is 2.75× Blackwell’s.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 79/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0064

Claim: The move from HBM3E to HBM4 doubles bus width per stack.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 80/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0068

Claim: Rubin retains 288GB HBM capacity, the same as GB300.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 81/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0072

Claim: 為追上 AMD MI450 的 memory bandwidth，Nvidia 要求 DRAM suppliers 提供更高的 HBM4 pin speed，且明顯高於 JEDEC 的 HBM4 規範。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 82/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0066

Claim: Rubin 的 HBM 總 bandwidth 為 22TB/s。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 83/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0071

Claim: Rubin HBM bandwidth rises substantially from the original 13TB/s specification announced at GTC 2025.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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While Nvidia is targeting 22TB/s, we understand that memory suppliers are having challenges hitting Nvidia’s requirements and we see it likely that initial shipments will come in slightly below at closer to 20TB/s. We have discussed the implications to SK Hynix, Samsung, and Micron extensively for Accelerator and HBM model subscribers. ↗ Micron is well behind Samsung and Hynix and we believe they are effectively out of the picture for Rubin HBM4. ↗ We have more details on qualifications and pin speeds in the Accelerator and HBM model ↗

Nvidia 目標是 22TB/s，但我們了解 memory supplier 要達到 Nvidia 要求仍有困難，因此 initial shipment 很可能略低，接近 20TB/s。我們已在 Accelerator、HBM model 對 SK Hynix、Samsung、Micron 的影響做大量分析 ↗。Micron 明顯落後 Samsung、Hynix，我們認為實際上已幾乎退出 Rubin HBM4 的供應競爭 ↗。更多 qualification、pin speed 細節可參考 Accelerator 與 HBM model ↗。

Atomic Claim 84/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0072

Claim: SemiAnalysis 了解，memory suppliers 正面臨難以達成 Nvidia HBM bandwidth 要求的挑戰。
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: COMPLETE
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Atomic Claim 85/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0071

Claim: Nvidia 對 Rubin HBM bandwidth 的目標為 22TB/s。
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 86/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0074

Claim: SemiAnalysis expects initial Rubin shipments to be closer to 20TB/s HBM bandwidth than Nvidia’s 22TB/s target.
Frame: CLAIM_ONLY · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 87/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0074

Claim: SemiAnalysis 評估，Micron 在 Rubin HBM4 進度上落後 Samsung 與 SK Hynix。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 88/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0075

Claim: As of February 2026, SemiAnalysis expects Micron to be effectively excluded from Rubin HBM4 supply.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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The NVLink-C2C chiplet houses the SerDes for the Vera CPU connection, doubled in bandwidth to 1.8TB/s, while the larger NVLink 6 chiplet on the other end of the chip features 36 custom ‘400G’ SerDes links for 2x NVLink bandwidth to all 72 Rubin GPUs.

NVLink-C2C chiplet 放置連接 Vera CPU 的 SerDes，bandwidth 加倍到 1.8TB/s；chip 另一端更大的 NVLink 6 chiplet，則包含 36 條 custom『400G』SerDes link，讓通往全部 72 顆 Rubin GPU 的 NVLink bandwidth 加倍。

Atomic Claim 89/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0079::SPLIT01

Claim: The larger Rubin NVLink 6 chiplet sits on the opposite side of the GPU package from the C2C I/O chiplet.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 90/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0078::SPLIT01

Claim: NVLink-C2C chiplet 內含用於連接 Vera CPU 的 SerDes。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 91/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0078::SPLIT02

Claim: NVLink-C2C 與 Vera CPU 之間的 connection bandwidth 加倍至 1.8TB/s。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 92/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0079::SPLIT03

Claim: 較大的 NVLink 6 chiplet 的 links 連向全部 72 顆 Rubin GPU。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 93/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0079::SPLIT02

Claim: 較大的 NVLink 6 chiplet 配置 36 條 custom 400G SerDes links。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 94/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0079::SPLIT04

Claim: 較大的 NVLink 6 chiplet 對全部 72 顆 Rubin GPU 提供 2 倍 NVLink bandwidth。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Transistor count has climbed 60% to 336 billion.

Transistor count 增加 60%，來到 336 billion。

Atomic Claim 95/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0080

Claim: Rubin GPU transistor count increases 60% over Blackwell to 336 billion.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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A notable omission from Rubin is the mention of Sparse FLOPs. In previous generations, 2:4 structured sparsity was used to double marketing FLOPs numbers. However, adoption was minimal especially at low precisions due to accuracy losses from the rigid sparsity structure forcing half of the values to be zero. Programmers basically ignored structured sparsity as it was not useful, which caused hardware designs to change as well. Blackwell Ultra GB300 added 50% more dense FP4 while keeping sparse FP4 FLOPs the same, while AMD’s MI355X stopped supporting structured sparsity on MXFP8, MXFP6 and MXFP4 formats to save silicon area.

Rubin 一個明顯不同之處，是不再強調 Sparse FLOPs。前幾代用 2:4 structured sparsity 把 marketing FLOPs 數字翻倍，但實際 adoption 很低，尤其 low precision 下，僵硬 sparsity pattern 強迫一半 value 變成 0，容易造成 accuracy loss。Programmer 基本上忽略 structured sparsity，因為不實用，hardware design 也因此改變。Blackwell Ultra GB300 增加 50% dense FP4、但 sparse FP4 FLOPs 維持不變；AMD MI355X 更直接取消 MXFP8、MXFP6、MXFP4 的 structured sparsity support，以節省 silicon area。

Atomic Claim 96/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0082

Claim: 在前幾代產品中，2:4 structured sparsity 曾被用來把 marketing FLOPs 數字放大至 2 倍。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 97/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0083

Claim: 然而，structured sparsity 的採用率很低，尤其在 low precision 下，因為僵化的 sparsity 結構迫使一半數值歸零，造成 accuracy loss。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 98/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0087

Claim: Blackwell Ultra GB300 的 sparse FP4 FLOPs 維持不變。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 99/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0088

Claim: AMD 的 MI355X 已停止在 MXFP8、MXFP6 與 MXFP4 格式上支援 structured sparsity。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 100/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0081

Claim: Rubin 的一個明顯缺項，是沒有提到 Sparse FLOPs。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 101/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0085

Claim: Blackwell Ultra GB300 的 dense FP4 增加 50%。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 102/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0089

Claim: AMD 移除 structured-sparsity 支援，是為了節省 silicon area。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 103/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0084::SPLIT02

Claim: Programmers 對 structured sparsity 的低採用促使 hardware designs 隨之改變。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 104/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0084::SPLIT01

Claim: Programmers 基本上忽略 structured sparsity，因為它實用性不足。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Rubin’s adaptive compression engine in the improved Transformer Engine is a key feature to re-boost naturally sparser inference performance by doing dynamic computation of sparsity in-flight and eliminating zeros in the data stream without zeroing out non-zero values, thus maintaining model accuracy while still boosting performance. This is done automatically on existing models built for Blackwell without the need for a new programming model or specific optimizations. While models that utilize Post Training Quantization or Quantization Aware Training will be tuned to maximize adaptive compression speedups, they are not strictly needed to take advantage of dynamic compression.

Rubin 改良 Transformer Engine 的 adaptive compression engine，是重新提高 naturally sparse inference performance 的關鍵。它在 in-flight data 上動態計算 sparsity，直接移除 data stream 中的 zero，但不會把原本非零 value 強制變零，因此既保留 model accuracy，又能提升 performance。現有為 Blackwell 建的 model 不需要新 programming model 或特定 optimization，就能自動使用這項功能。使用 Post Training Quantization 或 Quantization Aware Training 的 model 可以進一步 tuning、最大化 adaptive compression speedup，但並不是享受 dynamic compression 的必要條件。

Atomic Claim 105/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0088

Claim: Rubin 改良版 Transformer Engine 中的 adaptive compression engine，會在資料流中即時動態計算 sparsity 並消除 zeros，但不把非零值強制歸零，因此可維持 model accuracy，同時提升天然較 sparse 的 inference performance。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 106/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0090

Claim: 使用 Post Training Quantization 或 Quantization Aware Training 的 models 可針對 adaptive compression speedup 進一步調校，但要利用 dynamic compression 並不強制需要這些方法。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 107/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0089

Claim: Rubin adaptive compression applies automatically to existing models built for Blackwell, without a new programming model or specific optimizations.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

This means the sparser the workload, the closer the performance will be to the 50 PFLOPS marketed peak performance. NVIDIA thus brands the 50 PFLOPS figure as FP4 Inference while the 35 PFLOPS FP4 Training number is for dense workloads. As accuracy is preserved, this allows the marketing team to claim 5x FLOPs for Rubin over GB200, comparing 50 PFLOPS dynamically compressed FP4 to 10 PFLOPS dense FP4. Whether actual GEMM performance reaches 50 PFLOPS depends on how many zeros are in the tensor. The more zeros, the closer it can reach. The less zeros in the tensor, the lower the speedup. Overall, we expect to see much greater traction for Rubin’s adaptive sparsity compression as opposed to structured sparsity thanks to the automatic implementation.

這代表 workload 越 sparse，performance 就越接近 marketing peak 50 PFLOPS。因此 NVIDIA 把 50 PFLOPS 稱為 FP4 Inference，而 35 PFLOPS FP4 Training 則代表 dense workload。由於 accuracy 不被破壞，marketing team 可以宣稱 Rubin 相較 GB200 有 5x FLOPs——拿 dynamically compressed FP4 50 PFLOPS 去比 dense FP4 10 PFLOPS。實際 GEMM performance 能否到 50 PFLOPS，取決於 tensor 有多少 zero；zero 越多越接近，zero 越少 speedup 越低。整體而言，因為 implementation 是 automatic，我們預期 Rubin adaptive sparsity compression 的 adoption 會明顯高於過去 structured sparsity。

Atomic Claim 108/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0093

Claim: 在維持 accuracy 的前提下，marketing team 可宣稱 Rubin 的 FLOPs 是 GB200 的 5 倍：比較 50 PFLOPS 的 dynamically compressed FP4 與 10 PFLOPS 的 dense FP4。
Frame: COMPARISON · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 109/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0092::EPI02

Claim: Nvidia brands 35 PFLOPS as FP4 Training for dense workloads.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 110/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0097

Claim: 整體而言，SemiAnalysis 預期 Rubin 的 adaptive sparsity compression，因為能自動實作，採用度會明顯高於 structured sparsity。
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 111/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0092::EPI01

Claim: Nvidia brands 50 PFLOPS as FP4 Inference.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 112/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0091

Claim: In Rubin adaptive compression, a sparser workload is expected to approach the marketed 50 PFLOPS peak more closely.
Frame: CLAIM_ONLY · Mode: INFERRED · Mapping: PARTIAL
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Atomic Claim 113/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0094

Claim: Rubin adaptive-compression GEMM performance reaching 50 PFLOPS depends on how many zeros the tensors contain.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 114/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0095

Claim: More tensor zeros allow Rubin adaptive-compression performance to approach the 50 PFLOPS marketed peak more closely.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 115/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0096

Claim: Fewer tensor zeros reduce the speedup available from Rubin adaptive compression.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

With that said, many ML Systems engineer are still skeptical that this new form of sparsity will work well, and it is very possible that Nvidia’s 50 PFLOPS is purely marketing like prior generations

不過，許多 ML Systems engineer 仍懷疑這種新 sparsity 是否真的能有效運作；Nvidia 所稱 50 PFLOPS 也完全有可能像前幾代一樣，主要只是 marketing 數字。

Atomic Claim 116/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0098

Claim: 儘管如此，許多 ML Systems engineers 仍懷疑這種新的 sparsity 是否能良好運作。
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: PARTIAL
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Atomic Claim 117/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0099

Claim: 也很可能 Nvidia 所稱的 50 PFLOPS 和前幾代一樣，主要只是 marketing 數字。
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Rubin’s chip level TDP increases up to 2,300W vs 1000-1400W for Blackwell. Supply chain rumors have indicated that there are 2 different “SKUs” with different power and performance profiles: a Max-P variant at 2,300W and a Max-Q variant at 1,800W. However, these are not distinct hardware SKUs but the 2 default power profiles that Nvidia is offering users based on their workload needs. Max-Q is what Nvidia believes offers the best performance per Watt. Max-P offers the greatest absolute performance though this would come with an efficiency penalty. Running the Max-P setting results in a 20% increase in rack power draw but the performance gain fall well short of this 20% power consumption increase.

Rubin chip-level TDP 最高增至 2,300W，Blackwell 則約 1,000–1,400W。Supply chain 傳聞曾稱有兩種不同 power／performance profile 的『SKU』：2,300W Max-P 與 1,800W Max-Q；但它們其實不是不同 hardware SKU，而是 Nvidia 依 workload 需求提供的兩個 default power profile。Max-Q 是 Nvidia 認為 performance per Watt 最佳的設定；Max-P 追求最高 absolute performance，但會犧牲 efficiency。Max-P 會讓 rack power draw 增加約 20%，但 performance gain 明顯低於 20%。

Atomic Claim 118/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0104

Claim: Rubin Max-P offers the highest absolute performance, with an efficiency penalty relative to Max-Q.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 119/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0105

Claim: Nvidia 認為 Max-Q 提供最佳 performance per Watt。
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 120/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0102

Claim: Rubin Max-P and Max-Q are software power profiles of the same hardware, rather than distinct hardware SKUs.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 121/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0104

Claim: 但這兩者並非不同硬體 SKU，而是 Nvidia 依使用者 workload 需求提供的兩種預設 power profile。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 122/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0101

Claim: Supply chain rumors 指出有兩種不同 power/performance profile：Max-P 為 2,300W，Max-Q 為 1,800W。
Frame: CLAIM_ONLY · Mode: RUMORED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 123/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0105

Claim: The source reports Rubin Max-P raises rack power draw 20% relative to Max-Q.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 124/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0106

Claim: The source reports the Rubin Max-P performance gain over Max-Q is well below its 20% increase in power consumption.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 125/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0100

Claim: Rubin 的 chip-level TDP 最高增加到 2,300W，相較之下 Blackwell 為 1,000–1,400W。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

These power profiles are software managed. Users can also choose whatever max power draw they prefer (as long as it is no more than 2,300W per GPU) and this has been the case for previous GPU generations as well. Several hyperscalers and labs have chosen to run their GPUs at lower power to optimize for performance per Watt as well as taking into account power availability constraints.

這些 power profile 由 software 管理。使用者也能自行設定偏好的 max power draw，只要每顆 GPU 不超過 2,300W；前幾代 GPU 其實也一直如此。已有多家 hyperscaler、lab 選擇讓 GPU 跑在較低 power，以最佳化 performance per Watt，同時配合 power availability constraint。

Atomic Claim 126/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0108

Claim: Users may choose the Rubin maximum power draw up to 2,300W per GPU.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 127/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0110

Claim: 部分 hyperscalers 與 labs 選擇讓 GPUs 以較低 power 運作，以最佳化 performance per Watt，同時納入 power availability constraints。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 128/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0109

Claim: 前幾代 GPU 也同樣可以這樣調整 power draw。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 129/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0107

Claim: Rubin Max-P and Max-Q power profiles are managed by software.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 130/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TIM1

Claim: The Rubin package illustration labels TIM1 as graphene thin film.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

For the mechanical structure of the Rubin package, upgrades have also been made with the addition of an upgraded heat spreader and a stiffener. This compares to Blackwell B200 and B300 packages that only have a heat spreader lid. The heat spreader lid allows more equal distribution of heat exiting the package. It also provides mechanical support for the package to prevent warpage.

Rubin package mechanical structure 也升級，新增強化 heat spreader 與 stiffener。Blackwell B200、B300 package 只有 heat spreader lid；heat spreader lid 能讓 package 排出的熱更平均分布，同時提供 mechanical support、防止 warpage。

Atomic Claim 131/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0111::SPLIT01

Claim: The Rubin package mechanical structure adds an upgraded heat spreader.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 132/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0115

Claim: The Rubin heat-spreader lid provides mechanical support to reduce package warpage.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 133/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0114

Claim: The Rubin heat-spreader lid distributes heat leaving the package more evenly.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 134/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0111::SPLIT02

Claim: The Rubin package mechanical structure adds a stiffener.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 135/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0112

Claim: 相較之下，Blackwell B200 與 B300 package 僅配置 heat spreader lid。
Frame: COMPARISON · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

For Rubin, the heat spreader lid is a module made up of two separate lids. Beside the heat spreader lid, a stiffener is added to the package structure to provide even more mechanical support to avoid warpage. At the surface of the heat spreader lid, there will also be a layer of electroplated gold. The reason for this is to prevent corrosion from liquid metal TIM2, which is between the heat spreader lid and the cold plate.

Rubin 的 heat spreader lid 是由兩個獨立 lid 組成的 module；此外 package structure 另外加入 stiffener，進一步提供 mechanical support、降低 warpage。Heat spreader lid 表面還會有一層 electroplated gold，目的是避免 liquid metal TIM2 腐蝕；TIM2 位於 heat spreader lid 與 cold plate 之間。

Atomic Claim 136/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0119::SPLIT02

Claim: Rubin liquid metal TIM2 is between the heat spreader lid and the cold plate.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 137/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0117

Claim: 除了 heat spreader lid 之外，package structure 也加入 stiffener，提供更多 mechanical support 以避免 warpage。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 138/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0118

Claim: The Rubin heat-spreader lid surface is electroplated with gold.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 139/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0119::SPLIT01

Claim: The Rubin heat spreader lid surface is gold-plated to prevent corrosion from liquid metal TIM2.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 140/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0116

Claim: 對 Rubin 而言，heat spreader lid 是由兩個獨立 lids 組成的 module。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Vera

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

NVIDIA was aggressive on the CPU front ↗, with Vera doubling performance over Grace by moving to a 3nm reticle-sized compute die and disaggregating the memory controllers and I/O into chiplets. Core count increases from 72 to 88, with 91 cores printed on die to leave redundancy for yield improvement. These cores mark the return of NVIDIA’s custom ARM CPU designs, with the ‘Olympus’ core now supporting SMT multi-threading for a total of 176 processing threads. L3 cache also received a 40% capacity bump to 162MB. Memory bus width doubled to 1024-bit and speed increased to 9600MT/s for 2.5x bandwidth, while maximum capacity tripled to 1.5TB with 8 SOCAMM modules. The NVLink-C2C to the Rubin GPUs also doubled in bandwidth to 1.8TB/s. PCIe6 and CXL3.1 are now supported as well. All this results in transistor count increasing 2.2x to 227 billion.

CPU 方面 NVIDIA 也非常積極 ↗。Vera 使用 3nm reticle-size compute die，並把 memory controller、I/O 拆到 chiplet，performance 相較 Grace 加倍。Core count 從 72 增至 88，die 上實際 print 91 cores，保留 redundancy 以提高 yield。這些 core 也代表 NVIDIA custom ARM CPU design 回歸；新的『Olympus』core 支援 SMT multi-threading，共 176 processing thread。L3 cache capacity 增加 40% 至 162MB；memory bus width 加倍到 1024-bit、speed 升到 9600MT/s，memory bandwidth 提高 2.5x；8 個 SOCAMM module 讓 maximum capacity 增至 1.5TB、約為前代三倍。連 Rubin GPU 的 NVLink-C2C bandwidth 也加倍到 1.8TB/s，並新增 PCIe 6、CXL 3.1 support。整體 transistor count 增加 2.2x 至 227 billion。

Atomic Claim 141/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT01

Claim: Vera CPU memory bus width doubles to 1024-bit.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 142/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0125

Claim: Vera CPU NVLink-C2C bandwidth to Rubin GPUs doubles to 1.8TB/s.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 143/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0121::SPLIT01

Claim: Vera CPU increases the active core count from 72 to 88.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 144/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT02

Claim: Vera CPU memory speed increases to 9600MT/s.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 145/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0123

Claim: Vera CPU L3 cache capacity increases 40% over Grace to 162MB.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 146/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT05

Claim: For Nvidia’s CPU design, the source attributes Vera CPU performance doubling over Grace to the larger 3nm compute die and disaggregated memory-controller/I/O chiplets.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 147/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT05

Claim: Vera CPU uses eight SOCAMM modules for maximum memory capacity.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 148/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT03

Claim: For Nvidia’s CPU design, Vera CPU disaggregates memory controllers into chiplets.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 149/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT02

Claim: For Nvidia’s CPU design, Vera CPU uses a 3nm reticle-sized compute die.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 150/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0122::SPLIT02

Claim: Vera CPU Olympus cores support SMT multithreading.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 151/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT04

Claim: Vera CPU maximum memory capacity triples to 1.5TB.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 152/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT01

Claim: For Nvidia’s CPU design, Vera CPU doubles performance over Grace.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 153/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0122::SPLIT03

Claim: Vera CPU provides 176 processing threads.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 154/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0124::SPLIT03

Claim: The wider and faster Vera CPU memory interface provides 2.5x memory bandwidth.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 155/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0122::SPLIT01

Claim: Vera CPU Olympus cores mark the return of Nvidia custom ARM CPU designs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 156/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0120::SPLIT04

Claim: For Nvidia’s CPU design, Vera CPU disaggregates I/O into chiplets.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 157/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0126::SPLIT01

Claim: Vera CPU supports PCIe6.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 158/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0126::SPLIT02

Claim: Vera CPU supports CXL3.1.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 159/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0127

Claim: Vera CPU transistor count increases 2.2× over Grace to 227 billion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 160/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0121::SPLIT02

Claim: Vera CPU has 91 cores printed on die to leave redundancy for yield improvement.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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NVLink 6 Switch

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

While the rack-level switching bandwidth has doubled, the number of NVLink Switch chips per rack has also doubled to 36, with each switch tray now housing 4 Switch chips. This means the new NVLink 6 Switch chip has the same 28.8T bandwidth as NVLink5 Switch, with half the number of ports but running at double the rate using ‘400G’ bi-directional SerDes. This allows the high bandwidth switch design to remain as a single monolithic die, saving on design complexity. The layout remains the same as NVIDIA’s previous switches, with 2 sides for IO and a central logic section crossbar and 3.6 TFlop SHARP in-network compute acceleration.

雖然 rack-level switching bandwidth 加倍，但每 rack 的 NVLink Switch chip 數也加倍到 36 顆，每個 switch tray 現在放 4 顆 Switch chip。這代表新 NVLink 6 Switch chip 的 bandwidth 仍是 28.8T、與 NVLink 5 Switch 相同，只是 port 數減半、每 port 速度加倍，使用『400G』bi-directional SerDes。這讓 high-bandwidth switch 仍能維持單一 monolithic die，降低 design complexity。Layout 也延續 NVIDIA 前代 switch：兩側為 I/O，中間是 logic crossbar，並包含 3.6 TFlop SHARP in-network compute acceleration。

Atomic Claim 161/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0128::SPLIT02

Claim: Rubin doubles the number of NVLink switch chips per rack to 36.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 162/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0132::SPLIT02

Claim: The NVLink 6 switch provides 3.6 TFlop SHARP in-network compute acceleration.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 163/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0128::SPLIT01

Claim: Rubin rack-level NVLink switching bandwidth doubles.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 164/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0131

Claim: The described NVLink 6 SerDes design allows the high-bandwidth switch to remain a single monolithic die, reducing design complexity.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 165/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0129

Claim: 新的 NVLink 6 Switch chip 與 NVLink5 Switch 一樣具有 28.8T bandwidth，但 ports 數量只有一半。
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: PARTIAL
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Atomic Claim 166/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0128::SPLIT03

Claim: Each Rubin NVLink switch tray houses four switch chips.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 167/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0130

Claim: The NVLink 6 switch uses custom 400G bidirectional SerDes operating at twice the prior data rate.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 168/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0132::SPLIT01

Claim: The NVLink 6 switch chip retains the previous Nvidia switch layout: I/O on two sides and a central logic-section crossbar.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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ConnectX-9

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

The ConnectX-9 is largely iterative from ConnectX-8, with the same 800G networking bandwidth and 48-lane PCIe6 switch capability. However, CX-9 now supports 800G Ethernet with 4x200G PAM4 SerDes, compared to CX-8 that only supported it on InfiniBand. For the Rubin platform, NVIDIA is doubling the number of NICs per GPU to achieve 2x scale-out bandwidth.

ConnectX-9 大致是 ConnectX-8 的 iterative upgrade，networking bandwidth 同為 800G，也同樣具備 48-lane PCIe 6 switch capability。不過 CX-9 現在可用 4x200G PAM4 SerDes 支援 800G Ethernet；CX-8 的 800G 只支援 InfiniBand。Rubin platform 上，NVIDIA 會把每 GPU NIC 數量加倍，因此 scale-out bandwidth 也翻倍。

Atomic Claim 169/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0133::SPLIT03

Claim: ConnectX-9 retains the same 48-lane PCIe6 switch capability as ConnectX-8.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 170/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0133::SPLIT02

Claim: ConnectX-9 retains the same 800G networking bandwidth as ConnectX-8.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 171/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0134

Claim: CX-9 現在可透過 4×200G PAM4 SerDes 支援 800G Ethernet；相較之下，CX-8 的 800G 僅支援 InfiniBand。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 172/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0133::SPLIT01

Claim: ConnectX-9 is largely iterative from ConnectX-8.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 173/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0135

Claim: 在 Rubin platform 上，NVIDIA 將每顆 GPU 對應的 NIC 數量加倍，以達到 2 倍 scale-out bandwidth。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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BlueField-4

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

BlueField-4’s design departs significantly from BlueField-3. Instead of doing a bespoke tapeout with compute and networking, NVIDIA simply reuses their large Grace CPU die, co-packaged with a ConnectX-9 die to make an 800G DPU with massive compute capabilities. 128GB of LPDDR5 feeds the Grace CPU at half the bandwidth of regular Grace. That is 4x the memory capacity of BlueField-3. BlueField-4 can also function as a storage controller, with four BF-4 chips in each Context Memory Storage system.

BlueField-4 design 和 BlueField-3 差異很大。NVIDIA 不再另外做 compute + networking 的 bespoke tapeout，而是直接重用大型 Grace CPU die，再和 ConnectX-9 die co-package，做成具備強大 compute capability 的 800G DPU。128GB LPDDR5 為 Grace CPU 供應 memory，bandwidth 約為一般 Grace 的一半，但 capacity 是 BlueField-3 的 4x。BlueField-4 也能當 storage controller；每套 Context Memory Storage system 會使用 4 顆 BF-4。

Atomic Claim 174/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0140::SPLIT02

Claim: Each Context Memory Storage system contains four BlueField-4 chips.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 175/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0139

Claim: BlueField-4 memory capacity is four times that of BlueField-3.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 176/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0138

Claim: 128GB LPDDR5 供給 Grace CPU，其 bandwidth 為一般 Grace 的一半。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 177/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0140::SPLIT01

Claim: BlueField-4 can function as a storage controller.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 178/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0137

Claim: NVIDIA 不再做 compute/networking 的 bespoke tapeout，而是重用大型 Grace CPU die，與 ConnectX-9 die co-package，形成具備大量 compute capability 的 800G DPU。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Spectrum-6

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

While not part of the Rubin NVL72 rack, Spectrum-6 CPO enables even larger scale-out clusters with its doubled radix. The design retains the same features as Spectrum-5, with 8 IO chiplets surrounding the main switch die. 102.4T switching bandwidth is achieved with 512x 200G SerDes. 32 3.2T optical engines on the package convert these electrical signals to optical links, each with a detachable fiber connector. The SN6810 features one of these chips, while the SN6800 houses four, multiplexed together to create a 409.6T switch box. There will also be a non-CPO version with pluggable OSFP cages in the SN6600. The non-CPO version will be more common in our view.

Spectrum-6 CPO 雖不在 Rubin NVL72 rack 內，但 radix 加倍後，可以支援更大的 scale-out cluster。Design 延續 Spectrum-5：主 switch die 周圍配置 8 顆 I/O chiplet。512x 200G SerDes 提供 102.4T switching bandwidth；package 上 32 顆 3.2T optical engine 把 electrical signal 轉成 optical link，每顆都有 detachable fiber connector。SN6810 內含一顆這種 chip；SN6800 則裝四顆並 multiplex，形成 409.6T switch box。另有非 CPO 版 SN6600，使用 pluggable OSFP cage；我們認為非 CPO 版本會更普及。

Atomic Claim 179/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0148

Claim: SemiAnalysis 預期 Spectrum-6 的 non-CPO SN6600 版本會比 CPO 版本更普遍。
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 180/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0144::SPLIT01

Claim: The Spectrum-6 CPO package has 32 optical engines rated at 3.2T each.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 181/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0142::SPLIT02

Claim: Spectrum-6 has eight I/O chiplets surrounding its main switch die.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 182/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0143

Claim: Spectrum-6 achieves 102.4T switching bandwidth using 512 lanes of 200G SerDes.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 183/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0145

Claim: Spectrum-6 SN6810 contains one 102.4T switch package.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 184/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0144::SPLIT03

Claim: Each Spectrum-6 package optical engine has a detachable fiber connector.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 185/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0146

Claim: Spectrum-6 SN6800 multiplexes four 102.4T switch packages into a 409.6T switch box.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 186/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0141

Claim: Spectrum-6 CPO 雖不屬於 Rubin NVL72 rack，但藉由 doubled radix 可支援更大的 scale-out clusters。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 187/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0147

Claim: Spectrum-6 also offers the non-CPO SN6600 version using pluggable OSFP cages.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 188/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0144::SPLIT02

Claim: Spectrum-6 package optical engines convert electrical signals to optical links.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 189/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0142::SPLIT01

Claim: Spectrum-6 retains the same design features as Spectrum-5.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Rubin Oberon Rack: NVL72 not NVL144 nor NVL36

Since the announcement of GB200 at Nvidia GTC 2024, the concept of an AI server system has shifted from a chassis to a rack scale system. In our GB200 article ↗, we discussed the evolution of Nvidia AI server form factor from HGX (8 GPU per node) to Oberon (NVL72 rack scale). While the HGX form factor still exists, the majority of Nvidia’s Blackwell GPUs are integrated in the Oberon form factor. Rubin will also be offered in both HGX and Oberon systems.

自 Nvidia GTC 2024 公布 GB200 後，AI server system 的概念已從單一 chassis 轉向 rack-scale system。我們在 GB200 文章 ↗ 中討論過 Nvidia AI server form factor 從 HGX（每 node 8 GPU）演進到 Oberon（NVL72 rack-scale）。雖然 HGX form factor 仍存在，但 Nvidia 多數 Blackwell GPU 都整合進 Oberon。Rubin 也會同時提供 HGX、Oberon system。

Atomic Claim 190/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0149

Claim: 自 Nvidia 在 GTC 2024 發表 GB200 後，AI server system 的概念已從 chassis 轉向 rack-scale system。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 191/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0151

Claim: 雖然 HGX form factor 仍存在，但 Nvidia 多數 Blackwell GPUs 已整合在 Oberon form factor。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 192/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0152

Claim: Rubin is offered in HGX and Oberon system form factors.
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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The key difference between the Blackwell and Rubin Oberon architecture is the number of SKUs offered to customers. As Blackwell Oberon was the first ever mass deployment of a rack scale solution with rack power density over 100KW for the GB200 NVL72 SKU, many datacenters did not have the infrastructure ready to support 100kw+ per rack. Nvidia offered two SKUs of Blackwell Oberon: GB200 NVL72 and GB200 NVL36x2. The latter being a lower density SKU offered for customers who did not have the infra ready to handle the thermals of a single high density rack. We discussed the difference between the two form factors in the GB200 article ↗. ↗

Blackwell 與 Rubin 的 Oberon architecture，一個重要差異是提供給 customer 的 SKU 數量。Blackwell Oberon 是第一個真正 mass deployment、rack power density 超過 100kW 的 rack-scale solution；GB200 NVL72 推出時，很多 datacenter infrastructure 還沒準備好承受 100kW+ per rack。因此 Nvidia 為 Blackwell Oberon 提供兩個 SKU：GB200 NVL72 與 GB200 NVL36x2。後者是 lower-density SKU，給 infrastructure 還無法處理單一 high-density rack thermal load 的 customer。我們已在 GB200 文章 ↗ 詳細比較兩種 form factor。

Atomic Claim 193/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0155::SPLIT01

Claim: Nvidia offered GB200 NVL72 as a Blackwell Oberon SKU.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 194/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0155::SPLIT02

Claim: Nvidia offered GB200 NVL36x2 as a Blackwell Oberon SKU.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 195/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0156

Claim: GB200 NVL36x2 is the lower-density Blackwell SKU for customers unable to support the thermal load of a single NVL72 rack.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 196/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0153

Claim: Blackwell 與 Rubin Oberon architecture 的主要差異，是提供給 customers 的 SKU 數量。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 197/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0154::SPLIT02

Claim: At the initial Blackwell Oberon deployment, many datacenters lacked infrastructure for 100kW-plus racks.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 198/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0154::SPLIT01

Claim: Blackwell Oberon GB200 NVL72 was the first mass deployment of a rack-scale solution with power density exceeding 100kW per rack.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Unlike Blackwell, Rubin is only offered in the VR NVL72 SKU. The set up is very similar to that of GB200/GB300 NVL72. Each VR NVL72 system consists of:

Rubin 不同，只提供 VR NVL72 一種 SKU。整體 setup 和 GB200／GB300 NVL72 非常接近。每套 VR NVL72 system 包含：

Atomic Claim 199/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0158

Claim: The described VR NVL72 rack configuration closely resembles GB200/GB300 NVL72.
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 200/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0157

Claim: 不同於 Blackwell，Rubin 只提供 VR NVL72 SKU。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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72 Rubin GPU packages

72 個 Rubin GPU package。

Atomic Claim 201/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0160

Claim: 每套系統包含 72 個 Rubin GPU packages。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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36 Vera CPUs

Atomic Claim 202/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPU36

Claim: Each VR NVL72 rack contains 36 Vera CPUs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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36 NVLink 6 Switch ASICs

36 顆 NVLink 6 Switch ASIC。

Atomic Claim 203/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0161

Claim: 每套系統包含 36 顆 NVLink 6 Switch ASICs。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 204/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TRAY-GPU

Claim: Each compute tray in the VR NVL72 layout contains four Rubin GPUs.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 205/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TRAYS

Claim: The VR NVL72 rack layout contains eighteen 1U compute trays.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 206/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TRAY-CPU

Claim: Each compute tray in the VR NVL72 layout contains two Vera CPUs.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 207/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-OOB

Claim: The VR NVL72 layout includes two out-of-band 1GbE management switches.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

On a side note, VR NVL72 was initially known as VR NVL144 as Jensen math ↗ from GTC 2025 defined the number of GPU as the number of GPU compute die in system (with 2 compute dies per package and 72 Rubin packages per Oberon rack = 144 compute die). The naming was changed back to VR NVL72 to represent the 72 Rubin GPU packages in the system in late December. This was right before CES 2026 where the naming was officially confirmed as VR NVL72.

補充一點：VR NVL72 最初稱為 VR NVL144，因為 GTC 2025 的 Jensen math ↗ 把 GPU 數量定義成 system 內 GPU compute die 數；每個 Rubin package 有 2 顆 compute die，Oberon rack 有 72 個 Rubin package，所以算成 144 compute die。到 12 月底，命名改回 VR NVL72，用 system 裡實際 72 個 Rubin GPU package 表示；CES 2026 前夕正式確認名稱就是 VR NVL72。

Atomic Claim 208/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT03

Claim: Each Rubin GPU package contains two compute dies.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 209/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT05

Claim: With two compute dies per package and 72 packages, the Rubin Oberon rack contains 144 GPU compute dies.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 210/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT01

Claim: VR NVL72 was initially called VR NVL144.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 211/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT04

Claim: Each Rubin Oberon rack contains 72 Rubin GPU packages.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 212/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0164::SPLIT02

Claim: The VR NVL72 name was officially confirmed at CES 2026.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 213/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0164::SPLIT01

Claim: The VR NVL72 name was restored in late December, shortly before CES 2026.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 214/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0162::SPLIT02

Claim: At GTC 2025, Jensen counted GPU compute dies rather than packages for the VR NVL144 name.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 215/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0163

Claim: 到 12 月下旬，命名改回 VR NVL72，以代表 system 內的 72 個 Rubin GPU packages。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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CPX Form Factor

Atomic Claim 216/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPX-TRAY

Claim: The proposed Rubin CPX rack diagram labels eight Rubin CPX GPUs per compute tray.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

Although Nvidia initially planned to integrate the CPX accelerator into the VR NVL72 rack, the current development suggests that CPX will only be offered as a standalone rack as we detailed in our article introducing Nvidia ↗CPX ↗. To recap Rubin-era system planning in our previous CPX article, Nvidia initially contemplated three VR NVL72 configurations:

Nvidia 原本規劃把 CPX accelerator 整合進 VR NVL72 rack，但目前 development direction 顯示，CPX 最後可能只會以 standalone rack 提供；我們在介紹 Nvidia CPX 的文章 ↗ 已詳細說明。回顧前一篇 CPX 文章提到的 Rubin-era system planning，Nvidia 最初考慮過三種 VR NVL72 configuration：

Atomic Claim 217/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0166

Claim: 回顧 Rubin 時代的 system planning，Nvidia 最初考慮過 3 種 VR NVL72 configurations。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 218/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0165

Claim: 雖然 Nvidia 最初計畫把 CPX accelerator 整合進 VR NVL72 rack，但目前 development 顯示 CPX 將只以 standalone rack 形式提供。
Frame: NARY_RELATION · Mode: INFERRED · Mapping: COMPLETE
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VR NVL72 (Regular): Standard Oberon VR NVL72 without CPX

VR NVL72（Regular）：標準 Oberon VR NVL72，不含 CPX。

Atomic Claim 219/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0167

Claim: VR NVL72 Regular configuration 是標準 Oberon VR NVL72，不包含 CPX。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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VR NVL72 CPX (Integrated): Rubin GPU and Rubin CPX within the same compute tray

VR NVL72 CPX（Integrated）：Rubin GPU 與 Rubin CPX 放在同一 compute tray。

Atomic Claim 220/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0168

Claim: VR NVL72 CPX Integrated configuration 把 Rubin GPU 與 Rubin CPX 放在同一個 compute tray 內。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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VR NVL72 CPX (Dual Rack): Rubin CPX deployed in a separate rack alongside the VR NVL72 rack

VR NVL72 CPX（Dual Rack）：Rubin CPX 放在獨立 rack，和 VR NVL72 rack 並列部署。

Atomic Claim 221/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0169

Claim: VR NVL72 CPX Dual Rack configuration 則把 Rubin CPX 部署在獨立 rack，與 VR NVL72 rack 並列。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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The standalone/dedicated rack direction materially changes the deployment calculus. A dual-rack approach allows hyperscalers to scale prefill and decode capacity independently, optimize datacenter power envelopes, and reduce system-level failure domains versus tightly coupled trays. More importantly, it formalizes architectural disaggregation between inference prefill (compute-bound) and decode (bandwidth-bound).

轉向 standalone／dedicated rack，會明顯改變 deployment calculus。Dual-rack 可以讓 hyperscaler 獨立 scale prefill、decode capacity，也能最佳化 datacenter power envelope，並降低 tightly coupled tray 帶來的 system-level failure domain。更重要的是，這正式把 inference prefill（compute-bound）與 decode（bandwidth-bound）在 architecture 上拆開。

Atomic Claim 222/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0171::RESEG01

Claim: Dual-rack approach 讓 hyperscalers 可以獨立擴展 prefill 與 decode capacity。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 223/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0171::RESEG02

Claim: Dual-rack approach 可最佳化 datacenter power envelope。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 224/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0171::RESEG03

Claim: Dual-rack approach 相較 tightly coupled trays 可縮小 system-level failure domain。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 225/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0173

Claim: 更重要的是，這正式形成 inference prefill（compute-bound）與 decode（bandwidth-bound）之間的 architectural disaggregation。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Rubin CPX was originally architected as a GDDR7-based accelerator optimized for prefill, based on three key considerations:

Rubin CPX 原始 architecture 是使用 GDDR7、專為 prefill 最佳化的 accelerator，主要基於三個考量：

Atomic Claim 226/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0174

Claim: Rubin CPX 原先被設計成以 GDDR7 為基礎、針對 prefill 最佳化的 accelerator，主要基於三項考量。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Prefill is primarily FLOPs-limited, not bandwidth-limited, making HBM less indispensable.

Prefill 主要受 FLOPs 限制，而不是 bandwidth，因此 HBM 並非不可或缺。

Atomic Claim 227/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0175

Claim: Prefill 主要受 FLOPs 限制，而不是 bandwidth 限制，因此 HBM 的不可替代性較低。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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HBM’s increased bandwidth is structurally underutilized in prefill.

HBM 增加的 bandwidth 在 prefill 中結構性地無法充分利用。

Atomic Claim 228/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0176

Claim: HBM 增加的 bandwidth 在 prefill 中結構性地沒有被充分利用。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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GDDR7 offers materially lower cost per GB and avoids the need for 2.5D packaging,

GDDR7 的 cost per GB 明顯較低，而且不需要 2.5D packaging。

Atomic Claim 229/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0177

Claim: GDDR7 的每 GB 成本明顯較低。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 230/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0178

Claim: GDDR7 avoids the need for 2.5D packaging.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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However, Nvidia began exploring HBM-equipped variants for prefill, either via modified CPX configurations or through lower memory spec (such as using HBM3E) Rubin deployments dedicated to prefill, which we noted ↗ this way back in early December last year ↗ in our Accelerator & HBM model ↗.

不過 Nvidia 後來開始探索配備 HBM 的 prefill variant：可能是修改 CPX configuration，也可能用較低 memory spec（例如 HBM3E）的 Rubin，專門拿來做 prefill。我們早在去年 12 月初的 Accelerator & HBM model ↗ 就已經提過這個方向。

Atomic Claim 231/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0179::SPLIT01

Claim: Nvidia began exploring modified CPX configurations equipped with HBM for prefill.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 232/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0179::SPLIT02

Claim: Nvidia began exploring lower-memory-spec Rubin deployments, such as HBM3E, dedicated to prefill.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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We also think a lot this shift is driven by evolving memory economics. **Conventional DRAM pricing has risen sharply: **As DDR pricing increases, the relative premium of HBM compresses because pricing is more locked down in long term contracts, narrowing the cost gap between a GDDR-based CPX and lower-spec HBM configurations, therefore eliminating a lot of the cost benefits GDDR offers relative to performance. While memory bandwidth is not as important for pre-fill compare to decode, it is still necessary.

我們也認為，這個轉向很大一部分來自 memory economics 改變。Conventional DRAM 價格大幅上漲；DDR pricing 越高，HBM 相對 premium 就越縮小，因為 HBM 價格多由 long-term contract 鎖定。結果 GDDR-based CPX 與 lower-spec HBM configuration 的 cost gap 縮小，GDDR 原先相對 performance 的不少成本優勢被吃掉。雖然 prefill 相較 decode 沒那麼依賴 memory bandwidth，但 bandwidth 仍然是必要條件。

Atomic Claim 233/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0184

Claim: 成本差距縮小後，GDDR 相對於其效能所具備的 cost advantage 也下降。
Frame: COMPARISON · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 234/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0181

Claim: 隨 DDR 價格上升，HBM 的相對 premium 被壓縮。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 235/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0182

Claim: HBM premium 被壓縮的原因之一，是 HBM pricing 更多已被 long-term contracts 鎖定。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 236/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0180

Claim: 傳統 DRAM 價格已大幅上漲。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 237/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0183

Claim: 雖然 memory bandwidth 對 prefill 的重要性低於 decode，但仍然是必要條件。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 238/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0183

Claim: HBM premium 收斂，使 GDDR-based CPX 與 lower-spec HBM configuration 之間的成本差距縮小。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 239/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0180

Claim: SemiAnalysis 認為轉向 HBM-equipped prefill 設計很大程度由持續變化的 memory economics 驅動。
Frame: CLAIM_ONLY · Mode: INFERRED · Mapping: PARTIAL
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Compute Tray Redesign

One of the major changes with VR NVL72 is within the compute tray. This redesign of the compute tray is centered around simplifying assembly, namely eliminating cables from the compute tray as cables have been the major point of failure of GB200/300 assembly. As Jensen put it at CES 2026, the cableless design reduces the compute tray assembly time from 2 hours to 5 minutes. To achieve this, the VR NVL72 compute tray adopts a modular design with the modules connecting to each via board-to-board connectors.

VR NVL72 一項重大改變在 compute tray。這次 redesign 的核心是簡化 assembly，尤其把 cable 從 compute tray 裡移除，因為 cable 一直是 GB200／300 assembly 最大 failure point。Jensen 在 CES 2026 的說法是，cableless design 把 compute tray assembly time 從 2 小時縮短到 5 分鐘。為做到這點，VR NVL72 compute tray 採 modular design，各 module 透過 board-to-board connector 相連。

Atomic Claim 240/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0185

Claim: compute tray redesign 的核心是簡化 assembly，尤其是從 compute tray 移除 cables；因為 cables 是 GB200／300 assembly 的主要 failure point。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 241/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0187

Claim: 為達到這個目標，VR NVL72 compute tray 採 modular design，各 modules 透過 board-to-board connectors 相互連接。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 242/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0186

Claim: 依 Jensen 在 CES 2026 的說法，cableless design 將 compute tray assembly time 從 2 小時降到 5 分鐘。
Frame: NARY_RELATION · Mode: ATTRIBUTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

To understand the compute tray of VR NVL72 we must first understand the 6 modules that make up the VR NVL72 compute tray:

要理解 VR NVL72 compute tray，先要看構成它的六個 module：

Strata Module x 2

Strata Module ×2。

Atomic Claim 243/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-STRATA2

Claim: Each VR NVL72 compute tray contains 2 Strata modules.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Orchid Module x4

Orchid Module ×4。

Atomic Claim 244/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-ORCHID4

Claim: Each VR NVL72 compute tray contains 4 Orchid modules.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Compute Tray Midplane x 1

Compute Tray Midplane ×1。

Atomic Claim 245/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0189

Claim: 其中包含 1 個 Compute Tray Midplane。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Power Delivery Module x 1

Power Delivery Module ×1。

Atomic Claim 246/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0190

Claim: 關於 compute tray：其中包含 1 個 Power Delivery Module。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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BlueField-4 Module x 1

BlueField-4 Module ×1。

Atomic Claim 247/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0191

Claim: 其中包含 1 個 BlueField-4 Module。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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System Management Module x 1

System Management Module ×1。

Atomic Claim 248/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0192

Claim: Each VR NVL72 compute tray includes one System Management Module.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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We break down these components costs and all the subcomponent costs in the Nvidia VR NVL72 BoM and Power Budget Model ↗.

這些 component 與所有 subcomponent cost，我們都在 Nvidia VR NVL72 BoM and Power Budget Model ↗ 裡逐項拆解。

Strata

Atomic Claim 249/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-STRATA-CON

Claim: The Strata illustration shows three Paladin HD2 board-to-board connectors per board.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Strata Module, Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

Strata Module。Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

Bianca Module. Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

Bianca Module。Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

Situated at the back of the chassis, the Strata module of VR NVL72 is the equivalent of the Bianca board of GB200/300. It houses two Rubin GPUs and one Vera CPU. Unlike Bianca, the LPDDR5X memory for Vera is socketed via SOCAMM module. 8 SOCAMM sockets are placed on the left and right of Vera. Two SOCAMM modules of different capacities are offered, 192GByte and 128GByte, for a maximum of 1,534GByte and a minimum of 1,024GByte per Vera. The Connect-X NICs mezzanine module is also taken off the Strata module as CX-9 is moved to the front of the chassis. Under the cableless design, all the cable connector ports are also removed and replaced by Paladin HD2 board-to-board connectors at the bottom of the module. On the other side, the same set of Paladin HD2 backplane connectors as GB200 and GB300 are identically placed at the back of the module connecting to the NVLink 6 Switches via the NVLink backplane.

VR NVL72 的 Strata module 位於 chassis 後方，相當於 GB200／300 的 Bianca board，內含兩顆 Rubin GPU 與一顆 Vera CPU。與 Bianca 不同，Vera 的 LPDDR5X memory 改成透過 SOCAMM module socketed，Vera 左右各配置 SOCAMM socket、共 8 個。SOCAMM 有 192GB、128GB 兩種 capacity，因此每顆 Vera 最大 memory 可達 1,534GB、最小 1,024GB。ConnectX NIC mezzanine module 也從 Strata 移除，因為 CX-9 被移到 chassis 前方。Cableless design 下，所有 cable connector port 都拿掉，改成 module 底部的 Paladin HD2 board-to-board connector；另一側則保留與 GB200／GB300 相同配置的 Paladin HD2 backplane connector，位於 module 後方，透過 NVLink backplane 連到 NVLink 6 Switch。

Atomic Claim 250/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0200::SPLIT02

Claim: The rear Strata Paladin HD2 connectors connect to NVLink 6 switches through the NVLink backplane.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 251/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0200::SPLIT01

Claim: The Strata module uses the same Paladin HD2 backplane connectors in the same rear positions as GB200 and GB300.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 252/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0197::SPLIT01

Claim: The Vera CPU SOCAMM offering includes a 192GByte module.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 253/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0199

Claim: 在 cableless design 下，所有 cable connector ports 都被移除，改由 module 底部的 Paladin HD2 board-to-board connectors 取代。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 254/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0197::SPLIT04

Claim: The source specifies a minimum 1,024GByte per Vera CPU.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 255/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0196

Claim: Vera 左右兩側配置 8 個 SOCAMM sockets。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 256/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0197::SPLIT03

Claim: The source specifies a maximum 1,534GByte per Vera CPU.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 257/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0198

Claim: Connect-X NIC mezzanine module 也從 Strata module 移除，因為 CX-9 被移到 chassis 前方。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 258/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0193::SPLIT02

Claim: The VR NVL72 Strata module is the equivalent of the GB200/300 Bianca board.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 259/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0194::SPLIT01

Claim: Each Strata module contains two Rubin GPUs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 260/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0195

Claim: 不同於 Bianca，Vera 使用的 LPDDR5X memory 透過 SOCAMM module 以 socket 方式安裝。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 261/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0193::SPLIT01

Claim: The VR NVL72 Strata module sits at the back of the chassis.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 262/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0197::SPLIT02

Claim: The Vera CPU SOCAMM offering includes a 128GByte module.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 263/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0194::SPLIT02

Claim: Each Strata module contains one Vera CPU.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Orchid

Atomic Claim 264/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-ORCHID-E1S

Claim: The Orchid illustration includes one E1.S storage slot per board.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

The Orchid Module houses two ConnectX-9 NICs, two 800G transceiver cages, and one E1.S module slot. Four Orchid modules sit at the front of the chassis. With two Orchid modules stacked on top of each other, they occupy the front left and front right chassis space. At the end of the module there is one Paladin HD2 board-to-board connector that mates with the connector on the midplane. The Orchid module is slim and long, allowing the PCIe 6 signal to travel from the midplane to the CX-9 NICs at the front of the chassis.

Orchid Module 內含兩顆 ConnectX-9 NIC、兩個 800G transceiver cage，以及一個 E1.S module slot。四個 Orchid module 位於 chassis 前方；左右各兩個上下堆疊，占據 front-left、front-right 空間。Module 末端有一個 Paladin HD2 board-to-board connector，與 midplane 上的 connector 對接。Orchid module 做得狹長，讓 PCIe 6 signal 能從 midplane 一路走到 chassis 前端的 CX-9 NIC。

Atomic Claim 265/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0201::SPLIT01

Claim: Each Orchid module houses two ConnectX-9 NICs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 266/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0201::SPLIT03

Claim: Each Orchid module houses one E1.S module slot.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 267/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0202

Claim: Chassis 前方配置 4 個 Orchid modules。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 268/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0201::SPLIT02

Claim: Each Orchid module houses two 800G transceiver cages.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 269/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0204

Claim: Module 末端有 1 個 Paladin HD2 board-to-board connector，會與 midplane 上的 connector 對接。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 270/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0203

Claim: 每兩個 Orchid modules 上下堆疊，分別占據 chassis 前方左側與右側空間。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 271/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0209

Claim: Orchid module 採細長設計，讓 PCIe 6 signal 能從 midplane 傳到 chassis 前方的 CX-9 NICs。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Midplane

Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

The midplane acts as a bridge for the PCIe signal between the two Strata modules and the modules at the front of the chassis. The midplane module is vertically placed across the middle of the chassis with Paladin HD2 board-to-board connector on both sides of the module. Strata modules connect to one side of the midplane while the Orchid modules, the BlueField-4 module, the PDB module, and the management modules connects to the other side.

Midplane 是兩個 Strata module 與 chassis 前方各 module 之間的 PCIe signal bridge。Midplane module 垂直橫跨 chassis 中央，兩側都有 Paladin HD2 board-to-board connector。Strata module 接在其中一側；Orchid module、BlueField-4 module、PDB module、management module 則接在另一側。

Atomic Claim 272/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0210::SPLIT04

Claim: The management module connects to the VR NVL72 midplane side opposite the Strata modules.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 273/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0209

Claim: Strata modules 連接到 midplane 的其中一側。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 274/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0208::SPLIT01

Claim: The VR NVL72 midplane is placed vertically across the middle of the chassis.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 275/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0210::SPLIT01

Claim: The Orchid module connects to the VR NVL72 midplane side opposite the Strata modules.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 276/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0210::SPLIT02

Claim: The BlueField-4 module connects to the VR NVL72 midplane side opposite the Strata modules.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 277/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0208::SPLIT02

Claim: The VR NVL72 midplane has Paladin HD2 board-to-board connectors on both sides.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 278/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0210::SPLIT03

Claim: The PDB module connects to the VR NVL72 midplane side opposite the Strata modules.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 279/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0207

Claim: midplane 作為 PCIe signal bridge，連接兩個 Strata modules 與 chassis 前方的 modules。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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BlueField-4

Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

The BlueField-4 DPU sits in center of the front of the chassis between the left-side Orchid module and the management module. As mentioned in the sections above, BlueField-4 is made up of a Grace CPU and a CX-9 NIC. The module also comes with 128GByte of on board LPDDR5x, 512Gbyte of on board pluggable SSD and an integrated AST2600 BMC from Aspeed. In the reference design of the VR NVL72 compute tray, BlueField-4 acts as a DPU providing up to 800Gb/s of front end networking capability. However, just like BlueField-3, BlueField-4 will only be adopted by a handful of customers, namely CoreWeave and other smaller Neoclouds customers who have less customization capability. For most hyperscalers’ deployments, the BlueField-4 module will be replaced with their in-house frontend networking module or simply with a CX-9 which is cheaper.

BlueField-4 DPU 位於 chassis 前方中央，在左側 Orchid module 與 management module 之間。如前面所述，BlueField-4 由 Grace CPU + CX-9 NIC 組成，module 另外配 128GB onboard LPDDR5X、512GB onboard pluggable SSD，以及 Aspeed AST2600 integrated BMC。VR NVL72 compute tray reference design 中，BlueField-4 作為 DPU，提供最高 800Gb/s frontend networking capability。不過和 BlueField-3 一樣，BlueField-4 只會被少數 customer 採用，主要是 CoreWeave 與 customization capability 較弱的小型 Neocloud。大多數 hyperscaler deployment 會把 BlueField-4 module 換成自家 frontend networking module，或乾脆只用較便宜的 CX-9。

Atomic Claim 280/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0213::SPLIT01

Claim: The BlueField-4 module has 128GByte onboard LPDDR5X.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 281/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0214

Claim: 該 module 還整合一顆來自 Aspeed 的 AST2600 BMC。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 282/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0213::SPLIT02

Claim: The BlueField-4 module has 512GByte onboard pluggable SSD storage.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 283/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0218::SPLIT03

Claim: For most hyperscaler deployments, a CX-9 is the alternative replacement for BlueField-4 described by the source.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 284/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0218::SPLIT02

Claim: The source describes CX-9 as cheaper than the BlueField-4 module in this frontend-networking replacement context.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 285/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0211

Claim: BlueField-4 DPU 位於 chassis 前方中央，在左側 Orchid module 與 management module 之間。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 286/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0218

Claim: 與 BlueField-3 類似，BlueField-4 預期只會被少數客戶採用，例如 CoreWeave 與其他 customization 能力較低的小型 Neoclouds 客戶。
Frame: COMPARISON · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 287/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0215

Claim: 在 VR NVL72 compute tray reference design 中，BlueField-4 作為 DPU，提供最高 800Gb/s front-end networking capability。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 288/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0212::SPLIT01

Claim: BlueField-4 contains a Grace CPU.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 289/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0212::SPLIT02

Claim: BlueField-4 contains a CX-9 NIC.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 290/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0218::SPLIT01

Claim: For most hyperscaler deployments, the source expects BlueField-4 to be replaced by an in-house frontend module as one alternative.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Speaking of BlueField-4, it is important to discuss the new offering Jensen highlighted at CES earlier this year: ICMS, or Inference Context Memory Storage — a platform that we hear may be rebranded to “CMX” at GTC. ICMS, or CMX, introduces a third, entirely separate network dedicated solely to context memory. CMX is a purpose-built KV cache fabric. As long-context inference pushes context windows toward millions of tokens and agentic concurrency scales across users and services, the current memory hierarchy used to store KVcache begins to look insufficient.

談到 BlueField-4，也必須討論 Jensen 今年 CES 強調的新產品：ICMS（Inference Context Memory Storage），我們聽說 GTC 時可能會 rebrand 成『CMX』。ICMS／CMX 引入第三套、完全獨立、專門服務 context memory 的 network。CMX 本質上是一套 purpose-built KV cache fabric。當 long-context inference 把 context window 推向數百萬 token，agentic concurrency 又在 user、service 間同步擴張，現在用來存 KV cache 的 memory hierarchy 開始顯得不夠。

Atomic Claim 291/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0220

Claim: ICMS（或 CMX）新增第 3 個、完全獨立的 network，專門服務 context memory。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 292/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0220

Claim: 在討論 BlueField-4 時，Jensen 於 CES 提出了 ICMS（Inference Context Memory Storage）平台。
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: PARTIAL
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Atomic Claim 293/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0221

Claim: CMX 是為 KV cache 專門打造的 fabric。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 294/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0220::SPLIT02

Claim: SemiAnalysis 聽聞 ICMS（Inference Context Memory Storage）平台可能在 GTC 改名為「CMX」。
Frame: ATTRIBUTE · Mode: RUMORED · Mapping: PARTIAL
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Atomic Claim 295/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0222

Claim: 隨 long-context inference 把 context window 推向數百萬 tokens，且 agentic concurrency 在 users 與 services 間擴大，現有用於儲存 KV cache 的 memory hierarchy 開始顯得不足。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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KV cache grows linearly with sequence length and multiplicatively with workload parallelism, quickly expanding beyond what any single tier of memory was designed to hold. GPU HBM, while unmatched in bandwidth and latency, is not enough on its own to store KV especially for longer sequence length queries that are becoming popular between turns or tool calls. Host DRAM extends capacity but remains node-bound and limited in aggregate footprint and ultimately has limited capacity. Meanwhile, traditional shared storage—architected for durability rather than latency —has more access time and power overhead, making it unsuitable for participation in the decode loop.

KV cache 會隨 sequence length 線性成長，又會隨 workload parallelism 倍數放大，很快就超過任何單一 memory tier 原先設計承受的容量。GPU HBM 雖然 bandwidth、latency 無可取代，但單靠 HBM 已不足以存放越來越長的 KV，尤其 turn 與 tool call 之間常見的 long-sequence query。Host DRAM 能擴充 capacity，卻仍受 node-bound 限制，aggregate footprint 與最終 capacity 都有限；傳統 shared storage 則是為 durability 而設計、不是 latency，access time 與 power overhead 更高，不適合參與 decode loop。

Atomic Claim 296/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0229

Claim: Host DRAM 的 aggregate footprint 與 capacity 有上限。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 297/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0223::SPLIT03

Claim: The combined KV cache growth can quickly exceed what any single memory tier was designed to hold.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 298/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0228

Claim: Host DRAM 仍受限於單一 node。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 299/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0227

Claim: Host DRAM 可以擴充 memory capacity。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 300/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0223::SPLIT01

Claim: KV cache grows linearly with sequence length.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 301/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0227

Claim: 另一方面，traditional shared storage 的設計重點是 durability 而不是 latency，因此 access time 與 power overhead 較高，不適合參與 decode loop。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 302/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0223::SPLIT02

Claim: KV cache grows multiplicatively with workload parallelism.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 303/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0224

Claim: GPU HBM 雖然在 bandwidth 與 latency 上無可匹敵，但單靠 HBM 不足以儲存 KV，尤其是愈來愈常見、跨 turns 或 tool calls 的較長 sequence-length queries。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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As we noted in mid-January in our Memory Model note ↗, Nvidia’s ICMS inserts a new G3.5 tier between local SSD (G3) and shared storage (G4), optimized specifically for ephemeral, recomputable KV cache. The ICMS requires a dedicated networking layer designed exclusively for KV traffic. Wherever networking is used in this architecture, it is provisioned as a context memory network — isolated from general data movement and optimized for predictable decode latency.

如我們 1 月中 Memory Model note ↗ 所寫，Nvidia ICMS 在 local SSD（G3）與 shared storage（G4）之間插入新的 G3.5 tier，專門為 ephemeral、可重算的 KV cache 最佳化。ICMS 需要一套只為 KV traffic 設計的 dedicated networking layer；在這個 architecture 中，只要用到 networking，就被 provision 成 context memory network，和一般 data movement 隔離，並針對 predictable decode latency 最佳化。

Atomic Claim 304/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0228

Claim: Nvidia 的 ICMS 在 local SSD（G3）與 shared storage（G4）之間插入新的 G3.5 tier，專門針對 ephemeral、可重新計算的 KV cache 最佳化。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 305/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0233

Claim: 在此架構中，只要使用 networking，就會配置成 context memory network，與一般 data movement 隔離，並針對可預測的 decode latency 最佳化。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 306/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0229

Claim: ICMS 需要一層專門為 KV traffic 設計的獨立 networking layer。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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The challenge with this is that the volumes of SSDs going to ICMS / CMX are quite overblown by the industry. We worked through the math in the Memory model ↗ and Tokenomics model ↗.

這裡的問題是，業界對 ICMS／CMX 會吃掉多少 SSD volume 的想像相當膨脹。我們已在 Memory Model ↗ 與 Tokenomics Model ↗ 把數學完整算過。

Atomic Claim 307/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0232

Claim: SemiAnalysis 認為，業界對流向 ICMS／CMX 的 SSD volumes 有相當程度的高估。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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BlueField-4 will be the silicon anchor of this third network. Positioned on the storage array, it terminates NVMe-oF and RDMA traffic at line rate and manages KV movement independently of host CPUs and GPUs. With 2×400G SerDes links providing 800Gb/s of bandwidth, integrated Grace CPU, and LPDDR, BlueField-4 would act as the controller for a distributed context memory fabric. In a preferred DGX-style configuration, a single BlueField-4 per tray may serve four Rubin processors, with the DPU dedicated purely to KV cache traffic and not shared with generic storage I/O.

BlueField-4 會成為這第三套 network 的 silicon anchor。它位於 storage array 端，以 line rate terminate NVMe-oF、RDMA traffic，並且完全獨立於 host CPU、GPU 管理 KV movement。兩條 400G SerDes link 提供總計 800Gb/s bandwidth，再加 integrated Grace CPU 與 LPDDR，BlueField-4 可以當 distributed context-memory fabric 的 controller。在偏好的 DGX-style configuration 中，每 tray 一顆 BlueField-4 可服務四顆 Rubin processor；這顆 DPU 只處理 KV cache traffic，不和 generic storage I/O 共用。

Atomic Claim 308/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0238

Claim: 在原文偏好的 DGX-style context-memory 配置中，BlueField-4 DPU 將專用於 KV cache traffic，不與 generic storage I/O 共用。
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Atomic Claim 309/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0236

Claim: 搭配 LPDDR，BlueField-4 將作為 distributed context memory fabric 的 controller。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 310/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0235::SPLIT01

Claim: BlueField-4 has two 400G SerDes links providing 800Gb/s bandwidth.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 311/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0234::SPLIT03

Claim: In the proposed context-memory network, BlueField-4 manages KV movement independently of host CPUs and GPUs.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 312/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0234::SPLIT01

Claim: In the proposed context-memory network, BlueField-4 on the storage array terminates NVMe-oF traffic at line rate.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 313/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0233

Claim: BlueField-4 將成為這個第 3 network 的 silicon anchor。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 314/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0235::SPLIT02

Claim: BlueField-4 integrates a Grace CPU.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 315/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0237

Claim: 在偏好的 DGX-style configuration 中，每個 tray 可能配置 1 顆 BlueField-4，服務 4 顆 Rubin processors。
Frame: NARY_RELATION · Mode: HYPOTHETICAL · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 316/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0234::SPLIT02

Claim: In the proposed context-memory network, BlueField-4 on the storage array terminates RDMA traffic at line rate.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
開啟本版 Claim 與證據

The new CMX/ICMS ecosystem will likely include leading storage providers such as Weka, DDN, Dell Technologies, NetApp, VAST Data, and others.

新的 CMX／ICMS ecosystem 很可能會包含 Weka、DDN、Dell Technologies、NetApp、VAST Data 等 leading storage provider。

Atomic Claim 317/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0242

Claim: 新的 CMX／ICMS ecosystem 可能包含主要 storage provider Weka。
Frame: RELATION · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 318/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0239::SPLIT05

Claim: The CMX/ICMS ecosystem will likely include VAST Data.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 319/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0239::SPLIT04

Claim: The CMX/ICMS ecosystem will likely include NetApp.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 320/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0239::SPLIT03

Claim: The CMX/ICMS ecosystem will likely include Dell Technologies.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 321/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0239::SPLIT02

Claim: The CMX/ICMS ecosystem will likely include DDN.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Power Delivery

The power delivery module sits above the BlueField-4 module. The module receives 50V power from the internal busbar cable. Then the current is stepped down to 12V with a modular power brick. Then, 12V current is delivered to the Orchid module, the BlueField-4 module, the management modules via smaller internal busbars.

Power delivery module 位於 BlueField-4 module 上方。它先從 internal busbar cable 接收 50V power，再透過 modular power brick 降到 12V，最後以較小 internal busbar，把 12V 供給 Orchid module、BlueField-4 module、management module。

Atomic Claim 322/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0243::SPLIT02

Claim: The VR NVL72 power module delivers 12V to the BlueField-4 module through smaller internal busbars.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 323/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0242

Claim: In the VR NVL72 compute-tray power path, the modular power brick steps voltage down to 12V.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 324/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0243::SPLIT01

Claim: The VR NVL72 power module delivers 12V to the Orchid module through smaller internal busbars.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 325/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0243::SPLIT03

Claim: The VR NVL72 power module delivers 12V to the management modules through smaller internal busbars.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 326/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0240

Claim: The VR NVL72 power-delivery module sits above the BlueField-4 module.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 327/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0241

Claim: The VR NVL72 power-delivery module receives 50V from the internal busbar cable.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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In the VR NVL72 Component BoM and Power Budget Model ↗ we have the breakdown of the power delivery content for BlueField, Strada board, and the rest of the rack’s components.

VR NVL72 Component BoM and Power Budget Model ↗ 裡，我們有完整拆解 BlueField、Strata board，以及 rack 其他 component 的 power delivery content。

System Management

The management module is made up of multiple smaller management modules that fall under this category. These modules occupy a long slim space between the BlueField-4 module and the right-side Orchid modules. The management modules are the following:

Management module 其實由多個較小的 management module 組成，統稱在這個 category 下。這些 module 位於 BlueField-4 module 與右側 Orchid module 之間一條狹長空間。包含：

Atomic Claim 328/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0245

Claim: 這些 management modules 位於 BlueField-4 module 與右側 Orchid modules 之間的一條狹長空間。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 329/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0244

Claim: The VR NVL72 management-module category includes multiple smaller management modules.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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System Management Module (SMM)

System Management Module（SMM）。

Atomic Claim 330/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0247

Claim: The VR NVL72 management-module category includes a System Management Module (SMM).
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Trusted Platform Module (TPM)

Trusted Platform Module（TPM）。

Atomic Claim 331/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0248

Claim: 其中包含 Trusted Platform Module（TPM）。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Datacenter Secure Control Module (DC-SCM)

Datacenter Secure Control Module（DC-SCM）。

Atomic Claim 332/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0249

Claim: The VR NVL72 management-module category includes a Datacenter Secure Control Module (DC-SCM).
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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These modules provide management security functions over the compute tray. Hyperscalers usually have their own in-house management module design. Therefore, the management modules may be different for each end customer. Besides BlueField-4, the power delivery module and the management modules are the only other two components within the compute tray that Nvidia allows customization for. Some end customers are considering integrating the management modules into the power delivery module. Nevertheless, the modules need to follow the form factor that Nvidia provides so it can fit into the designated connector on the compute tray midplane.

這些 module 負責 compute tray 的 management、security function。Hyperscaler 通常有自家 in-house management module design，因此不同 end customer 最後使用的 management module 可能不同。除了 BlueField-4 外，power delivery module 與 management module 是 compute tray 裡 Nvidia 唯二另外允許 customization 的 component。有些 end customer 正考慮把 management module 直接整合進 power delivery module。不過不論怎麼客製，module 都必須遵循 Nvidia 提供的 form factor，才能插進 compute tray midplane 指定 connector。

Atomic Claim 333/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0250

Claim: 這些 modules 為 compute tray 提供 management 與 security functions。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 334/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0255

Claim: 不過，這些 modules 仍必須遵循 Nvidia 提供的 form factor，才能裝入 compute tray midplane 上指定的 connector。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 335/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0253

Claim: 除了 BlueField-4 之外，power delivery module 與 management modules 是 compute tray 內另外兩種 Nvidia 允許客製化的 components。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 336/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0251

Claim: Hyperscalers 通常有自家的 management module 設計。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 337/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0252

Claim: VR NVL72 management-module designs can differ by end customer.
Frame: CLAIM_ONLY · Mode: INFERRED · Mapping: PARTIAL
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Atomic Claim 338/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0254

Claim: Some VR NVL72 customers are considering integrating management modules into the power-delivery module.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Compute Tray Topology

The compute tray topology of VR NVL72 is roughly similar to that of GB200 and GB300. The three main differences to Grace Blackwell are the connections between GPU and ConnectX NICs, the connections to the local NVMe storage, and the connection between the BlueField-4 and ConnectX-9.

VR NVL72 compute tray topology 大致和 GB200、GB300 類似。相較 Grace Blackwell，主要有三個差異：GPU 與 ConnectX NIC 的 connection、local NVMe storage 的 connection，以及 BlueField-4 與 ConnectX-9 之間的 connection。

Atomic Claim 339/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0257::SPLIT01

Claim: Compared with Grace Blackwell, VR NVL72 changes the connections between GPUs and ConnectX NICs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 340/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0257::SPLIT03

Claim: Compared with Grace Blackwell, VR NVL72 changes the connection between BlueField-4 and ConnectX-9.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 341/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0256

Claim: VR NVL72 的 compute tray topology 與 GB200、GB300 大致相似。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 342/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0257::SPLIT02

Claim: Compared with Grace Blackwell, VR NVL72 changes the connections to local NVMe storage.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

Firstly, the connection between the GPU and the ConnectX NICs evolved from GB200 to GB300 then to Vera Rubin. For GB200, the GPU does not have direct access to the ConnectX-7. Instead, B200 connects to Grace CPU via C2C connection then the Grace CPU talks to the ConnectX-7 over PCIe 5. For GB300, Nvidia introduced NIC direct to ConnectX-8, which allows the B300 GPU to communicate directly with the ConnectX-8 NIC without going through the Grace CPU.

首先，GPU 與 ConnectX NIC 的連法從 GB200、GB300 到 Vera Rubin 一路演進。GB200 時，GPU 無法直接 access ConnectX-7；B200 先透過 C2C 連 Grace CPU，再由 Grace CPU 走 PCIe 5 和 ConnectX-7 communication。GB300 則導入 NIC Direct to ConnectX-8，讓 B300 GPU 能直接和 ConnectX-8 NIC communication，不必再繞 Grace CPU。

Atomic Claim 343/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0260

Claim: 相反地，B200 先透過 C2C connection 連到 Grace CPU，再由 Grace CPU 透過 PCIe 5 與 ConnectX-7 通訊。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 344/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0258

Claim: 首先，GPU 與 ConnectX NICs 之間的連線，從 GB200 到 GB300，再到 Vera Rubin 持續演進。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 345/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0261

Claim: 在 GB300 中，Nvidia 導入 NIC direct to ConnectX-8，使 B300 GPU 可直接與 ConnectX-8 NIC 通訊，不需經過 Grace CPU。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 346/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0259

Claim: 在 GB200 中，GPU 無法直接存取 ConnectX-7。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Essentially, this means ConnectX-8 has two hosts, Grace CPU and B300 GPU. This improves latency in the backend network. However, for VR NVL72, the direct connection between Rubin GPU and ConnectX-9 is reverted back to the same design as GB200, as Rubin does not have PCIe bandwidth for two Connect-9. Rubin connects to Vera via C2C link, then Vera will connect to ConnectX-9 via PCIe6 lanes.

本質上，ConnectX-8 變成有兩個 host：Grace CPU 與 B300 GPU，因此 backend network latency 得以改善。不過 VR NVL72 又把 Rubin GPU ↔ ConnectX-9 的 direct connection 改回類似 GB200 的設計，因為 Rubin 沒有足夠 PCIe bandwidth 同時直接連兩顆 ConnectX-9。Rubin 先透過 C2C link 連 Vera，再由 Vera 用 PCIe 6 lane 連 ConnectX-9。

Atomic Claim 347/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0263

Claim: The described Astra management offload is intended to improve VR NVL72 backend-network latency.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 348/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0264

Claim: 但在 VR NVL72 中，Rubin GPU 與 ConnectX-9 的 direct connection 又回到與 GB200 相同的設計，因為 Rubin 沒有足夠的 PCIe bandwidth 供兩個 ConnectX-9 使用。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 349/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0265

Claim: Rubin 先透過 C2C link 連到 Vera，再由 Vera 透過 PCIe6 lanes 連到 ConnectX-9。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 350/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0262

Claim: 這代表 ConnectX-8 有兩個 hosts：Grace CPU 與 B300 GPU。
Frame: NARY_RELATION · Mode: INFERRED · Mapping: COMPLETE
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Secondly, the local NVMe storage for Rubin has been moved to a different location from that of NVMe storage in Grace Blackwell. Previously, local NVMe storage was managed by BlueField-3. For VR NVL72, the local NVMe storage is physically on the Orchid module managed by the ConnectX-9.

第二，Rubin 的 local NVMe storage 位置也和 Grace Blackwell 不同。以前 local NVMe 由 BlueField-3 管理；VR NVL72 則把 local NVMe 直接放到 Orchid module 上，交由 ConnectX-9 管理。

Atomic Claim 351/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0266

Claim: 第二，Rubin 的 local NVMe storage 已移到與 Grace Blackwell 中 NVMe storage 不同的位置。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 352/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0267

Claim: 過去，local NVMe storage 由 BlueField-3 管理。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 353/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0268::SPLIT01

Claim: VR NVL72 local NVMe storage is physically on the Orchid module.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 354/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0268::SPLIT02

Claim: ConnectX-9 manages VR NVL72 local NVMe storage.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia ↗, Nvidia VR NVL72 BoM and Power Budget Model ↗

Lastly, the BlueField-4 DPU is able to control the 8 ConnectX-9 backend NICs allowing for unified management of both front end north-south network & back end high speed East-West networks. This system, known as Advanced Secure Trusted Resource Architecture (Astra), thus takes the provisioning and monitoring load off of the host CPU. The only issue with this is that BlueField-4 is expensive, so we expect most hyperscale customers to deploy their in-house DPU solutions instead. We will discuss customization more in the later sections.

最後，BlueField-4 DPU 可以控制 8 顆 ConnectX-9 backend NIC，統一管理 frontend north-south network 與 backend high-speed east-west network。這套系統稱為 Advanced Secure Trusted Resource Architecture（Astra），可把 provisioning、monitoring 負載從 host CPU 移走。唯一問題是 BlueField-4 很貴，因此我們預期多數 hyperscale customer 最後會部署自家 DPU solution；後面 customization 一節會再談。

Atomic Claim 355/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0269::SPLIT02

Claim: BlueField-4 control of backend NICs enables unified management of frontend north-south and backend high-speed east-west networks.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 356/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0270

Claim: 這套稱為 Advanced Secure Trusted Resource Architecture（Astra）的 system，會把 provisioning 與 monitoring 負載從 host CPU 移開。
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: PARTIAL
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Atomic Claim 357/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0269::SPLIT01

Claim: BlueField-4 DPU can control eight ConnectX-9 backend NICs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 358/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0271

Claim: 問題在於 BlueField-4 成本高，因此 SemiAnalysis 預期多數 hyperscale customers 會改用自家的 DPU solutions。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: PARTIAL
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Evolution from Blackwell

All of these modules in the VR NVL72 compute tray, while not exactly the same, are found in the compute tray of GB200/300. The only difference is the midplane module as it is a new component introduced to eliminate internal cables form the compute tray. Also, the modules at the front of the chassis (daughter modules) are much longer than their equivalent in Blackwell to connect the signal from the midplane to the front I/O ports via PCB. In the sections below we will discuss the cableless design, the changes in thermal design, and the changes in mechanical design in the compute tray.

VR NVL72 compute tray 裡這些 module 雖然不完全相同，但 GB200／300 compute tray 基本上也都有對應 component。唯一真正新增的是 midplane module，用來消除 compute tray 內部 cable。另外 chassis 前方的 daughter module 也比 Blackwell 對應 module 長很多，因為 signal 要透過 PCB 從 midplane 拉到 front I/O port。下面會依序討論 cableless design、thermal design change 與 mechanical design change。

Atomic Claim 359/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0273

Claim: 唯一的差異是 midplane module；它是新加入的 component，用來消除 compute tray 內部 cables。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 360/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0272

Claim: VR NVL72 compute tray 裡的這些 modules 雖然不完全相同，但在 GB200/300 的 compute tray 中也都找得到對應元件。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 361/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0274

Claim: 此外，chassis 前端的 daughter modules 比 Blackwell 中的對應模組長得多，以便透過 PCB 把 midplane 的 signal 接到前端 I/O ports。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Compute Tray Cableless Design

As mentioned above the VR NVL72 compute tray is designed around the cableless concept. As we discussed in our PCB Supercycle Core Research note in August last year ↗ as well as our recent Core Research note on Amphenol’s AI Content ↗, there are two reasons for this design. First, flyover cables present multiple different points of failure as they can easily be damaged during assembly. Second, the high-density design of VR NVL72 leaves limited space for cables to be routed.

如前面所述，VR NVL72 compute tray 是圍繞 cableless concept 設計。我們去年 8 月 PCB Supercycle Core Research note ↗，以及最近 Amphenol AI Content Core Research note ↗ 都提過兩個原因。第一，flyover cable 有很多 failure point，assembly 過程中很容易受損；第二，VR NVL72 的 high-density design 幾乎沒有多餘空間可以 route cable。

Atomic Claim 362/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0279

Claim: 第一，flyover cables 有多個不同的 failure points，因為它們在 assembly 過程中很容易受損。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 363/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0277

Claim: 如前所述，VR NVL72 compute tray 是以 cableless concept 為核心設計。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 364/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0280

Claim: 第二，VR NVL72 的 high-density design 留給 cable routing 的空間有限。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Replacing Internal Cables with Board-to-Board Connectors

For the GB200/300, the most valuable cable that is exclusively supplied by Amphenol is the DensiLink OverPass cable set within the compute tray. This cable provides the ethernet connection between the CX-7/8 NIC and the OSFP cages. However, this cable is extremely vulnerable to scratches and damage of the cable termination during assembly, thereby creating many points of failure. There are also several other lower-end PCIe cables in use (MCIO and SlimSAS) that also suffer from the same points of failure. These cables involve many other suppliers as well – complicating procurement and vendor management. Given the delicate nature of the cable, workers must be extremely careful while placing the cables in a very dense and compact chassis, which prolongs assembly time.

GB200／300 compute tray 裡價值最高、且由 Amphenol 獨家供應的 cable，是 DensiLink OverPass cable set，負責 CX-7／8 NIC 到 OSFP cage 的 Ethernet connection。但這種 cable 在 assembly 時非常容易被刮傷，termination 也很脆弱，因此產生大量 failure point。此外還有 MCIO、SlimSAS 等較低階 PCIe cable，也有類似問題，且涉及更多 supplier，讓 procurement、vendor management 更複雜。由於 cable 很精密，worker 必須在高度密集、狹小 chassis 中非常小心地安裝，也直接拉長 assembly time。

Atomic Claim 365/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0286

Claim: 由於 cable 很脆弱，工人在非常 dense、compact 的 chassis 中放置 cables 時必須格外小心，因而拉長 assembly time。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 366/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0281

Claim: 在 GB200/300 中，compute tray 內最有價值、由 Amphenol 獨家供應的 cable 是 DensiLink OverPass cable set。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 367/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0282

Claim: 這條 cable 提供 CX-7/8 NIC 與 OSFP cages 之間的 Ethernet connection。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 368/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0283

Claim: GB300 DensiLink OverPass cables are vulnerable to scratches and termination damage during assembly, creating failure points.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 369/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0284

Claim: 另外也使用多種較低階的 PCIe cables（MCIO、SlimSAS），同樣存在這些 failure points。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 370/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0285

Claim: The cable types used in the GB300 compute tray involve multiple suppliers, complicating procurement and vendor management.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Although a cableless design might initially appear unfavorable for Amphenol, it is in fact a positive. Signals between the Strata module and the daughter modules still need a physical interconnect. In this architecture, those signals exit the Strata board through Amphenol’s PaladinHD2 board-to-board connectors. The signal is then routed through a PCB midplane sitting in the middle of the chassis. On the other side of the PCB midplane, the daughter modules connect to the PCB midplane via another set of Paladin HD2 B2B connectors. In our VR NVL72 Component BoM and Power Budget Model ↗ we have a detailed breakdown of Amphenol’s compute tray content in Vera Rubin NVL72. This is also discussed in more detail in our article on **Amphenol’s AI Content. ↗ **

Cableless design 表面上看似對 Amphenol 不利，實際上反而是正面。Strata module 和 daughter module 間仍需要 physical interconnect，只是 signal 改從 Strata board 經 Amphenol Paladin HD2 board-to-board connector 離開，再走 chassis 中央 PCB midplane；midplane 另一側，daughter module 也透過另一組 Paladin HD2 B2B connector 接上。VR NVL72 Component BoM and Power Budget Model ↗ 有 Amphenol 在 Vera Rubin NVL72 compute tray content 的完整拆解；我們的 Amphenol AI Content 文章 ↗ 也有更深入分析。

Atomic Claim 371/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0288

Claim: 在這個 architecture 中，signals 會從 Strata board 經由 Amphenol 的 PaladinHD2 board-to-board connectors 離開。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 372/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0287

Claim: 原文判斷：雖然 cableless design 初看可能對 Amphenol 不利，但實際上反而是正面因素，因為 Strata module 與 daughter modules 之間的 signals 仍需要 physical interconnect。
Frame: NARY_RELATION · Mode: INFERRED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 373/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0289

Claim: 接著 signal 會經過位於 chassis 中央的 PCB midplane。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 374/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0290

Claim: 在 PCB midplane 另一側，daughter modules 透過另一組 Paladin HD2 B2B connectors 連到 PCB midplane。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 375/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-BW-CON-COMPARE

Claim: The Amphenol content table specifies four DensiLink Overpass flyover cables per GB300 compute tray.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 376/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CON-COMPARE

Claim: The Amphenol content table specifies 22 Paladin HD2 board-to-board connectors per VR NVL72 compute tray.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

Relocating ConnectX-9

To accommodate this cableless design, the CX-9 NICs, that would have been on the Strata modules, are relocated to the Orchid module (from the back half to the front half of the chassis) as illustrated in the diagram below.

為配合 cableless design，原本會放在 Strata module 的 CX-9 NIC 被移到 Orchid module，也就是從 chassis 後半部搬到前半部，如下圖所示。

Atomic Claim 377/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0291

Claim: 為了配合 cableless design，原本會放在 Strata modules 上的 CX-9 NICs 被移到 Orchid module，也就是從 chassis 後半部移到前半部。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

For the GB200/GB300, the PCIe signal distance between the GPU/CPU and the CX-7/8 is shorter than the Ethernet/InfiniBand signal distance between the CX-7/8 and the OSFP cages. Previously – having to transmit a 200G Ethernet/InfiniBand signal from the NIC in the back half of the compute tray to the OSFP cage in the front of the compute tray necessitated the use of flyover cables as the signal loss over PCB at 200Gbit/s (uni-directional) per lane is too high.

GB200／GB300 中，GPU／CPU 到 CX-7／8 的 PCIe signal distance，比 CX-7／8 到 OSFP cage 的 Ethernet／InfiniBand distance 短。過去 NIC 位於 compute tray 後半部，要把每 lane 單向 200Gbit/s Ethernet／InfiniBand signal 傳到前方 OSFP cage，因為 200G signal 走 PCB 的 loss 太高，所以必須使用 flyover cable。

Atomic Claim 378/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0293

Claim: 過去，從 compute tray 後半部的 NIC，把 200G Ethernet／InfiniBand signal 傳到前端 OSFP cage 時，必須使用 flyover cables，因為 PCB 上每 lane 200Gbit/s（uni-directional）的 signal loss 太高。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 379/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0292

Claim: 在 GB200／GB300 中，GPU／CPU 到 CX-7/8 的 PCIe signal 距離，比 CX-7/8 到 OSFP cages 的 Ethernet／InfiniBand signal 距離更短。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

But now that the NIC is closer to the OSFP cage, the lower speed PCIe Gen6 signal (64Gbit/s per lane uni-directional) travels the longer distance. By making the PCIe Gen6 signal longer, the signal can travel over PCB given that PCIe Gen6 has better signal integrity than the higher speed 200G Ethernet/InfiniBand signal.

現在 NIC 已搬近 OSFP cage，反而是較低速度的 PCIe Gen6 signal（每 lane 單向 64Gbit/s）要走較長距離。因為 PCIe Gen6 相較 200G Ethernet／InfiniBand 有更好的 signal integrity，所以即使距離拉長，仍能改走 PCB。

Atomic Claim 380/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0294

Claim: 現在 NIC 更靠近 OSFP cage，因此較低速的 PCIe Gen6 signal（每 lane 64Gbit/s、uni-directional）改為走較長距離。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 381/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0295

Claim: 把 PCIe Gen6 signal 的路徑拉長後，仍可讓 signal 走 PCB，因為 PCIe Gen6 的 signal integrity 優於更高速的 200G Ethernet／InfiniBand signal。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

PCB vs Flyover Cables

Nevertheless, it is still challenging to drive a PCIe Gen6 signal over around 500mm of PCB distance from the Strata Module to the front of the Orchid Module. In addition to having high quality SerDes, proper signal integrity is still achievable by upgrading PCB materials.

即便如此，PCIe Gen6 要從 Strata Module 經約 500mm PCB distance 一路傳到 Orchid Module 前端，仍很有挑戰。除了 high-quality SerDes 之外，也必須升級 PCB material 才能維持足夠 signal integrity。

Atomic Claim 382/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0297

Claim: 除了需要高品質 SerDes，透過升級 PCB materials，仍可達成適當的 signal integrity。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 383/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0296

Claim: 即便如此，要讓 PCIe Gen6 signal 從 Strata Module 經約 500mm 的 PCB 距離走到 Orchid Module 前端，仍然很有挑戰。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

First, we must understand why high-speed signals perform worse on PCB versus flyover cables. As SerDes rates increase, high-speed channels become increasingly constrained by insertion loss introduced by PCB traces, vias, dielectric materials and conductor roughness. Insertion loss is defined as the signal power that is lost as a signal is traveling through an interconnect channel.

首先要理解，為什麼 high-speed signal 走 PCB 比 flyover cable 更差。隨 SerDes rate 提高，PCB trace、via、dielectric material、conductor roughness 帶來的 insertion loss 會越來越成為 high-speed channel 限制。Insertion loss 就是 signal 通過 interconnect channel 時損失的 signal power。

Atomic Claim 384/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0299::SPLIT02

Claim: As SerDes rates increase, insertion loss introduced by vias increasingly constrains high-speed channels.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 385/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0299::SPLIT04

Claim: As SerDes rates increase, insertion loss introduced by conductor roughness increasingly constrains high-speed channels.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 386/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0300

Claim: Insertion loss 定義為 signal 通過 interconnect channel 時損失的 signal power。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 387/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0299::SPLIT01

Claim: As SerDes rates increase, insertion loss introduced by PCB traces increasingly constrains high-speed channels.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 388/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0299::SPLIT03

Claim: As SerDes rates increase, insertion loss introduced by dielectric materials increasingly constrains high-speed channels.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 389/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCL-FOIL

Claim: The CCL composition illustration identifies copper foil as the conductive layer.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 390/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCL-FILLER

Claim: The CCL composition illustration describes filler as part of the insulation layer providing stability.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Source: Doosan, SemiAnalysis

The three main mechanisms contributing to insertion loss in a PCB channel are conductor loss from skin effect and copper surface roughness, dielectric loss from laminate absorption, and geometry loss from discontinuities such as vias and layer changes.

PCB channel 的 insertion loss 主要來自三種機制：skin effect 與 copper surface roughness 造成的 conductor loss、laminate absorption 造成的 dielectric loss，以及 via、layer change 等 discontinuity 造成的 geometry loss。

Atomic Claim 391/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0301::SPLIT03

Claim: PCB geometry loss from discontinuities such as vias and layer changes contributes to insertion loss.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 392/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0301::SPLIT02

Claim: PCB dielectric loss from laminate absorption contributes to insertion loss.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 393/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0301::SPLIT01

Claim: PCB conductor loss from skin effect and copper surface roughness contributes to insertion loss.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 394/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-SKIN

Claim: The cited signal-loss slide gives skin depth as 1/sqrt(pifmu*sigma).
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Source: DesignCon, Circuit Foil Luxembourg

Conductor loss is driven by copper surface roughness. As signals travel down the copper traces in the PCB, energy is lost due to the resistance in copper. At higher frequencies, the signal traveling through the copper crowds toward the surface of the trace, which is known as the skin effect. On top of the natural resistance of copper, if the surface is rough, the current will not travel along a uniform path incurring more resistance and loss.

Conductor loss 主要受 copper surface roughness 影響。Signal 沿 PCB copper trace 傳輸時，本來就會因 copper resistance 損失 energy；frequency 越高，current 越集中在 trace 表面，這就是 skin effect。在 copper 天生 resistance 之外，如果表面又粗糙，current path 不再均勻，會進一步增加 resistance 與 loss。

Atomic Claim 395/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0305

Claim: 除了 copper 本身的電阻之外，如果表面粗糙，current 會沿不均勻路徑傳輸，進一步增加 resistance 與 loss。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 396/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0304

Claim: 在更高頻率下，signal 在 copper 中傳輸時會往 trace 表面集中，這種現象稱為 skin effect。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 397/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0303

Claim: Signal 沿 PCB 的 copper traces 傳輸時，會因 copper 的電阻而損失能量。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 398/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0302

Claim: Conductor loss 主要由 copper surface roughness 驅動。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Dielectric loss is driven by the energy absorption nature of the dielectric materials. Dielectric materials, resins and glass fiber cloth, provide insulation and mechanical reinforcement function for the PCB traces. At high frequency, high-speed signal doesn’t simply travel through the copper traces, the signal traves as an electromagnetic wave with electric field extending into the dielectric materials. As the signal propagates, the dielectric absorbs a portion of the energy and dissipates as heat, contributing to insertion loss. Dielectric loss scales with frequency, hence dielectric loss is a dominant limiter of signal performance of long reach PCB traces.

Dielectric loss 來自 dielectric material 吸收能量的特性。Resin、glass fiber cloth 等 dielectric material 為 PCB trace 提供 insulation、mechanical reinforcement。High frequency 下，high-speed signal 不只是沿 copper trace 傳輸，而是以 electromagnetic wave 形式傳播，electric field 也會延伸進 dielectric。Signal 前進時，dielectric 會吸收一部分能量並轉成 heat，因此形成 insertion loss。Dielectric loss 會隨 frequency 增加，因此對 long-reach PCB trace 而言，是限制 signal performance 的主要因素之一。

Atomic Claim 399/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT03

Claim: Resins provide insulation for PCB traces.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 400/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0306

Claim: Dielectric loss 來自 dielectric materials 吸收能量的特性。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 401/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT01

Claim: Dielectric materials provide insulation for PCB traces.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 402/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0308

Claim: 在高頻下，high-speed signal 不只是沿 copper traces 傳輸，而是以 electromagnetic wave 形式傳播，其 electric field 會延伸進 dielectric materials。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 403/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT06

Claim: Glass fiber cloth provide mechanical reinforcement for PCB traces.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 404/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0309

Claim: Signal 傳播時，dielectric 會吸收部分能量並以熱的形式耗散，進而造成 insertion loss。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 405/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT04

Claim: Resins provide mechanical reinforcement for PCB traces.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 406/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT02

Claim: Dielectric materials provide mechanical reinforcement for PCB traces.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 407/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0307::SPLIT05

Claim: Glass fiber cloth provide insulation for PCB traces.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 408/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0310

Claim: Dielectric loss 會隨 frequency 上升，因此是 long-reach PCB traces signal performance 的主要限制因素。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Geometry loss describes the insertion loss incurred from abrupt structures of the PCB traces. Real PCB channels include many abrupt structures, such as vias and layer swaps. These are like bumps in a highway, and signals could reflect backward and be interrupted increasing insertion loss.

Geometry loss 指的是 PCB trace 中突變 structure 帶來的 insertion loss。Real PCB channel 裡有很多不連續結構，例如 via、layer swap，就像高速公路上的顛簸；signal 可能因此向後反射或被打斷，增加 insertion loss。

Atomic Claim 409/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0311

Claim: Geometry loss 指的是 PCB traces 中 abrupt structures 所造成的 insertion loss。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 410/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0314

Claim: Vias and layer changes along a PCB signal path can reflect and interrupt signals, increasing insertion loss.
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 411/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0312

Claim: 實際的 PCB channels 含有許多 abrupt structures，例如 vias 與 layer swaps。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Another factor that affects signal performance is cross-talk. Given the increase in the number of I/Os per GPU, lane density in the PCB also increases. Cross-talk describes the scenario where the copper traces are too close to each other and the signal from one lane affects the signal in a neighboring lane. Some copper traces are designed for power as well. When the power lanes are too close to the signal lanes, noise from the power lanes can also modulate the signal as well.

另一個影響 signal performance 的因素是 cross-talk。GPU I/O 數量增加後，PCB lane density 也提高；當 copper trace 太靠近，一條 lane 的 signal 會干擾旁邊 lane，這就是 cross-talk。有些 copper trace 用來供 power，如果 power lane 太靠近 signal lane，power noise 也可能調變 signal。

Atomic Claim 412/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0317

Claim: Cross-talk 指的是 copper traces 太靠近時，一條 lane 的 signal 會影響相鄰 lane signal 的情況。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 413/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0319

Claim: 當 power lanes 與 signal lanes 太靠近時，power lanes 的 noise 也可能調變 signal。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 414/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0315

Claim: 另一個影響 signal performance 的因素是 cross-talk。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 415/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0318

Claim: 部分 copper traces 也被設計用來傳輸 power。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 416/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0316

Claim: 隨著每顆 GPU 的 I/O 數量增加，PCB 的 lane density 也會提高。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

In conclusion, insertion loss scales with signal frequency, and high-speed signal suffers more insertion loss from PCB than from fly over cables. Hence, as traditional CPU servers upgrade to higher signaling frequencies such as upgrading to newer PCIe generations, the CPU server design increases the adoption of fly over cables to compensate for insertion loss from the PCB. The alternative solution would be upgrading PCB materials, however, fly over cables are more cost effective and remain feasible for traditional server applications.

總結來說，insertion loss 會隨 signal frequency 增加，而且 high-speed signal 走 PCB 的 loss 比 flyover cable 更大。因此傳統 CPU server 升級到更高 signaling frequency，例如新版 PCIe generation 時，通常會增加 flyover cable 使用量來補償 PCB insertion loss。另一個解法是升級 PCB material，但對傳統 server application 而言，flyover cable 通常更 cost-effective、也仍然可行。

Atomic Claim 417/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0323::RESEG01

Claim: flyover cables 在 traditional server applications 中仍然可行。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
開啟本版 Claim 與證據

Atomic Claim 418/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0322::RESEG02

Claim: 對 traditional server applications 而言，flyover cables 相較升級 PCB materials 更具成本效益。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
開啟本版 Claim 與證據

Atomic Claim 419/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0322::RESEG01

Claim: 相對於採用 flyover cables，另一種處理 PCB insertion loss 的方案是升級 PCB materials。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
開啟本版 Claim 與證據

Atomic Claim 420/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0320::SPLIT01

Claim: Insertion loss scales with signal frequency.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 421/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0321

Claim: 因此，traditional CPU servers 升級到更高 signaling frequencies、例如新版 PCIe generations 時，會增加採用 flyover cables，以補償 PCB 的 insertion loss。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 422/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0320::SPLIT02

Claim: High-speed signals suffer more insertion loss on PCB than on flyover cables.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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For VR NVL72, the design has turned toward cableless given the higher density and manufacturing complexity of AI server. The cost saved on improving higher manufacturing yields and assembly time reduction more than offsets the higher cost of the upgraded PCB materials. It is critical that all the factors that contribute towards insertion loss in the PCB are mitigated, hence PCB material upgrades are necessary for VR NVL72. We break down the cost by component here ↗.

VR NVL72 則因 AI server density 與 manufacturing complexity 更高，design 轉向 cableless。透過提升 manufacturing yield、縮短 assembly time 所省下的成本，足以抵銷 upgraded PCB material 的較高成本。由於所有會造成 PCB insertion loss 的因素都必須盡量被壓低，因此 VR NVL72 升級 PCB material 是必要的。我們在這裡 ↗ 逐項拆解 component cost。

Atomic Claim 423/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0324

Claim: 對 VR NVL72 而言，由於 AI server 的 density 與 manufacturing complexity 更高，設計方向轉向 cableless。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 424/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0325

Claim: 提高 manufacturing yield 與縮短 assembly time 所節省的成本，足以超過升級 PCB materials 帶來的額外成本。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 425/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0326

Claim: 必須降低 PCB 中所有造成 insertion loss 的因素，因此 VR NVL72 必須升級 PCB materials。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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PCB Materials Upgrade and Area Growth

PCB content value in VR NVL72 will grow significantly compared to that of GB200/GB300. The two main drivers of this content growth are significant material upgrades and the notable increase of high-end PCB area and layers. Our VR NVL72 Component BoM and Power Budget Model ↗ has provides the $ content breakdown of high end CCL and PCB content for VR NVL72 vs GB200/GB300.

VR NVL72 的 PCB content value 相較 GB200／GB300 會大幅增加，主要有兩個 driver：material 明顯升級，以及 high-end PCB area、layer 數量大幅增加。VR NVL72 Component BoM and Power Budget Model ↗ 提供 VR NVL72 vs GB200／GB300 的 high-end CCL、PCB $ content 詳細拆解。

Atomic Claim 426/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0328::RESEG01

Claim: VR NVL72 的 PCB content growth 其中一個主要 driver 是顯著的 material upgrades。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 427/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0327

Claim: VR NVL72 的 PCB content value 相較 GB200／GB300 將顯著成長。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 428/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0329::RESEG01

Claim: VR NVL72 的 PCB content growth 另一個主要 driver，是 high-end PCB area 與 layer count 顯著增加。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Source: VR NVL72 Component BoM and Power Budget Model ↗

On the material side, CCL content upgrades from M7 to M8/M9 drives material upgrades. Copper foil is upgraded to HVLP4 across the board for the main compute and networking boards. A glass fiber cloth upgrade is necessary to reduce dielectric loss, but whether quartz cloth (Q glass) is necessary remains a debate. Below let’s discuss the materials upgrade and the key considerations behind the adoption of each material.

Material 方面，CCL 從 M7 升到 M8／M9。主要 compute、networking board 的 signal layer，copper foil 全面升級到 HVLP4。為降低 dielectric loss，glass fiber cloth 也必須升級；至於是否真的需要 quartz cloth（Q glass），目前仍有爭議。下面會討論 material upgrade，以及各種材料 adoption 背後的關鍵考量。

Atomic Claim 429/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0333

Claim: Whether VR NVL72 boards require quartz cloth (Q glass) remains debated.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 430/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0330

Claim: 在 material 方面，CCL content 從 M7 升級到 M8/M9，帶動 material upgrade。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 431/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0331

Claim: In the VR NVL72 board-material upgrade, main compute and networking boards use HVLP4 copper foil.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 432/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0332

Claim: 為降低 dielectric loss，需要升級 glass fiber cloth。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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The Table below shows the CCL classification and PCB specification of each main board in Blackwell versus Rubin.

下表整理 Blackwell 與 Rubin 各主要 board 的 CCL classification 與 PCB specification。

Atomic Claim 433/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-NVSwitch-WUS

Claim: The February table lists WUS as a VR NVL72 NVSwitch PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 434/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-NVSwitch-TTM

Claim: The February table lists TTM as a VR NVL72 NVSwitch PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 435/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCLSUP-midplane

Claim: The February table lists EMC as a VR NVL72 midplane CCL supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 436/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-daughter-ISU

Claim: The February table lists ISU as a VR NVL72 daughter/peripheral PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 437/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-NVSwitch-ISU

Claim: The February table lists ISU as a VR NVL72 NVSwitch PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 438/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-daughter-TTM

Claim: The February table lists TTM as a VR NVL72 daughter/peripheral PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 439/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-midplane-ISU

Claim: The February table lists ISU as a VR NVL72 midplane PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 440/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCL-NVSwitch

Claim: The February VR NVL72 CCL table specifies M8.5 (HVLP4, LDK2) for NVSwitch.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 441/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCB-midplane

Claim: The February VR NVL72 PCB table lists 44L PTH for midplane.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 442/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-daughter-WUS

Claim: The February table lists WUS as a VR NVL72 daughter/peripheral PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 443/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCLSUP-NVSwitch

Claim: The February table lists EMC as a VR NVL72 NVSwitch CCL supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 444/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-HPM-Unimicron

Claim: The February table lists Unimicron as a VR NVL72 HPM PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 445/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCL-Strata

Claim: The February VR NVL72 CCL table specifies M8.5/M6 (HVLP4, LDK2) for Strata/HPM.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 446/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCLSUP-daughter

Claim: The February table lists EMC as a VR NVL72 daughter/peripheral CCL supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 447/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCB-NVSwitch

Claim: The February VR NVL72 PCB table lists 32L PTH for NVSwitch.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 448/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-GPU_ABF_AREA

Claim: The February table specifies VR NVL72 gpu abf area as 8,051mm².
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 449/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-GPU_ABF_LAYERS

Claim: The February table specifies VR NVL72 gpu abf layers as 18 layers.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 450/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCB-Strata

Claim: The February VR NVL72 PCB table lists 26L HDI (6+14+6) for Strata/HPM.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 451/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-midplane-WUS

Claim: The February table lists WUS as a VR NVL72 midplane PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 452/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-midplane-TTM

Claim: The February table lists TTM as a VR NVL72 midplane PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 453/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CCLSUP-HPM

Claim: The February table lists Doosan as a VR NVL72 HPM CCL supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 454/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCBSUP-HPM-VGT

Claim: The February table lists VGT as a VR NVL72 HPM PCB supplier.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 455/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-PCB-daughter

Claim: The February VR NVL72 PCB table lists 20L PTH for daughter/peripheral boards.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

The classification of CCL materials is determined by its dielectric constant (Dk) and dissipation factor (Df) at a given frequency. Insertion loss is lower at lower Dk and Df value. The common classification is anchored to the Megtron series from Panasonic as they have been setting the industry standard. When people describe the CCL as M7 classification it usually means it matches the same Dk and Df specifications as Megtron 7 of Panasonic.

CCL material classification 由特定 frequency 下的 dielectric constant（Dk）與 dissipation factor（Df）決定；Dk、Df 越低，insertion loss 越低。業界常見 classification 以 Panasonic Megtron 系列為基準，因為它一直在設定 industry standard。當大家說 CCL 是 M7 class，通常表示 Dk、Df specification 與 Panasonic Megtron 7 相近。

Atomic Claim 456/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0336

Claim: Dk 與 Df 越低，insertion loss 也越低。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 457/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0335

Claim: CCL materials 的 classification，是依特定 frequency 下的 dielectric constant（Dk）與 dissipation factor（Df）決定。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 458/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0337

Claim: 業界常見的 classification 以 Panasonic 的 Megtron series 為基準，因為該系列一直在設定 industry standard。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 459/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0338

Claim: 當 CCL 被描述為 M7 classification，通常代表其 Dk 與 Df specifications 與 Panasonic Megtron 7 相同。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Source: Panasonic

Copper foil content in Rubin is upgraded from HVLP2 to HVLP4 grade copper foil for the signal layers. As discussed earlier, due to the skin effect, smoother copper foil equals to lower insertion loss. HVLP is the classification of copper foil standing for Ultra-Low Profile Copper Foil. The higher the HVLP grade equals to lower surface roughness.

Rubin signal layer 的 copper foil 從 HVLP2 升到 HVLP4。如前面 skin effect 所述，copper surface 越平滑，insertion loss 越低。HVLP 是 Ultra-Low Profile Copper Foil 的分類，grade 越高代表 surface roughness 越低。

Atomic Claim 460/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0341

Claim: HVLP 是 copper foil 的 classification，代表 Ultra-Low Profile Copper Foil。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 461/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0342

Claim: HVLP grade 越高，surface roughness 越低。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 462/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0340

Claim: 如前述 skin effect 所示，copper foil 越平滑，insertion loss 越低。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 463/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0339

Claim: Rubin 的 signal layers 將 copper foil 從 HVLP2 升級到 HVLP4 grade。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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For the power layers, the additional layers in Strata compared to Blackwell are mostly power layers to accommodate more power going into the GPU. By adding more dedicated power layers, cross talk is reduced as power layers and signal layers are separated. Power layer copper foils are much thicker to insulate the current travelling through it.

Power layer 方面，Strata 相較 Blackwell 增加的 layer，大多是用來承受 GPU 更高 power 的 dedicated power layer。增加 power layer 後，power、signal layer 可以更好分離，降低 cross-talk。Power layer 的 copper foil 也會厚很多，以承載更大的 current。

Atomic Claim 464/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0364

Claim: 關於 PCB：增加 dedicated power layers 並把 power layers 與 signal layers 分離，可降低 cross-talk。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 465/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0343

Claim: 在 power layers 方面，Strata 相較 Blackwell 增加的 layers 多數是 power layers，用來承載更多送入 GPU 的 power。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 466/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0346

Claim: The source describes power-layer copper foils as thicker “to insulate the current”; this is retained as source wording, not a validated electrical explanation.
Frame: CLAIM_ONLY · Mode: ATTRIBUTED · Mapping: PARTIAL
開啟本版 Claim 與證據

The glass fiber cloth upgrade aims to reduce the dielectric constant of CCL. Beside glass fiber cloth, resin is also a key factor contributing to dielectric constant. To achieve a desirable dielectric constant, the CCL makers have their unique recipes to their formulation of the two dielectric materials in the CCL. Currently, debate around the CCL spec is around the adoption of Quartz cloth (Q glass).

Glass fiber cloth 升級的目標，是降低 CCL dielectric constant。除了 glass fiber cloth，resin 也是 Dk 的重要決定因素，因此不同 CCL maker 都有自己配方，調整兩種 dielectric material 的比例，以達到目標 dielectric constant。目前 CCL spec 的主要爭議，就在是否導入 Quartz cloth（Q glass）。

Atomic Claim 467/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0348

Claim: 除了 glass fiber cloth 之外，resin 也是影響 dielectric constant 的重要因素。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 468/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0350

Claim: 目前 CCL spec 的主要爭議在於是否採用 Quartz cloth（Q glass）。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 469/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0349

Claim: 為了達到理想的 dielectric constant，各家 CCL makers 對 CCL 中兩種 dielectric materials 的配方都有自己的 recipe。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 470/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0347

Claim: Glass fiber cloth upgrade 的目標是降低 CCL 的 dielectric constant。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Quartz cloth is the next generation material that replaces the glass fiber cloth materials as the reinforcing layer, pushing dielectric constant even lower. Besides lower dielectric constant, quartz cloth also has the benefits of being stronger, more temperature resistance, and having a lower CTE. On the other hand, the cost is multiples higher than that of the highest-grade glass fiber cloth and is much harder to process at the PCB manufacturing level, leading to worse yield.

Quartz cloth 是用來取代 glass fiber cloth reinforcing layer 的 next-generation material，可以把 dielectric constant 再往下降。除了低 Dk，quartz cloth 還更強、更耐高溫、CTE 更低；但成本是最高階 glass fiber cloth 的數倍，而且 PCB manufacturing processing 難很多，yield 也較差。

Atomic Claim 471/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0351

Claim: Quartz cloth 是下一代 reinforcing-layer material，可取代 glass fiber cloth，並把 dielectric constant 進一步降低。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 472/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0372

Claim: The source describes quartz cloth as more temperature-resistant than glass fiber cloth.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 473/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0373

Claim: The source describes quartz cloth as having lower CTE than glass fiber cloth.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 474/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0355

Claim: Quartz cloth is harder to process at the PCB manufacturing level than the highest-grade glass fiber cloth, leading to worse yield.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 475/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0371

Claim: The source describes quartz cloth as stronger than glass fiber cloth.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 476/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0354

Claim: 另一方面，quartz cloth 成本是 highest-grade glass fiber cloth 的數倍。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Within VR NVL72, Quartz is initially adopted for the Orchid board and the midplane to allow the longest distance PCIe Gen 6 signal traveling through these two boards with as little insertion loss as possible. However, given the cost of the Quartz cloth and the difficulty in Q cloth processing, Nvidia is currently exploring the option of downgrading back to glass fiber cloth. The final decision is pending on the signal performance with the downgraded glass fiber cloth.

VR NVL72 一開始在 Orchid board、midplane 採 Quartz，目的是讓最長距離的 PCIe Gen6 signal 穿過這兩塊 board 時，insertion loss 盡可能低。不過考量 quartz cloth 成本高、Q cloth processing 困難，Nvidia 現在也在評估降回 glass fiber cloth。最終決定要看 downgrade 後的 signal performance 是否仍達標。

Atomic Claim 477/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0358

Claim: 不過考量 Quartz cloth 的成本與 Q-cloth processing 難度，Nvidia 目前正在評估降回 glass fiber cloth 的方案。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 478/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0356::RESEG01

Claim: 在 VR NVL72 中，Quartz cloth 最初用於 Orchid board。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 479/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0357::RESEG01

Claim: VR NVL72 在 Orchid board 與 midplane 最初採用 Quartz cloth，是為了讓最長距離的 PCIe Gen 6 signal 穿過這兩塊 boards 時，insertion loss 盡可能低。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 480/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0356::RESEG02

Claim: 在 VR NVL72 中，Quartz cloth 最初用於 midplane。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 481/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0359

Claim: The VR NVL72 quartz-versus-glass material decision remains pending results from signal-performance tests using downgraded glass cloth.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

Beside material upgrade, the other driver of PCB content value is the increase of high end PCB area coverage. In Grace Blackwell, the only boards with high end material are the Bianca board with M7 grade CCL and the NVSwtich board with M8 grade CCL, leaving front half of the compute tray uncovered by high end PCB board. For VR NVL72, the Orchid board and the midplane board increases the high end PCB board area in the compute tray covering the front half of the chassis. With the Strata board bigger than the Bianca board and the extra peripheral boards in the compute tray, we estimate that the area of high end PCB board increases by ~2.3 times from GB300 to VR NVL72. As the tables shows, the Orchid board is the main contributor to the delta of total high-end PCB area between GB300 and VR NVL72 rack.

除了 material upgrade，PCB content value 另一個 driver 是 high-end PCB area 大幅增加。Grace Blackwell 只有 Bianca board 使用 M7 CCL、NVSwitch board 使用 M8 CCL，因此 compute tray 前半部沒有 high-end PCB。VR NVL72 新增 Orchid board、midplane board，把 high-end PCB coverage 延伸到 chassis 前半部；再加上 Strata board 比 Bianca 更大、compute tray 還多了額外 peripheral board，我們估計從 GB300 到 VR NVL72，high-end PCB board area 增加約 2.3x。如下表，Orchid board 是 GB300 vs VR NVL72 rack high-end PCB total area 差距的主要來源。

Atomic Claim 482/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0360

Claim: 除了 material upgrade，PCB content value 的另一個驅動因素是 high-end PCB area coverage 增加。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 483/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0364

Claim: Orchid board 是 GB300 與 VR NVL72 rack 之間 total high-end PCB area 差異的主要貢獻者。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 484/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0361::SPLIT03

Claim: In Grace Blackwell, only the Bianca and NVSwitch boards use high-end materials, leaving the front half of the compute tray uncovered by high-end PCB.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 485/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0361::SPLIT01

Claim: In Grace Blackwell, the Bianca board uses M7-grade CCL.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 486/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0362

Claim: 對 VR NVL72 而言，Orchid board 與 midplane board 增加了 compute tray 的 high-end PCB board area，覆蓋 chassis 前半部。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 487/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0361::SPLIT02

Claim: In Grace Blackwell, the NVSwitch board uses M8-grade CCL.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 488/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0363

Claim: 由於 Strata board 比 Bianca board 更大，加上 compute tray 額外的 peripheral boards，SemiAnalysis 估計 high-end PCB board area 從 GB300 到 VR NVL72 增加約 2.3 倍。
Frame: NARY_RELATION · Mode: ESTIMATED · Mapping: COMPLETE
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Our VR NVL72 Component BoM and Power Budget Model ↗ has provides the $ content breakdown of high end CCL and PCB content for VR NVL72 vs GB200/GB300.

VR NVL72 Component BoM and Power Budget Model ↗ 提供 VR NVL72 與 GB200／GB300 的 high-end CCL、PCB $ content 詳細拆解。

Compute Tray: Thermal

VR NVL72 takes liquid cooling to the next level. The VR NVL72 compute tray is 100% liquid cooled, whereas GB200 and GB300 compute trays adopt a hybrid of 85% liquid cooling and 15% air cooling. As a result of this, fans are removed from the compute tray and the cold plate coverage increases to remove heat from the front half of the chassis. An internal manifold will be placed in the middle of the chassis to distribute inlet coolant to the various modules and to collect the outlet coolant. Each of the modules within the compute tray will have a cold plate module attached. Each cold plate module connects to the internal manifolds via MQD (a smaller form factor quick disconnect specification standard by Nvidia for compact area application within the compute tray).

VR NVL72 把 liquid cooling 再推進一級：compute tray 變成 100% liquid cooled；GB200、GB300 則是約 85% liquid cooling + 15% air cooling 的 hybrid。結果 fan 從 compute tray 移除，cold plate coverage 也擴大到 chassis 前半部。Chassis 中央會放 internal manifold，把 inlet coolant 分配到各 module，再收集 outlet coolant；compute tray 內每個 module 都有自己的 cold plate module，並透過 MQD 連到 internal manifold。MQD 是 Nvidia 為 compute tray 內 compact application 標準化的較小型 quick-disconnect specification。

Atomic Claim 489/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0368

Claim: 因此，compute tray 中的 fans 被移除。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 490/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0372::SPLIT01

Claim: Each VR NVL72 cold plate module connects to the internal manifolds via MQD.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 491/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0367

Claim: GB200 與 GB300 compute trays 採用 85% liquid cooling、15% air cooling 的 hybrid cooling。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 492/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0366

Claim: VR NVL72 compute tray 採 100% liquid cooling。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 493/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0370

Claim: An internal manifold in the center of the VR NVL72 compute tray distributes inlet coolant to modules and collects outlet coolant.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 494/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0372::SPLIT02

Claim: MQD is Nvidia smaller-form-factor quick-disconnect specification for compact areas within the compute tray.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 495/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0371

Claim: compute tray 內每個 module 都會附上一個 cold plate module。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 496/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0369

Claim: cold plate coverage 增加，以移除 chassis 前半部的熱。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

The coolant enters the compute tray via UQD from the left rear side of the chassis. Then, the coolant enters the internal manifold via a tube, where the coolant is distributed to all the modules. The coolant collects the heat from the different modules and re-enters the internal manifold. Finally, the coolant exits the compute tray via UQD at the rear right side of the chassis.

Coolant 從 chassis 左後方透過 UQD 進入 compute tray，再經 tube 進入 internal manifold，由 manifold 分配到所有 module。Coolant 吸收各 module heat 後重新回到 internal manifold，最後從 chassis 右後方的 UQD 離開 compute tray。

Atomic Claim 497/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0376

Claim: 最後 coolant 從 chassis 右後側透過 UQD 離開 compute tray。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 498/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0375

Claim: In VR NVL72, coolant collects heat from modules and returns to the internal manifold.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 499/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0373

Claim: Coolant 從 chassis 左後側透過 UQD 進入 compute tray。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 500/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0374

Claim: In VR NVL72, coolant enters the internal manifold through a tube before being distributed to modules.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

Several upgrades are also made on the cold plate for VR NVL72. For each Strata module, the cold plate will be provided as a single module covering the entire Strata board including two Rubin GPUs, one Vera CPU, SOCAMM modules, and the various VRM components. The cold plate of the Rubin GPU is upgraded to a “micro-channel cold plate” (MCCP). Essentially, the pitch between the channels in the cold plate is reduced to to 100 micron from 150 micron. This increases the surface area and increases the thermal dissipation capacity of the cold plate. Also, there will be a layer of gold plated on the surface contacting the Rubin GPU. The reason for this is to prevent corrosion of the copper from the liquid metal Indium TIM2.

VR NVL72 的 cold plate 也做了多項升級。每個 Strata module 會使用一整塊 cold plate module，覆蓋整張 Strata board，包括兩顆 Rubin GPU、一顆 Vera CPU、SOCAMM module，以及各種 VRM component。Rubin GPU 的 cold plate 升級成 micro-channel cold plate（MCCP），channel pitch 從 150 micron 縮小到 100 micron，增加 surface area、提高 thermal dissipation capacity。和 Rubin GPU 接觸的表面還會鍍一層 gold，用來避免 liquid-metal Indium TIM2 腐蝕 copper。

Atomic Claim 501/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT02

Claim: The single Strata cold plate module covers two Rubin GPUs.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 502/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0379

Claim: Rubin GPU 的 cold plate 升級為 micro-channel cold plate（MCCP）。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 503/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0384

Claim: Gold plating on the Rubin cold-plate contact surface prevents copper corrosion from liquid-metal indium TIM2.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 504/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT04

Claim: The single Strata cold plate module covers SOCAMM modules.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 505/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0382::RESEG01

Claim: 增加 surface area 會提高 cold plate 的 thermal dissipation capacity。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 506/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT03

Claim: The single Strata cold plate module covers one Vera CPU.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 507/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT05

Claim: The single Strata cold plate module covers VRM components.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 508/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0380

Claim: The Rubin micro-channel cold plate reduces channel pitch from 150 micrometres to 100 micrometres.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 509/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0378::SPLIT01

Claim: The Strata cold plate is provided as one module covering the entire Strata board.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 510/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0381::RESEG01

Claim: 將 cold plate 的 channel pitch 從 150 micron 縮小到 100 micron，會增加其 surface area。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 511/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0383

Claim: 此外，與 Rubin GPU 接觸的表面會鍍上一層 gold。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

Beyond the Strata module, the modules at the front of the Chassis will also have a cold plate module attached. Each Orchid module will have a cold plate module covering the CX-9, the E1.S SSD, the transceiver cages and the various VRMs. The cold plate and the board will be less than 0.5U tall as two Orchid modules are stacked on top of each other in a 1U chassis. Each pair of Orchid modules shares only a pair of QD from the manifold. There will be another set of manifolds that distribute the coolant to the top and the bottom cold plates for the pair of Orchid modules. In our VR NVL72 Component BoM and Power Budget Model ↗ we have the content for all the various thermal components including the cold plate modules, manifolds, and the Quick Disconnects.

除了 Strata module，chassis 前方各 module 也都有 cold plate module。每個 Orchid module 的 cold plate 會覆蓋 CX-9、E1.S SSD、transceiver cage 與各種 VRM。因兩個 Orchid module 要上下堆疊在 1U chassis 中，所以 cold plate + board 高度都低於 0.5U。每一對 Orchid module 只共享一對 manifold QD，另外還會有一組 manifold，把 coolant 分到上下兩塊 cold plate。VR NVL72 Component BoM and Power Budget Model ↗ 收錄各種 thermal component，包括 cold plate module、manifold、Quick Disconnect 的 content。

Atomic Claim 512/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0386::SPLIT04

Claim: Each Orchid module cold plate covers the VRMs.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 513/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0386::SPLIT02

Claim: Each Orchid module cold plate covers the E1.S SSD.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 514/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0388

Claim: 每一對 Orchid modules 只共用一對來自 manifold 的 QD。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 515/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0389

Claim: 另有一組 manifolds，將 coolant 分配到這對 Orchid modules 的上、下 cold plates。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 516/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0386::SPLIT01

Claim: Each Orchid module cold plate covers CX-9.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 517/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0386::SPLIT03

Claim: Each Orchid module cold plate covers the transceiver cages.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 518/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0387

Claim: cold plate 與 board 的高度都會低於 0.5U，因為 2 個 Orchid modules 會上下堆疊在 1U chassis 中。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 519/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0385

Claim: 除了 Strata module，chassis 前端的 modules 也會附上 cold plate module。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

Previously, cold plates were assembled at the L10 assembly level where the various components are put into place in the chassis. Given the modular approach, the cold plates need to be more tightly integrated with the module itself. Hence, the cold plate will be attached at the L6 assembly level right after the PCBA process. This increases the assembly efficiency as the assembly at L10 is simplified to slotting in the completed modules into the corresponding connectors and quick disconnects.

過去 cold plate 通常在 L10 assembly 階段才裝，也就是各 component 放入 chassis 時才一起組裝。但 modular approach 下，cold plate 必須和 module 本身更緊密整合，因此改在 PCBA 後的 L6 assembly 階段就先裝上。這能提高 assembly efficiency，因為到了 L10 只需要把完整 module 插進對應 connector 與 quick disconnect。

Atomic Claim 520/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0390

Claim: 過去 cold plates 是在 L10 assembly level 組裝，也就是把各種 components 裝入 chassis 的階段。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 521/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0391

Claim: 採用 modular approach 後，cold plates 必須與 module 本體更緊密整合。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 522/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0392

Claim: 因此，cold plate 會在 PCBA process 後、L6 assembly level 就先安裝。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 523/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0393

Claim: 這會提高 assembly efficiency，因為 L10 assembly 被簡化為把完成的 modules 插入對應 connectors 與 quick disconnects。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Compute Tray: Power Delivery

At the compute tray level, 50VDC power enters the compute tray via the busbar clips at the back of the chassis. Then power travels to the middle of the chassis via the internal busbar cables. From the internal busbar cables, the power path is split into three destinations. The first and second path goes to the left and the right Strata Board, where the internal busbar cable feeds 50VDC power to the Strata Board directly. The third path goes to the power distribution module at the front of the chassis. The internal busbar cables will feed 50VDC power to a busbar device that travels under the PCB midplane to connect to the power distribution board (PDB) on the other side of the PCB midplane. This differs from Grace Blackwell, where 50VDC power goes directly to the PDB. Then, the PDB feeds 12VDC to all the boards in the compute tray.

Compute tray level 上，50VDC 從 chassis 後方 busbar clip 進入，再透過 internal busbar cable 送到 chassis 中央；之後 power path 分成三路。前兩路分別去左右 Strata Board，internal busbar cable 直接把 50VDC 餵給 Strata Board。第三路則前往 chassis 前方的 power distribution module：internal busbar cable 把 50VDC 送到一個從 PCB midplane 下方穿過的 busbar device，再連到 midplane 另一側的 power distribution board（PDB）。這和 Grace Blackwell 不同；Grace Blackwell 是 50VDC 直接進 PDB，再由 PDB 將 12VDC 分配到 compute tray 所有 board。

Atomic Claim 524/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0398

Claim: The third VR NVL72 compute-tray power path feeds the power-distribution module at the front of the chassis.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 525/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0397

Claim: 第一、第二條 path 分別前往左、右 Strata Board，由內部 busbar cable 直接供應 50VDC power。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 526/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0400

Claim: 這與 Grace Blackwell 不同；在 Grace Blackwell 中，50VDC power 會直接送到 PDB。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 527/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0399

Claim: Internal busbar cables 先提供 50VDC 給一個 busbar device；該 device 從 PCB midplane 下方穿過，連接到 midplane 另一側的 power distribution board（PDB）。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 528/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0395

Claim: 接著 power 透過內部 busbar cables 傳到 chassis 中央。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 529/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0394

Claim: 在 compute tray 層級，50VDC power 會透過 chassis 後方的 busbar clips 進入 compute tray。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 530/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0401

Claim: 接著 PDB 向 compute tray 中所有 boards 提供 12VDC。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 531/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0396

Claim: 從內部 busbar cables 開始，power path 分成三個 destinations。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

50VDC enters the Strata Board via one of the 50V power connectors on both sides of the Strata board. 50VDC is stepped down to 12VDC by the IBC module at the bottom of the Strata Board. Then the 12VDC will be stepped down to 1VDC by the VRM before feeding into the Rubin GPU and Vera CPU. Strata directly receives 50VDC whereas the Bianca board of Grace Blackwell receives 12VDC from the PDB. As the Strata board draws around 4800W of power (equivalent to the TDP of half a general server rack) versus Bianca at 3000W, it is necessary to deliver power to the board at a higher voltage. The benefit of moving 50VDC-12VDC conversion closer is to the reduce current and increase transmission efficiency. 96 Amps at 50V has 17x lower power loss than 400A at 12V due to the quadratic relationship between power loss and current.

50VDC 會從 Strata Board 左右兩側其中一個 50V power connector 進入，再由 board 底部 IBC module 降到 12VDC，接著由 VRM 再降到約 1VDC，供 Rubin GPU、Vera CPU 使用。Strata 是直接接收 50VDC；Grace Blackwell 的 Bianca board 則從 PDB 接 12VDC。Strata power draw 約 4,800W——相當於半個一般 server rack 的 TDP——而 Bianca 約 3,000W，因此必須以較高 voltage 將 power 送進 board。把 50VDC→12VDC conversion 移近 load，可以降低 current、提高 transmission efficiency。50V 下 96A 的 power loss，比 12V 下 400A 低約 17x，因為 power loss 和 current 呈平方關係。

Atomic Claim 532/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0406::SPLIT02

Claim: The source compares around 4,800W of Strata power with the TDP of half a general-server rack.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 533/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0403

Claim: 位於 Strata Board 底部的 IBC module 將 50VDC 降壓至 12VDC。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 534/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0408

Claim: 在 power loss 與 current 呈平方關係下，50V、96A 的 power loss 比 12V、400A 低 17 倍。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 535/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0402

Claim: 50VDC 會透過 Strata Board 兩側的 50V power connectors 進入 Strata Board。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 536/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0407::SPLIT01

Claim: Moving the 50VDC-to-12VDC conversion closer to Strata reduces transmission current.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 537/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0405

Claim: Strata 直接接收 50VDC；相較之下，Grace Blackwell 的 Bianca board 從 PDB 接收 12VDC。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 538/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0406::SPLIT01

Claim: The Strata board draws around 4,800W, versus about 3,000W for Bianca.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 539/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0406::SPLIT03

Claim: Strata higher power draw versus Bianca requires delivering power to the board at higher voltage.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 540/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0407::SPLIT02

Claim: Moving the 50VDC-to-12VDC conversion closer to Strata improves transmission efficiency.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 541/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0404

Claim: 之後 VRM 再把 12VDC 降至 1VDC，供給 Rubin GPU 與 Vera CPU。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

We have the volume and ASP for all the power semis for the all the various VRMs contained in the VR NVL72 Component BoM and Power Budget Model ↗.

VR NVL72 Component BoM and Power Budget Model ↗ 裡，我們有所有 VRM 所使用 power semiconductor 的 volume 與 ASP。

Nvidia’s Christmas Present: GB300 & B300 - Reasoning Inference, Amazon, Memory, Supply Chain

Dylan Patel ↗, Myron Xie ↗, and Daniel Nishball ↗

Dylan Patel ↗、Myron Xie ↗、Daniel Nishball ↗

·

2024年12月25日

Read full story ↗

閱讀完整文章 ↗

Power sloshing between Vera and Rubin is still present, a feature carried over from GB300 that we covered in our article above. This enables more efficient power planning by sharing the 4800W provided amongst both GPU and CPU. In GPU demanding loads, 2300W goes to each GPU leaving 200W for the CPU. Vera can then dynamically boost to higher power when GPU demand drops to help minimize GPU idle time while not overprovisioning power.

Vera、Rubin 之間的 power sloshing 仍然存在，是從 GB300 延續下來的 feature。它可以在 CPU、GPU 間共享 4,800W power budget，讓 power planning 更有效率。GPU-heavy workload 時，每顆 GPU 可用 2,300W，CPU 剩約 200W；當 GPU demand 下降，Vera 又可以動態 boost 到更高 power，減少 GPU idle time，同時不需要 overprovision power。

Atomic Claim 542/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0412

Claim: Vera CPU can dynamically boost power when GPU demand falls, reducing GPU idle time without power overprovisioning.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 543/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0410

Claim: 這讓 4,800W power 可以在 GPU 與 CPU 間共享，提升 power planning efficiency。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 544/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0411

Claim: 在 GPU demand 高的負載下，每顆 GPU 分配 2,300W，剩下 200W 給 CPU。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 545/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0409

Claim: Vera 與 Rubin 之間仍保留 power sloshing，這項 feature 從 GB300 延續而來。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

For the modules at the front of chassis - CX-9,BlueField-4, and management - the PDB feeds 12VDC of power to each of the modules. 50VDC l down to 12VDC at the PDB then, via a coper busbar device, the PDB feeds 12VDC to its neighboring modules. The power connector of CX-9 is located near the Paladin HD2 at the top of the modules.

Chassis 前方的 CX-9、BlueField-4、management module 都由 PDB 提供 12VDC。50VDC 在 PDB 降到 12VDC 後，再透過 copper busbar device，供電給相鄰 module。CX-9 的 power connector 位於 module 頂部、靠近 Paladin HD2 的位置。

Atomic Claim 546/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0413::SPLIT02

Claim: The PDB supplies 12VDC to the front-chassis BlueField-4 module.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 547/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0414

Claim: PDB 先將 50VDC 降至 12VDC，再透過 copper busbar device，向鄰近 modules 供應 12VDC。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 548/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0415

Claim: CX-9 的 power connector 位於 module 頂部、靠近 Paladin HD2 的位置。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 549/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0413::SPLIT01

Claim: The PDB supplies 12VDC to the front-chassis CX-9 module.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 550/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0413::SPLIT03

Claim: The PDB supplies 12VDC to the front-chassis management module.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Compute Tray: Mechanical

The mechanical components of the VR NVL72 compute tray are slightly more sophisticated than that of the Grace Blackwell. At the front of the chassis, there is a mechanical structure that separates the front into three sections, with the left and right sections housing the Orchid modules and the middle sections housing the BlueField-4, the power delivery and the management modules. Each of the modules will also have a small metal chassis. The mechanical structure provides a simple guiding mechanism that guides the modules to a blind mate process with the midplane and the internal manifolds.

VR NVL72 compute tray 的 mechanical component 比 Grace Blackwell 稍微複雜。Chassis 前方有 mechanical structure，把前端分成三區：左右區放 Orchid module，中間區放 BlueField-4、power delivery、management module。每個 module 本身也都有小型 metal chassis。這套 mechanical structure 同時提供簡單 guide mechanism，讓 module 可以 blind-mate midplane 與 internal manifold。

Atomic Claim 551/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT01

Claim: A mechanical structure divides the VR NVL72 front chassis into three sections.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 552/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0418

Claim: Each removable VR NVL72 front module has a small metal chassis.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 553/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0419

Claim: Mechanical structure 提供簡單的 guiding mechanism，引導 modules 與 midplane、internal manifolds 進行 blind-mate。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 554/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT03

Claim: The BlueField-4 module occupies the middle section of the VR NVL72 front chassis.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 555/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT02

Claim: Orchid modules occupy the left and right sections of the VR NVL72 front chassis.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 556/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0416

Claim: VR NVL72 compute tray 的 mechanical components，比 Grace Blackwell 稍微更複雜。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 557/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT05

Claim: The management module occupies the middle section of the VR NVL72 front chassis.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 558/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0417::SPLIT04

Claim: The power-delivery module occupies the middle section of the VR NVL72 front chassis.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia, SemiAnalysis

The midplane and the internal manifolds are shipped together as a module. The mechanical design of this module is shown in the picture above. These highlighted mechanical parts acts as a loading mechanism for the modules. These loading mechanisms ensure the modules are well connected to the Paladin connectors and the MQD by applying some force to the modules locking them in place.

Midplane 與 internal manifold 會作為同一個 module 出貨，其 mechanical design 如上圖。圖中標示的 mechanical part 就是 module loading mechanism；它們會對 module 施加一定 force 並鎖定位置，確保 Paladin connector、MQD 都有可靠接合。

Atomic Claim 559/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0422

Claim: VR NVL72 loading mechanisms lock modules in place and ensure reliable engagement with Paladin connectors and MQD interfaces.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 560/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0421

Claim: The highlighted mechanical parts in the VR NVL72 compute-tray illustration serve as module loading mechanisms.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 561/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0420

Claim: midplane 與 internal manifolds 會一起以一個 module 的形式出貨。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Rack Level Infrastructure: Thermal

Beyond the redesigned fanless front chassis and the 100% liquid-cooled compute tray, the most notable point in the Vera Rubin cooling architecture discussion was Jensen’s comment on coolant/water warm temperatures and the use of chillers. For many (for Mr. Market more broadly!) the statement that Vera Rubin can operate with 45C inlet temperatures, potentially avoiding mechanical compressor-based chillers, was viewed as a major surprise for much of the cooling supplier ecosystem. We instead view this as a continuation of existing trends.

除了重新設計的 fanless front chassis 與 100% liquid-cooled compute tray，Vera Rubin cooling architecture 最受注意的其實是 Jensen 對 coolant／water warm temperature 與 chiller 的說法。對很多人——甚至 Mr. Market 整體——來說，Vera Rubin 可以用 45°C inlet temperature 運作、可能不需要 mechanical compressor-based chiller，對 cooling supplier ecosystem 是很大驚喜。我們反而認為，這只是既有 trend 的延續。

Atomic Claim 562/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0426

Claim: Jensen’s comment, as reported by SemiAnalysis, says Vera Rubin can operate at a 45°C coolant inlet temperature.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Vera Rubin will be able to operate at a 45C inlet temperature, but Blackwell is already capable of operating with inlet water temperatures above 40C (see for example Supermicro’s DLC-2 system). Major system vendors such as Lenovo and HPE have also been discussing 100% liquid-cooled architectures operating at 45C since early 2025. In 2024, HPE announced an industrial cooling system based on full liquid cooling, and similar approaches have long been used before in HPC. Lenovo discussed the next generation of its Neptune liquid solution at the 2025 OCP Summit, which is fully liquid-cooled and also uses 45C water.

Vera Rubin 確實可以在 45°C inlet temperature 下運作，但 Blackwell 本來就已能使用 40°C 以上 inlet water，例如 Supermicro DLC-2。Lenovo、HPE 等 major system vendor 從 2025 年初也一直在談 45°C、100% liquid-cooled architecture。HPE 早在 2024 年就發布 full-liquid-cooling industrial cooling system，而類似做法在 HPC 更早就長期存在。Lenovo 在 2025 OCP Summit 討論下一代 Neptune liquid solution，同樣是 fully liquid-cooled、使用 45°C water。

Atomic Claim 563/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0431::RESEG02

Claim: Lenovo 的下一代 Neptune liquid solution 採 fully liquid-cooled architecture。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 564/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0429

Claim: 2024 年，HPE 發布以 full liquid cooling 為基礎的 industrial cooling system。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 565/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0431::RESEG01

Claim: Lenovo 在 2025 OCP Summit 討論下一代 Neptune liquid solution。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 566/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0428

Claim: Lenovo、HPE 等 major system vendors 自 2025 年初起，也一直在討論以 45°C 運行的 100% liquid-cooled architectures。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 567/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0427

Claim: Blackwell 已能在高於 40°C 的 inlet water temperature 下運行。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 568/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0430

Claim: 類似的做法在 HPC 領域早已使用多年。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 569/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0432::RESEG01

Claim: Lenovo 的下一代 Neptune liquid solution 使用 45°C water。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
開啟本版 Claim 與證據

Source: HPE

Consider Schneider’s GB300 Reference Design 111, presented in September 2025, as another example. In this reference design, the datacenter uses a dual-loop architecture: a chilled-water loop dedicated to air cooling (feeding the fan walls) and a separate, higher-temperature loop dedicated to liquid cooling. On the liquid side, the TCS circulates coolant to the cold plates at roughly 40C and returns it at a higher temperature, while the CDU transfers that heat into the facility water loop, which can enter the CDU at approximately 37C.

Schneider 在 2025 年 9 月公布的 GB300 Reference Design 111 也是另一個例子。這套 reference design 使用 dual-loop datacenter architecture：chilled-water loop 專門供 air cooling（fan wall），另一套較高溫 loop 專供 liquid cooling。Liquid side 上，TCS 以約 40°C coolant 供應 cold plate，再以更高 temperature 回流；CDU 則把這些 heat transfer 到 facility water loop，而 facility water 進 CDU 時約可達 37°C。

Atomic Claim 570/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0435

Claim: 在 liquid loop 中，TCS 以約 40°C coolant 供給 cold plates，回水溫度更高；CDU 再把熱傳到 facility water loop，而 facility water 進入 CDU 時約為 37°C。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 571/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0433

Claim: 另一個例子是 Schneider 的 GB300 Reference Design 111，於 2025 年 9 月發表。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 572/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0434

Claim: The cited Schneider datacenter reference design separates chilled-water and warmer liquid-cooling loops.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Source: Schneider

So 45C cooling is not entirely new. Even with this capability, most operators deploying Blackwell are still designing for 20-30C water temperatures. As a rough approximation, current Blackwell inlet temperatures are around room temperature, with outlet temperatures in the 40-50C range. Only a small number of operators, such as Firmus, have removed chillers from the loop (even with systems like GB200) in favor of highly optimized economizer designs where climate permits. Avoiding the compression step in mechanical cooling can deliver meaningful energy efficiency gains.

所以 45°C cooling 並不是全新的概念。即使具備這種能力，多數部署 Blackwell 的 operator 現在仍以 20–30°C water temperature 設計。粗略來說，現有 Blackwell inlet 大約接近 room temperature，outlet 約 40–50°C。真正拿掉 chiller 的 operator 仍只有少數，例如 Firmus；即使 GB200，也是在氣候允許時採高度最佳化 economizer design。避開 mechanical cooling 的 compression step，確實可以得到顯著 energy-efficiency gain。

Atomic Claim 573/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0439

Claim: 只有少數 operators 在 climate 條件允許時，以高度最佳化的 economizer design 取代 loop 中的 chillers。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 574/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0438::EPI02

Claim: As a rough approximation, current Blackwell outlet temperature is in the 40-50C range.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 575/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0436

Claim: 因此，45°C cooling 並不是完全新的概念。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
開啟本版 Claim 與證據

Atomic Claim 576/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0440

Claim: 在 mechanical cooling 中避開 compression step，可以帶來有意義的 energy-efficiency improvement。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 577/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0438::EPI01

Claim: As a rough approximation, current Blackwell inlet temperature is around room temperature.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 578/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0437

Claim: 即使具備較高溫操作能力，多數部署 Blackwell 的 operators 目前仍以 20–30°C water temperature 進行設計。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Now, how does Nvidia cool this heat monster, given that Vera Rubin’s power consumption and heat generation is roughly double that of Blackwell? Before answering, it is worth adding another consideration. Warmer inlet temperatures, while improving energy efficiency, can make cooling more challenging as inlet temperatures approach the maximum outlet temperature (the system’s ceiling temperature) and the delta-T tightens. With less temperature differential, you need higher water/coolant flow to remove the same amount of heat. In Blackwell reference architectures, the ceiling temperature is around 65C (e.g. see the Vertiv GB200 NVL72 reference design).

那 Nvidia 要怎麼冷卻這頭 heat monster？畢竟 Vera Rubin power consumption 與 heat generation 大約都是 Blackwell 的兩倍。在回答前還要加一個考量：較高 inlet temperature 雖能提高 energy efficiency，卻也會讓 cooling 更困難，因為 inlet 越接近 maximum outlet temperature，也就是 system ceiling temperature，delta-T 就越小。Temperature differential 變小時，要移除同樣 heat，就需要更高 water／coolant flow。Blackwell reference architecture 的 ceiling temperature 約 65°C，例如 Vertiv GB200 NVL72 reference design。

Atomic Claim 579/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0443

Claim: 較高的 inlet temperature 雖能提升 energy efficiency，但當 inlet temperature 接近 maximum outlet temperature、delta-T 收窄時，cooling 會變得更困難。
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Atomic Claim 580/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0445

Claim: 在 Blackwell reference architectures 中，ceiling temperature 約為 65°C。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 581/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0444

Claim: 當 temperature differential 較小時，要移除相同熱量，就需要更高的 water/coolant flow。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Source: Vertiv

Although NVIDIA initially did not formally publish full specifications for Vera Rubin’s liquid cooling system, we believe the platform will support maximum coolant return temperatures up to 65C. This aligns with Nvidia’s warm-water operating envelope, and while the exact implication for delta-T depends on the chosen supply setpoint and flow control strategy, we can expect a slightly tighten delta-T. The pressure envelope is expected to be unchanged versus GB200, with maximum operating pressure of 72 psig (5 bar) and minimum burst pressure of 217 psig (15 bar), aligning with OCP’s MGX rack-level liquid-cooling specification.

雖然 NVIDIA 一開始沒有正式公布 Vera Rubin liquid-cooling system 的完整 specification，我們認為 platform 會支援最高約 65°C coolant return temperature。這符合 Nvidia warm-water operating envelope；實際 delta-T 要看供水 setpoint 與 flow-control strategy，但可以預期 delta-T 會稍微收窄。Pressure envelope 預計和 GB200 相同：maximum operating pressure 72 psig（5 bar），minimum burst pressure 217 psig（15 bar），符合 OCP MGX rack-level liquid-cooling specification。

Atomic Claim 582/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0448::SPLIT04

Claim: The expected Vera Rubin pressure envelope aligns with OCP MGX rack-level liquid-cooling specification.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 583/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0447::SPLIT01

Claim: SemiAnalysis believes a coolant return temperature up to 65C for Vera Rubin aligns with Nvidia warm-water operating envelope.
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: COMPLETE
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Atomic Claim 584/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0447::SPLIT03

Claim: SemiAnalysis expects Vera Rubin delta-T to tighten slightly.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 585/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0448::SPLIT03

Claim: Vera Rubin minimum burst pressure is expected to be 217 psig (15 bar).
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 586/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0448::SPLIT02

Claim: Vera Rubin maximum operating pressure is expected to be 72 psig (5 bar).
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 587/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0446

Claim: 雖然 NVIDIA 起初未正式公布 Vera Rubin liquid-cooling system 的完整規格，SemiAnalysis 認為該 platform 將支援最高 65°C 的 coolant return temperature。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 588/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0448::SPLIT01

Claim: The Vera Rubin pressure envelope is expected to remain unchanged versus GB200.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 589/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0447::SPLIT02

Claim: The exact Vera Rubin delta-T implication depends on the supply setpoint and flow-control strategy.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 590/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-INLET-MIN

Claim: The NVIDIA coolant envelope table specifies a minimum coolant inlet temperature of 17°C.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

In practice, cooling follows straightforward physics. To cool a system, you must deliver sufficient water/coolant at the appropriate temperature and pressure through the loop. If you want to increase the cooling capacity of a CDU, you increase flow rate while managing pressure, which in this case implies around a 2.0-2.5x flow increase, depending on how far outlet temperatures are actually pushed by operators.

實務上 cooling 還是很單純的物理：要把 system 冷下來，就必須以適當 temperature、pressure 提供足夠 water／coolant flow。若要提高 CDU cooling capacity，就增加 flow rate、同時管理 pressure。這裡大約意味著 flow 要增加 2.0–2.5x，實際幅度取決於 operator 最後把 outlet temperature 推到多高。

Atomic Claim 591/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0451

Claim: 若要提高 CDU 的 cooling capacity，就需要提高 flow rate。
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 592/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0450

Claim: 要冷卻一套 system，必須在 loop 中以適當 temperature 與 pressure 提供足夠的 water／coolant。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 593/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0452::RESEG01

Claim: 提高 CDU cooling capacity、增加 flow rate 時，同時需要管理 pressure。
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Atomic Claim 594/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0452::RESEG02

Claim: 在此案例中，需要的 flow increase 約為 2.0–2.5 倍；實際幅度取決於 operators 將 outlet temperature 推高到何種程度。
Frame: CLAIM_ONLY · Mode: ESTIMATED · Mapping: CLAIM_ONLY
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Nvidia has indicated that Vera Rubin increases liquid flow rate and achieves nearly double the thermal performance vs Blackwell, without increasing CDU pressure head or introducing additional cooling complexity or cost. Nvidia has achieved this by optimizing the entire hydraulic path. We expect larger quick disconnects to support higher flow, as well as updated manifolds and piping. As seen in the image below, vendor roadmaps suggest that, at least for the next generation of racks, 2 inch QDs should be sufficient to accommodate higher flow while staying within pressure and flow-velocity limits.

Nvidia 表示 Vera Rubin 提高 liquid flow rate 後，可以在不增加 CDU pressure head、也不增加額外 cooling complexity 或 cost 的情況下，做到接近 Blackwell 兩倍的 thermal performance。這是靠最佳化整條 hydraulic path 完成。我們預期會使用更大的 quick disconnect 支援 higher flow，manifold、piping 也會更新。如下圖 vendor roadmap 所示，至少下一代 rack 使用 2-inch QD 應足以承受更高 flow，同時維持 pressure 與 flow-velocity limit。

Atomic Claim 595/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0454::RESEG03

Claim: Nvidia 表示，Vera Rubin 不需要增加額外 cooling complexity。
Frame: CLAIM_ONLY · Mode: ATTRIBUTED · Mapping: CLAIM_ONLY
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Atomic Claim 596/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0454::RESEG02

Claim: Nvidia 表示，Vera Rubin 達到上述 thermal performance 時，不需要提高 CDU pressure head。
Frame: NARY_RELATION · Mode: ATTRIBUTED · Mapping: PARTIAL
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Atomic Claim 597/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0454::RESEG01

Claim: Nvidia 表示，Vera Rubin 的 thermal performance 接近 Blackwell 的 2 倍。
Frame: COMPARISON · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 598/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0456::SPLIT01

Claim: SemiAnalysis expects larger quick disconnects to support higher flow in Vera Rubin.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 599/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0454::RESEG04

Claim: Nvidia 表示，Vera Rubin 不需要增加額外 cooling cost。
Frame: CLAIM_ONLY · Mode: ATTRIBUTED · Mapping: CLAIM_ONLY
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Atomic Claim 600/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0456::SPLIT03

Claim: SemiAnalysis expects updated piping in Vera Rubin.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 601/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0456::SPLIT02

Claim: SemiAnalysis expects updated manifolds in Vera Rubin.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 602/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0455

Claim: Nvidia 透過最佳化整條 hydraulic path 達成這項結果。
Frame: RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 603/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0453

Claim: Nvidia 表示，Vera Rubin 會提高 liquid flow rate。
Frame: RELATION · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 604/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0457

Claim: Vendor roadmaps 顯示，至少對下一代 racks 而言，2-inch QD 應足以容納較高 flow，同時維持在 pressure 與 flow-velocity limits 內。
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: COMPLETE
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Source: CoolIT

Procurement and Cooling Vendor Implications

The primary vendor implication of the updated cooling architecture and doubled power density relates to CDUs and the rack-to-CDU ratio. Today, a CDU can support around 10 GB200 racks. With a rack generating about 2x the heat, that ratio would need to decline unless CDU capacity increases, implying either more CDUs or higher-capacity CDUs. We believe most major operators expect to maintain a ratio of around 10 racks per CDU. As rack power density rises, this points to larger CDUs. Today, in-row CDUs offer cooling capacities up to roughly 2 MW, but we expect future facility CDUs to reach 3-6 MW. Delta currently leads in the CDU specialist segment, alongside Schneider Electric, Vertiv, and nVent. Foxconn and Quanta dominate the system integrator category.

Updated cooling architecture 與 power density 加倍，對 vendor 最直接的影響在 CDU 與 rack-to-CDU ratio。現在一台 CDU 大約可支援 10 個 GB200 rack；若每 rack heat 變成約 2x，除非 CDU capacity 跟著提高，否則 ratio 就必須下降，代表要增加 CDU 數量或改用更高 capacity CDU。我們認為多數 major operator 仍希望維持約 10 rack/CDU，因此 rack power density 越高，就越需要更大的 CDU。目前 in-row CDU cooling capacity 最高約 2MW，未來 facility CDU 預計會到 3–6MW。CDU specialist 目前 Delta 領先，另外還有 Schneider Electric、Vertiv、nVent；system integrator 則以 Foxconn、Quanta 為主。

Atomic Claim 605/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0466

Claim: Foxconn 與 Quanta 主導 system integrator category。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 606/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0460

Claim: 如果單一 rack 產生約 2 倍 heat，而 CDU capacity 沒有提高，rack-to-CDU ratio 就需要下降；也就是需要更多 CDU 或更高 capacity 的 CDU。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 607/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0462

Claim: 在 rack power density 上升且 operators 預期維持約十個 rack／CDU 的前提下，SemiAnalysis 推論將需要更大型的 CDU。
Frame: RELATION · Mode: INFERRED · Mapping: COMPLETE
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Atomic Claim 608/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0459

Claim: 目前一台 CDU 大約可支援 10 個 GB200 racks。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 609/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0463

Claim: 關於 CDU：目前 in-row CDUs cooling capacity 最高約 2MW。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 610/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0465::SPLIT04

Claim: nVent participates in the CDU specialist segment.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 611/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0464

Claim: SemiAnalysis 預期未來 facility CDU capacity 將達 3–6MW。
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 612/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0465::SPLIT02

Claim: Schneider Electric participates in the CDU specialist segment.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 613/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0465::SPLIT03

Claim: Vertiv participates in the CDU specialist segment.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 614/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0465::SPLIT01

Claim: Delta currently leads the CDU specialist segment.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 615/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0461

Claim: SemiAnalysis 認為，多數 major operators 預期維持約 10 racks／CDU 的比例。
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 616/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0458

Claim: Updated cooling architecture 與約翻倍的 power density，對 vendors 的主要影響落在 CDU 與 rack-to-CDU ratio。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Source: CoolIT

The shift from liquid + air to 100% liquid systems, combined with higher flow rates and greater cooling capacity, will require changes across the cooling stack. Fans and radiators used in L2A CDUs will become less critical over time. That said, L2A is likely to maintain meaningful share during the current upcycle, where deployment speed matters more than full optimization, though the long-term trajectory clearly favors L2L. High-density L2L systems will also require redesigns across much of the TCS. This includes updated manifolds, larger quick disconnects (Colder Products Company, Danfoss, Staubli, Parker Hannifin), gold-plated cold plates (AVC, Delta, Boyd, CoolIT, Auras) and, very critically, larger pumps capable of delivering the required water volume. Pump sizing is directly linked to power density and the heat that must be removed. Even manufacturers of motor and drive components used in these pumps, such as Allegro MicroSystems, could see their prospects change as either larger motors, more motors, or both are required. In summary, higher heat on the TCS loop likely increases content/MW for white-space cooling vendors. QDs should benefit most, alongside manifolds and cold plates, with CDUs also benefiting, though to a lesser extent.

從 liquid + air 轉向 100% liquid，再加上 higher flow rate、greater cooling capacity，整個 cooling stack 都要改。L2A CDU 使用的 fan、radiator 長期重要性會下降。不過現在這一波 upcycle 更重視 deployment speed、不是完全最佳化，因此 L2A 短中期仍會保有相當 share；長期方向則很明確地偏向 L2L。High-density L2L system 也會迫使 TCS 大量 redesign，包括更新 manifold、更大的 quick disconnect（Colder Products Company、Danfoss、Staubli、Parker Hannifin）、gold-plated cold plate（AVC、Delta、Boyd、CoolIT、Auras），以及非常關鍵的 larger pump，才能供應所需 water volume。Pump sizing 直接和 power density、需要移除的 heat 掛鉤；甚至 Allegro MicroSystems 這類 pump motor／drive component maker，也可能因 motor 變大、數量變多或兩者同時發生而受影響。總結來說，TCS loop heat 增加，應會提高 white-space cooling vendor 的 content/MW，其中 QD 受益最大，其次是 manifold、cold plate；CDU 也受益，但幅度相對小。

Atomic Claim 617/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0468::EPI01

Claim: Fans used in L2A CDUs will become less critical over time as systems move to fully liquid cooling.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 618/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT05

Claim: The source names Colder Products Company among quick-disconnect vendors in the L2L redesign discussion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 619/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT03

Claim: High-density L2L systems will require gold-plated cold plates.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 620/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT13

Claim: The source names Auras among cold-plate vendors in the L2L redesign discussion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 621/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT02

Claim: High-density L2L systems will require larger quick disconnects.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 622/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT08

Claim: The source names Parker Hannifin among quick-disconnect vendors in the L2L redesign discussion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 623/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0469::SPLIT01

Claim: L2A is likely to retain meaningful share in the current upcycle because deployment speed matters more than full optimization.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 624/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT10

Claim: The source names Delta among cold-plate vendors in the L2L redesign discussion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 625/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT07

Claim: The source names Staubli among quick-disconnect vendors in the L2L redesign discussion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 626/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT01

Claim: High-density L2L systems will require updated manifolds.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 627/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT12

Claim: The source names CoolIT among cold-plate vendors in the L2L redesign discussion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 628/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0468::EPI02

Claim: Radiators used in L2A CDUs will become less critical over time as systems move to fully liquid cooling.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 629/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0476::SPLIT01

Claim: SemiAnalysis expects quick disconnects to benefit most from greater heat on the TCS loop.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 630/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0467

Claim: 從 liquid + air 轉向 100% liquid cooling，再加上更高 flow rate 與更大 cooling capacity，會要求整個 cooling stack 發生變化。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 631/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0470

Claim: 原文預期：High-density L2L systems 也需要重新設計 TCS 的大部分內容。
Frame: CLAIM_ONLY · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 632/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT04

Claim: High-density L2L systems will require larger pumps capable of delivering the required water volume.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 633/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0476::SPLIT03

Claim: SemiAnalysis expects cold plates to benefit from greater heat on the TCS loop.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 634/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT11

Claim: The source names Boyd among cold-plate vendors in the L2L redesign discussion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 635/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0474

Claim: 像 Allegro MicroSystems 這類用於 pumps 的 motor 與 drive component makers，也可能因需要更大型 motors、更多 motors、或兩者兼具而改變其前景。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Atomic Claim 636/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0476::SPLIT04

Claim: SemiAnalysis expects CDUs to benefit from greater heat on the TCS loop, but less than quick disconnects.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 637/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT06

Claim: The source names Danfoss among quick-disconnect vendors in the L2L redesign discussion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 638/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0472

Claim: Pump sizing 與 power density 直接相關。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 639/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0476::SPLIT02

Claim: SemiAnalysis expects manifolds to benefit from greater heat on the TCS loop.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 640/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0469::SPLIT02

Claim: The source judges the long-term cooling trajectory to favor L2L.
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: COMPLETE
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Atomic Claim 641/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0473::RESEG01

Claim: Pump sizing 與需要移除的 heat 直接相關。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 642/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0475

Claim: 總結而言，TCS loop 上更高的 heat 可能提高 white-space cooling vendors 的 content／MW。
Frame: CLAIM_ONLY · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 643/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0471::SPLIT09

Claim: The source names AVC among cold-plate vendors in the L2L redesign discussion.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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For the FWS layout, the headline implication is the potential for chiller-less designs. While we addressed this debate in a separate explanatory note for our core research and datacenter model subscribers, we reiterate that this is not entirely disruptive. Some operators are already running Blackwell systems without chillers in more AI-optimized designs, while others choose to retain chillers for workload flexibility, mixed-hall compatibility, redundancy, and reliability. Over the long term, we expect AI-optimized systems to make chillers less necessary, with content shifting from air-cooled chillers toward dry coolers or adiabatic towers. We currently estimate roughly $0.5M/MWof[[04_{k}nowledg{e}_{b}ase/Air-cooledchiller|air-cooledchiller]]contentversusabout$0.2M/MW for dry coolers or adiabatic towers. SPX Technologies, alongside BAC and Evapco, could benefit, while Johnson Controls, Carrier, and Trane may be challenged. Nonetheless, we expect this efficiency/flexibility trade-off to persist in the medium term and do not foresee a chiller downturn occurring overnight. See our Industrials Model for more details. ↗

FWS layout 最受關注的影響，是可能採 chiller-less design。我們在 core research、datacenter model subscriber 的獨立 explanatory note 已討論過：這並不是完全 disruptive 的變化。有些 operator 現在就已在更 AI-optimized 的 design 中，讓 Blackwell 不使用 chiller；另一些則為 workload flexibility、mixed-hall compatibility、redundancy、reliability 保留 chiller。長期看，AI-optimized system 會讓 chiller 越來越不必要，content 可能從 air-cooled chiller 轉向 dry cooler 或 adiabatic tower。我們目前估算 air-cooled chiller content 約 $0.5M/MW，而 dry cooler／adiabatic tower 約 $0.2M/MW。SPX Technologies、BAC、Evapco 可能受益，Johnson Controls、Carrier、Trane 則較受挑戰。不過 efficiency vs flexibility 的 trade-off 中期仍會存在，我們不認為 chiller demand 會一夕崩掉。更多細節可參考 Industrials Model ↗。

Atomic Claim 644/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0479::SPLIT02

Claim: Some operators retain chillers for mixed-hall compatibility.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 645/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0477

Claim: 對 FWS layout 而言，最主要的 implication 是 chiller-less design 的可能性。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 646/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0482::SPLIT02

Claim: BAC could benefit from cooling content shifting toward dry coolers or adiabatic towers.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 647/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0483::SPLIT02

Claim: Carrier may be challenged by cooling content shifting away from air-cooled chillers.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 648/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0481

Claim: SemiAnalysis 目前估計 air-cooled chiller content 約為 $0.5M／MW；drycoolers或adiabatictowers則約為$0.2M／MW。
Frame: CLAIM_ONLY · Mode: ESTIMATED · Mapping: PARTIAL
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Atomic Claim 649/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0480::SPLIT02

Claim: SemiAnalysis expects content to shift from air-cooled chillers toward dry coolers or adiabatic towers over the long term.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 650/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0480::SPLIT01

Claim: SemiAnalysis expects AI-optimized systems to make chillers less necessary over the long term.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 651/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0484

Claim: 即便如此，SemiAnalysis 預期 efficiency／flexibility trade-off 在中期仍會持續，不認為 chiller downturn 會一夕發生。
Frame: CLAIM_ONLY · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 652/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0482::SPLIT01

Claim: SPX Technologies could benefit from cooling content shifting toward dry coolers or adiabatic towers.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 653/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0482::SPLIT03

Claim: Evapco could benefit from cooling content shifting toward dry coolers or adiabatic towers.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 654/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0479::SPLIT04

Claim: Some operators retain chillers for reliability.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 655/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0479::SPLIT03

Claim: Some operators retain chillers for redundancy.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 656/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0483::SPLIT01

Claim: Johnson Controls may be challenged by cooling content shifting away from air-cooled chillers.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 657/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0483::SPLIT03

Claim: Trane may be challenged by cooling content shifting away from air-cooled chillers.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 658/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0479::SPLIT01

Claim: Some operators retain chillers for workload flexibility.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 659/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0478

Claim: 部分 operators 已在更偏 AI-optimized 的 designs 中，讓 Blackwell systems 在沒有 chillers 的情況下運行。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Rack Level Infrastructure: Power Delivery

In the GB200 article from 2024 ↗, we discussed the previous evolution on power delivery from node level PSU (power supply unit) to centralized rack level power shelf. As VR NVL72 rack TDP reaches 180kW-220kW per rack from 120kW-140kW for GB200 and GB300, the power delivery infrastructure has evolved yet again. In the section below we will discuss the power delivery infrastructure at the rack level of the reference design and the power delivery at the compute tray level for VR NVL72.

我們在 2024 GB200 文章 ↗ 已談過 power delivery 從 node-level PSU 演進到 centralized rack-level power shelf。現在 VR NVL72 rack TDP 從 GB200／GB300 的 120–140kW 再提高到約 180–220kW，power delivery infrastructure 又必須再演進。下面會討論 reference design 的 rack-level power delivery，以及 VR NVL72 compute tray level 的 power delivery。

Atomic Claim 660/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0486::RESEG01

Claim: VR NVL72 rack TDP 為每 rack 180–220kW，較 GB200／GB300 的 120–140kW 更高。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 661/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0487::RESEG01

Claim: VR NVL72 rack TDP 提升到 180–220kW，使 power delivery infrastructure 再次演進。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Since the deployment of GB200, the main theme of the power delivery infrastructure evolution has been about transmission efficiency and power stability. Hyperscalers are developing power delivery infrastructure to address the challenges that comes with high density AI server racks with the roadmap set to 1MW per rack in the next couple of years. Hence, HVDC (high voltage direct current) power rack, BBU (battery back up units), CBU (capacitor backup units), liquid cooled busbar, and SST (solid state transformers) are being developed to increase transmission efficiency and power stability. These will be deployed by customers depending on their proprietary infrastructure designs. For more detail on this, we wrote about the challenge on the grid with AI training in this report. ↗

自 GB200 開始部署後，power delivery infrastructure evolution 的兩大主題一直是 transmission efficiency 與 power stability。Hyperscaler 正為 high-density AI server rack 的挑戰開發新 infrastructure，而 roadmap 幾年內就朝 1MW per rack 前進。因此 HVDC（high-voltage direct current）power rack、BBU（battery backup unit）、CBU（capacitor backup unit）、liquid-cooled busbar、SST（solid-state transformer）都在開發，以提高 transmission efficiency、power stability；customer 會依自家 proprietary infrastructure design 決定採用哪些方案。我們在 AI training 對 grid 挑戰的報告 ↗ 有更完整討論。

Atomic Claim 662/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0491::SPLIT03

Claim: CBU is being developed as power infrastructure to improve transmission efficiency and power stability; deployment depends on customer infrastructure design.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 663/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0489

Claim: 自 GB200 部署以來，power delivery infrastructure 演進的主要主題一直是 transmission efficiency 與 power stability。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 664/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0491::SPLIT02

Claim: BBU is being developed as power infrastructure to improve transmission efficiency and power stability; deployment depends on customer infrastructure design.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 665/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0490::SPLIT02

Claim: Hyperscaler power roadmaps target 1MW per rack in the next couple of years.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 666/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0491::SPLIT01

Claim: HVDC is being developed as power infrastructure to improve transmission efficiency and power stability; deployment depends on customer infrastructure design.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 667/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0491::SPLIT04

Claim: Liquid-cooled busbars are being developed to improve power transmission efficiency and stability; deployment depends on customer infrastructure design.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 668/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0490::SPLIT01

Claim: Hyperscalers are developing power infrastructure to address high-density AI server rack challenges.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 669/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0518

Claim: SST（solid state transformers）也在開發，以提高 transmission efficiency 與 power stability。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 670/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0492

Claim: Deployment of the described HVDC, BBU, CBU and liquid-cooled-busbar technologies depends on each customer’s infrastructure design.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

For the VR NVL72 reference design, the power delivery infrastructure at the rack level includes four 110kW power shelves. The VR NVL72 system has a TDP up to 220kW for the 2300W Rubin TDP SKU. The design with four 110kW power shelves is an N+1 redundancy approach. Each 110kW power shelf is 3U tall and includes six 18.3kW PSU with built in capacitors in the PSU. Each power shelf receives three phase 415VAC-480VAC of power from two 100A whips. The power shelves step down the power from 415VAC-480VAC to 50VDC and sends it to the busbar. Interestingly, the busbar of VR NVL72 is rated for 5000A+, which is much higher than that of Grace Blackwell at 2900A. Given the extremely high current and the lack of fans in the rack, the busbar has to be liquid cooled.

VR NVL72 reference design 的 rack-level power delivery 包含四個 110kW power shelf。若 Rubin TDP 設定 2,300W，整套 VR NVL72 system TDP 最高約 220kW；四個 110kW power shelf 採 N+1 redundancy。每個 power shelf 高 3U，內含六個 18.3kW PSU，capacitor 已整合在 PSU 裡。每個 shelf 從兩條 100A whip 接收 three-phase 415–480VAC，再降到 50VDC 送往 busbar。值得注意的是，VR NVL72 busbar rating 超過 5,000A，明顯高於 Grace Blackwell 的 2,900A；在如此高 current、rack 又沒有 fan 的情況下，busbar 本身也必須 liquid-cooled。

Atomic Claim 671/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0500

Claim: VR NVL72 的 busbar rated current 為 5,000A+，明顯高於 Grace Blackwell 的 2,900A。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 672/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0493

Claim: VR NVL72 reference design 的 rack-level power delivery infrastructure 包含 4 個 110kW power shelves。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 673/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0496

Claim: 每個 110kW power shelf 高度為 3U。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 674/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0501

Claim: 由於 current 極高且 rack 內沒有 fans，busbar 必須採 liquid cooling。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 675/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0494

Claim: 對 2,300W Rubin TDP SKU 而言，VR NVL72 system TDP 最高可達 220kW。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 676/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0498

Claim: 每個 power shelf 由兩條 100A whips 接收 three-phase 415VAC–480VAC power。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 677/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0495

Claim: 採用 4 個 110kW power shelves 的設計，是 N+1 redundancy approach。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 678/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0497::SPLIT01

Claim: Each 110kW VR NVL72 power shelf contains six 18.3kW PSUs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 679/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0499

Claim: power shelves 將 415VAC–480VAC 降壓為 50VDC，並送到 busbar。
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 680/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0497::SPLIT02

Claim: VR NVL72 power-shelf PSUs have built-in capacitors.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 681/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BUSBAR-CURRENT

Claim: The cited OCP 2025 busbar comparison rates the liquid-cooled ORv3 HPR example at 15,625A.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 682/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BUSBAR-LIQ

Claim: The cited OCP 2025 busbar comparison rates the liquid-cooled ORv3 HPR example at 750kW.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 683/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BUSBAR-AIR

Claim: The cited OCP 2025 busbar comparison rates the air-cooled ORv3 HPR example at 140kW.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Source: TE Connectivity, OCP 2025

For the hyperscale customers, they might choose to deploy a standalone power rack either in LVDC (low voltage direct current) or HVDC (high voltage direct current). Below we provide two possible scenarios of the power rack deployment for VR NVL72.

Hyperscale customer 也可能選擇 standalone power rack，採 LVDC（low-voltage DC）或 HVDC（high-voltage DC）。下面提供兩種 VR NVL72 power-rack deployment 可能 scenario。

Atomic Claim 684/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0502

Claim: 對 hyperscale customers 而言，他們可能選擇部署 standalone power rack，採 LVDC 或 HVDC。
Frame: NARY_RELATION · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

First, VR NVL72 rack with an HVDC power rack running at 800VDC (Nvidia Spec) or +/-400VDC (OCP Spec). Since the VR NVL72 rack busbar is still running at 50V and the compute tray can only take in 50V, the 800VDC from the power rack cannot be directly delivered to the busbar. There would still be DC-DC power shelves in the VR NVL72 rack. The DC-DC power shelves will step down the voltage of the current from 800VDC to 50VDC as demonstrated below.

第一種是 VR NVL72 rack 搭 HVDC power rack，運行 800VDC（Nvidia spec）或 ±400VDC（OCP spec）。但 VR NVL72 rack busbar 仍是 50V、compute tray 也只能接 50V，因此 power rack 的 800VDC 無法直接進 busbar，rack 內仍需要 DC-DC power shelf，把 800VDC 降到 50VDC，如下圖。

Atomic Claim 685/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0506::RESEG01

Claim: 在第一個 HVDC power-rack deployment scenario 中，compute tray 只能接收 50V。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: CLAIM_ONLY
開啟本版 Claim 與證據

Atomic Claim 686/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0504::SPLIT02

Claim: An alternative HVDC power-rack specification for VR NVL72 is OCP +/-400VDC.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 687/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0508

Claim: In the hypothetical HVDC power-rack deployment, DC-DC shelves convert 800VDC to 50VDC.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 688/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0505::RESEG01

Claim: 在第一個 HVDC power-rack deployment scenario 中，VR NVL72 rack 的 busbar 仍運行於 50V。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: CLAIM_ONLY
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Atomic Claim 689/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0504::SPLIT01

Claim: One possible VR NVL72 power configuration uses an HVDC power rack running at 800VDC under the Nvidia specification.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 690/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0507

Claim: In the hypothetical HVDC power-rack deployment, the VR NVL72 rack still needs DC-DC power shelves.
Frame: NARY_RELATION · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 691/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0506::RESEG02

Claim: 在第一個 HVDC power-rack deployment scenario 中，power rack 的 800VDC 無法直接送入 busbar。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: CLAIM_ONLY
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Source: OCP, Meta, SemiAnalysis

Second, some customers, namely Meta, may look to integrate their network switch rack with BBU and CBU shelves for efficiency and peak shaving. This allows more CBU and BBU capacity that wouldn’t have been able to fit in the GPU rack. The BBU/CBU and switch rack will be connected to the GPU rack with 50V horizontal busbars. Meta calls this the high power rack, discussed at OCP.

第二種，有些 customer——特別是 Meta——可能把 network switch rack 與 BBU、CBU shelf 整合，追求 efficiency、peak shaving。這樣能放入更多原本塞不進 GPU rack 的 CBU／BBU capacity。BBU/CBU + switch rack 再以 50V horizontal busbar 連到 GPU rack。Meta 在 OCP 把這種設計稱為 high power rack。

Atomic Claim 692/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0512

Claim: In the proposed Meta high-power-rack scenario, 50V horizontal busbars connect the BBU/CBU and switch rack to the GPU rack.
Frame: NARY_RELATION · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Atomic Claim 693/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0510::RESEG01

Claim: 在所提出的 switch-rack integration scenario 中，這種配置可容納更多 CBU capacity；這些 capacity 原本無法放進 GPU rack。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: CLAIM_ONLY
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Atomic Claim 694/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0513::SPLIT02

Claim: Meta discussed the high power rack at OCP.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 695/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0513::SPLIT01

Claim: Meta calls the described combined BBU/CBU and network-switch configuration the high power rack.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 696/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0511::RESEG01

Claim: 在所提出的 switch-rack integration scenario 中，這種配置可容納更多 BBU capacity；這些 capacity 原本無法放進 GPU rack。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: CLAIM_ONLY
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Atomic Claim 697/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0509::SPLIT02

Claim: Some customers, notably Meta, may integrate CBU shelves into the network switch rack for efficiency and peak shaving.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 698/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0509::SPLIT01

Claim: Some customers, notably Meta, may integrate BBU shelves into the network switch rack for efficiency and peak shaving.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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We have more detailed power and architecture details in our VR NVL72 Component BoM and Power Budget Model ↗.

VR NVL72 Component BoM and Power Budget Model ↗ 有更詳細的 power 與 architecture 資料。

Networking: NVLink 6, Rubin Scale Out

NVIDIA’s gen-on-gen innovations are evolutionary and not revolutionary. With GPU scale-up and scale-out bandwidth doubling approximately every 18 months, the copper infrastructure in NVIDIA racks are being innovated to accommodate higher bandwidth workloads. Scale-up network infrastructure will eventually involve optics to build larger world sizes, but that is the topic of a separate article.

NVIDIA 每一代 innovation 更像 evolution，而不是 revolution。GPU scale-up、scale-out bandwidth 約每 18 個月翻倍，NVIDIA rack 內的 copper infrastructure 也持續演進，以承受更高 bandwidth workload。Scale-up network 最終會導入 optics、建立更大 world size，但那是另一篇文章的主題。

Atomic Claim 699/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0515::SPLIT01

Claim: GPU scale-up bandwidth doubles approximately every 18 months.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 700/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0515::SPLIT04

Claim: Scale-up network infrastructure will eventually involve optics to build larger world sizes.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 701/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0515::SPLIT02

Claim: GPU scale-out bandwidth doubles approximately every 18 months.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 702/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0515::SPLIT03

Claim: Nvidia rack copper infrastructure is evolving to accommodate higher-bandwidth workloads.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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The below table shows the evolution of scale-up and scale-out networking speeds. NVLink 6 used in Vera Rubin doubles NVLink bandwidth by implementing bi-directional signaling over the same number of copper cables - effectively delivering 4 Lanes of 200G per NVLink. Much more on this in the following sections.

下表整理 scale-up、scale-out networking speed 的演進。Vera Rubin 使用的 NVLink 6，透過在相同數量 copper cable 上實作 bi-directional signaling，把 NVLink bandwidth 加倍——等效每條 NVLink 提供 4 lanes × 200G。後面會再深入說明。

Atomic Claim 703/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0517

Claim: Vera Rubin 使用的 NVLink 6，透過在相同數量 copper cables 上實作 bi-directional signaling，使 NVLink bandwidth 翻倍；等效為每個 NVLink 提供 4 lanes × 200G。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

Let’s step through key features of Rubin’s networking and the architectures that are likely to be built around Rubin scale-up and scale-out networks.

接下來逐項看 Rubin networking 的關鍵 feature，以及可能圍繞 Rubin scale-up、scale-out network 建立的 architecture。

Bi-directional SerDes for Scale-Up

The doubling of bandwidth per logical GPU from NVLink 5 in GB300 NVL72 to NVLink 6 in Vera Rubin NVL72 are made possible by using a simultaneous bi-directional SerDes for the copper backplane instead of increasing the modulation or baud rate. Whereas NVLink 5 delivers 224G per electrical lane, NVLink 6.0 delivers 448G per electrical lane. Each electrical lane is one differential pair (DP) consisting of two conductors that carry equal magnitude, and opposite polarity signals.

從 GB300 NVL72 的 NVLink 5 到 Vera Rubin NVL72 的 NVLink 6，每 logical GPU bandwidth 翻倍，並不是靠提高 modulation 或 baud rate，而是在 copper backplane 使用 simultaneous bi-directional SerDes。NVLink 5 每 electrical lane 是 224G，NVLink 6.0 則達 448G。每一 electrical lane 就是一組 differential pair（DP），由兩條 conductor 組成，承載 magnitude 相等、polarity 相反的 signal。

Atomic Claim 704/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0518

Claim: 從 GB300 NVL72 的 NVLink 5 到 Vera Rubin NVL72 的 NVLink 6，每個 logical GPU 的 bandwidth 翻倍；原文認為這是藉由 copper backplane 上 simultaneous bi-directional SerDes 達成，而不是提高 modulation 或 baud rate。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 705/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0520

Claim: 每個 electrical lane 是一組 differential pair（DP），由兩條 conductors 組成，兩者承載 magnitude 相等、polarity 相反的 signals。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 706/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0519

Claim: NVLink 5 每個 electrical lane 為 224G；NVLink 6.0 則為 448G。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

This gives rise to the engineering problem of ensuring that a clean signal can be received at either end of the wire because two signals sent in opposite directions over the same copper wire will superpose to form a composite signal that is different from the intended transmitting signal.

這帶來一個 engineering problem：同一 copper wire 上兩個相反方向 signal 會 superpose，形成不同於原本 transmitting signal 的 composite signal，因此必須確保 wire 兩端都還能接收到乾淨 signal。

Atomic Claim 707/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0521

Claim: For simultaneous bidirectional copper signaling, opposite signals superpose on the wire, requiring separation at the receiver.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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In optics, bidirectional interconnect can be achieved by integrating an optical circulator to a transceiver as discussed in our TPUv7 article ↗ published late last year. The circulator works by routing the inbound and outbound signal onto separate paths ↗, ensuring no overlaps between both at the photodiode receiver. Bidirectional interconnect is, however, much trickier in the copper domain. A circulator cannot be used as copper cables are linear transmission lines, which means that the inbound and outbound signals will be summed at the receiver through superposition. The receiver at each end of the copper wire therefore needs a mechanism to separate the local TX from the local RX.

在 optics 中，bidirectional interconnect 可以透過把 optical circulator 整合進 transceiver 實現，正如我們去年底 TPUv7 文章 ↗ 所述。Circulator 會把 inbound、outbound signal route 到不同 optical path ↗，確保 photodiode receiver 處兩者不重疊。但 copper domain 麻煩得多：copper cable 是 linear transmission line，無法使用 circulator；inbound、outbound signal 會因 superposition 在 receiver 相加。因此 copper wire 兩端 receiver 都需要能把 local TX 從 local RX 中分離的 mechanism。

Atomic Claim 708/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0524

Claim: 但在 copper domain 中，bidirectional interconnect 困難得多。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 709/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0523

Claim: Circulator 會把 inbound 與 outbound signals 導向不同 paths，確保兩者在 photodiode receiver 不重疊。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 710/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0525::RESEG02

Claim: Copper cable path 無法使用 circulator。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 711/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0527

Claim: 因此 copper wire 兩端的 receiver 都需要一套 mechanism，把 local TX 與 local RX 分離。
Frame: CLAIM_ONLY · Mode: INFERRED · Mapping: PARTIAL
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Atomic Claim 712/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0522

Claim: 在 optics 中，可以透過把 optical circulator 整合進 transceiver 來實作 bidirectional interconnect。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 713/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0525::RESEG01

Claim: Copper cables 是 linear transmission lines。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 714/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0526::RESEG01

Claim: 在 copper cable receiver，inbound 與 outbound signals 會透過 superposition 相加。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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The solution to this problem is the use of a hybrid at each end of the wire. Without a hybrid, there will be self-interference at the local RX because both the local TX and local RX are being transmitted along the same wire:

解法是在 wire 兩端各使用 hybrid。若沒有 hybrid，local TX、local RX 都沿同一條 wire 傳輸，local RX 會受到 self-interference：

Atomic Claim 715/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0561

Claim: 關於 SerDes：若沒有 hybrid，local TX 與 local RX 同時沿同一條 wire 傳送，會在 local RX 產生 self-interference。
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Atomic Claim 716/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0528

Claim: The described simultaneous bidirectional copper link uses a hybrid at each end of the wire to suppress self-interference.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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B0+A0=BA0

B0 + A0 = BA0

Atomic Claim 717/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0532

Claim: In the source echo-cancellation notation, the superposed signal is B0 + A0 = BA0.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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An inverted copy of the local TX must therefore be generated at the local RX for proper echo cancellation:

因此 local RX 必須生成 local TX 的 inverted copy，才能正確進行 echo cancellation：

Atomic Claim 718/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0531

Claim: 因此 local RX 必須產生 local TX 的 inverted copy，才能進行正確的 echo cancellation。
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: PARTIAL
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B0+A0=BA0+(−A0)=B0

B0 + A0 = BA0 + (−A0) = B0

Atomic Claim 719/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-ECHO-CANCEL

Claim: The source writes the cancellation expression as B0+A0=BA0+(−A0)=B0; this records the source notation without endorsing the entire equality chain.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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The diagram below illustrates this dynamic:

下圖示意這個 dynamic：

Source: IEE Explore ↗

While bidirectional signaling is being used for short-reach (less than 5mm) die-to-die interconnect, what stands out is that NVIDIA has extended this technology to longer reach transmission over copper backplane with a reach of at least 1m.

Bidirectional signaling 本來已用在 short-reach（<5mm）die-to-die interconnect；真正特別的是 NVIDIA 把這項技術延伸到 copper backplane 上至少 1m 的 longer-reach transmission。

Atomic Claim 720/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0533

Claim: Bidirectional signaling 已用於小於 5mm 的 short-reach die-to-die interconnect；更值得注意的是，NVIDIA 已把這項技術延伸到 copper backplane 上至少 1m 的 longer-reach transmission。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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The challenge with bidirectional signaling is that echo cancellation must be precisely calibrated or slight delays in the generation of the local TX copy can cause link failure. However, if NVIDIA were to continue using the 200G SerDes, doubling the bandwidth would mean doubling the number of copper cables at the backplane, which is a tall order for several reasons.

Bidirectional signaling 的挑戰，是 echo cancellation 必須非常精準；local TX copy 只要生成時間稍有 delay，就可能造成 link failure。但如果 NVIDIA 繼續沿用 regular 200G SerDes，要把 bandwidth 加倍就得把 backplane copper cable 數也加倍，這在多方面都很困難。

Atomic Claim 721/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0534

Claim: Bidirectional signaling 的挑戰是 echo cancellation 必須精準校準；local TX copy 的生成只要有些微 delay，就可能造成 link failure。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 722/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0535

Claim: 如果 NVIDIA 繼續使用 200G SerDes，要把 bandwidth 翻倍就代表 copper backplane 上的 copper cable 數量也要翻倍，這在多個層面都很困難。
Frame: NARY_RELATION · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Cramming in approximately five thousand copper cables on the backplane at the Blackwell generation has introduced non-trivial reliability failure modes at scale. To double scale-up bandwidth while staying on regular 200G SerDes would require the backplane to double to ten thousand copper cables: only further increasing the manufacturing complexity and likelihood of failure of the system.

Blackwell 世代 backplane 已經塞進約 5,000 條 copper cable，在 scale 下帶來不小的 reliability failure mode。若維持 regular 200G SerDes，又想把 scale-up bandwidth 翻倍，backplane 就得增加到約 10,000 條 cable，只會進一步提高 manufacturing complexity 與 system failure probability。

Atomic Claim 723/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0538::RESEG02

Claim: 約 10,000 條 copper cables 的 backplane 配置會進一步提高 system failure 的 likelihood。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: CLAIM_ONLY
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Atomic Claim 724/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0536

Claim: 在 Blackwell generation，copper backplane 已塞入約 5,000 條 copper cables，並在 scale deployment 下帶來不可忽視的 reliability failure modes。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 725/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0537::RESEG01

Claim: 若維持一般 200G SerDes 並讓 scale-up bandwidth 加倍，backplane 需要約 10,000 條 copper cables。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: CLAIM_ONLY
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Atomic Claim 726/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0538::RESEG01

Claim: 約 10,000 條 copper cables 的 backplane 配置會進一步提高 manufacturing complexity。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: CLAIM_ONLY
開啟本版 Claim 與證據

Blackwell Copper Backplane ↗, Source: Nvidia

Blackwell Copper Backplane ↗。Source: Nvidia

NVIDIA could also opt to deploy wider racks instead as is the case of AMD’s Helios rack ↗, but this could affect the signal integrity on the PCB as electrical signals will have to traverse a longer path.

NVIDIA 也可以像 AMD Helios rack ↗ 一樣改用更寬的 rack，但 electrical signal 要走更長 path，可能會傷害 PCB signal integrity。

Atomic Claim 727/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0539

Claim: Nvidia could hypothetically choose a wider rack, similar to AMD Helios, for its rack architecture.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 728/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0540

Claim: 採用更寬 rack 也可能影響 PCB 上的 signal integrity，因為 electrical signals 必須走更長的 path。
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: PARTIAL
開啟本版 Claim 與證據

Scale-Up Network – NVLink 6

The bidirectional SerDes technology employed on the copper backplane is used for NVIDIA’s scale-up network. For Vera Rubin NVL72, the scale-up network continues to be rail-optimized with all-to-all connectivity between each GPU and switch ASIC in the scale-up domain.

Copper backplane 上的 bidirectional SerDes 用於 NVIDIA scale-up network。Vera Rubin NVL72 的 scale-up network 仍然採 rail-optimized design，scale-up domain 內每顆 GPU 與每顆 switch ASIC 之間維持 all-to-all connectivity。

Atomic Claim 729/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0541

Claim: Copper backplane 上採用的 bidirectional SerDes technology，用於 NVIDIA 的 scale-up network。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 730/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0542

Claim: 對 Vera Rubin NVL72，scale-up network 繼續採 rail-optimized design，scale-up domain 中每顆 GPU 與 switch ASIC 之間都是 all-to-all connectivity。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Last year, we discussed NVIDIA’s GB200 scale-up architecture, which consists of 18 NVLink 5 Switch chips in a single rack for the NVL72 system.

去年我們討論過 NVIDIA GB200 scale-up architecture：NVL72 單 rack 共有 18 顆 NVLink 5 Switch chip。

Atomic Claim 731/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0543

Claim: NVIDIA 的 GB200 scale-up architecture，在單一 NVL72 rack 中包含 18 顆 NVLink 5 Switch chips。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

GB200 Hardware Architecture - Component Supply Chain & BOM

Dylan Patel ↗, Wega Chu ↗, and 4 others

Dylan Patel ↗、Wega Chu ↗，以及另外 4 位作者。

·

2024年7月17日

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Although the NVLink 6 Switch used in the VR NVL72 system delivers the same per switch 28.8T aggregate bandwidth as NVLink 5 Switch, the SerDes speed on the NVLink 6 Switch is double the SerDes speed of NVLink 5 Switch but with the same number of DPs. As such, in order to deliver double the aggregate scale-up bandwidth required for NVLink 6, Vera Rubin NVL72 racks will contain double the number of NVLink Switches as compared to GB200 racks. This translates to four NVLink Switch chips per tray on 9 switch trays, or 36 NVLink Switch chips in each rack.

VR NVL72 使用的 NVLink 6 Switch，每顆 aggregate bandwidth 和 NVLink 5 Switch 一樣都是 28.8T，但 NVLink 6 SerDes speed 是 NVLink 5 的兩倍、DP 數量相同。因此要提供 NVLink 6 所需的 2x aggregate scale-up bandwidth，Vera Rubin NVL72 rack 的 NVLink Switch 數量就必須是 GB200 rack 的兩倍。也就是每個 switch tray 放 4 顆 NVLink Switch、共 9 個 switch tray，整 rack 總計 36 顆 NVLink Switch。

Atomic Claim 732/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0546::SPLIT01

Claim: VR NVL72 has four NVLink switch chips per switch tray.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 733/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0546::SPLIT03

Claim: VR NVL72 has 36 NVLink switch chips per rack, from four chips on each of nine trays.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 734/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0545

Claim: 為提供 NVLink 6 所需的 2 倍 aggregate scale-up bandwidth，Vera Rubin NVL72 rack 的 NVLink Switch 數量會是 GB200 rack 的 2 倍。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 735/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0544::SPLIT03

Claim: NVLink 6 switches retain the same number of DPs as NVLink 5.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 736/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0544::SPLIT01

Claim: The VR NVL72 NVLink 6 switch retains the same 28.8T aggregate bandwidth per switch as NVLink 5.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 737/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0546::SPLIT02

Claim: VR NVL72 has nine switch trays.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 738/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0544::SPLIT02

Claim: NVLink 6 switch SerDes speed is twice that of NVLink 5.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Each VR NVL72 Switch tray contains four NVLink 6 Switch ASICs and one system management module. The design of the Rubin NVLink 6 Switch tray is also simpler and relatively seamless compared to the first Oberon NVLink 5 Switch released for GB200 because Rubin NVLink 6 Switch trays will not use flyover cables. As such, all NVLink signals will run over the PCB.

每個 VR NVL72 switch tray 包含四顆 NVLink 6 Switch ASIC 與一個 system management module。相較 GB200 第一代 Oberon NVLink 5 Switch，Rubin NVLink 6 Switch tray design 更簡單、assembly 也更順，因為不再使用 flyover cable，所有 NVLink signal 都改走 PCB。

Atomic Claim 739/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0549::RESEG01

Claim: Rubin NVLink 6 Switch tray 相較 GB200 首代 Oberon NVLink 5 Switch 更 seamless。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 740/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0547::SPLIT02

Claim: Each VR NVL72 switch tray contains one system management module.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 741/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0550

Claim: On the Rubin NVLink 6 switch board, NVLink signals travel over PCB traces.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 742/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0547::SPLIT01

Claim: Each VR NVL72 switch tray contains four NVLink 6 switch ASICs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 743/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0549::RESEG02

Claim: Rubin NVLink 6 Switch trays 不使用 flyover cables。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 744/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0548::RESEG01

Claim: Rubin NVLink 6 Switch tray 相較 GB200 首代 Oberon NVLink 5 Switch 更簡化。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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The NVLink 6 Switch board is liquid cooled and will be covered with a cold plate, which is a single module. Connected to the NVSwitch tray is the system management module (SMM) that comes with a CPU and acts as a host to the switch tray. The switch tray to SMM connection uses flyover cables, but this is the only flyover cable connection required in the entire Vera Rubin NVL72 system. Given that the PCIe connection is lower speed and the NVLink Switch tray contains relatively few modules, assembly of the switch tray is unlikely to be challenging.

NVLink 6 Switch board 採 liquid cooling，整張 board 覆蓋一體式 cold plate module。NVSwitch tray 旁接 system management module（SMM），內含 CPU、作為 switch tray host。Switch tray 到 SMM 仍使用 flyover cable，但這是整套 Vera Rubin NVL72 唯一需要的 flyover cable connection。因 PCIe connection speed 較低，NVLink Switch tray module 數也少，所以 assembly 應不會太困難。

Atomic Claim 745/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0553::SPLIT03

Claim: The system management module acts as the NVSwitch tray host.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 746/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0554

Claim: switch tray 與 SMM 之間使用 flyover cables 連接。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 747/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0555

Claim: The switch-tray-to-SMM connection is the only required flyover-cable connection in the described VR NVL72 system.
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 748/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0556::RESEG01

Claim: 由於 PCIe connection 速度較低、且 NVLink Switch tray 內 modules 相對少，switch tray assembly 不太可能構成重大挑戰。
Frame: CLAIM_ONLY · Mode: EXPECTED · Mapping: CLAIM_ONLY
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Atomic Claim 749/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0551

Claim: NVLink 6 Switch board 採 liquid cooling。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 750/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0584

Claim: NVLink 6 Switch board 會由單一 module 形式的 cold plate 覆蓋。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 751/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0553::SPLIT02

Claim: The NVSwitch tray system management module contains a CPU.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 752/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0553::SPLIT01

Claim: A system management module is connected to the NVSwitch tray.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

The diagram below shows how the NVLink 6 signal traverses through the tray. Each of the green lines represents nine 400G logical ports of NVLink 6, or 18 TX/RX lanes of 200G. Because there is only 1 DP per lane using bidirectional SerDes, there are a total of 18 DPs between any connector and any switch for a total of 72 DPs per connector, which is the same as prior generation of NVLink 5 Switch Tray.

下圖顯示 NVLink 6 signal 如何穿越 tray。每條綠線代表 9 個 400G logical port，也就是 18 條 200G TX/RX lane。因 bidirectional SerDes 每 lane 只用 1 個 DP，所以任一 connector 與任一 switch 間共有 18 DP；每 connector 總計 72 DP，和前代 NVLink 5 Switch Tray 相同。

Atomic Claim 753/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0559::RESEG01

Claim: 使用 bidirectional SerDes 時，每個 lane 只需要 1 個 differential pair（DP）。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 754/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0559::RESEG02

Claim: In the illustrated Rubin NVLink 6 switch-tray topology, each connector-to-switch path contains 18 differential pairs.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 755/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0558

Claim: Reference topology 中每條 green line 代表 NVLink 6 的 9 個 400G logical ports，或 18 條 200G TX/RX lanes。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 756/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0560::RESEG01

Claim: Each connector in the illustrated Rubin NVLink 6 switch-tray topology contains 72 differential pairs.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 757/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0560::RESEG02

Claim: 每個 connector 的 72 個 differential pairs（DPs）與前代 NVLink 5 Switch Tray 相同。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

As previously explained, high speed signals require better PCB materials, especially for NVLink 6 which has much lower tolerance for insertion loss given the use of bidirectional signaling. The number of lanes between the PaladinHD2 connectors and the NVLink Switch also creates complexity for PCB design. Hence, the NVLink 6 Switch board PCB is upgraded to 32 layers with M8+ graded CCL - minimally LDK2 glass fiber cloth or potentially Quartz fiber cloth.

如前所述，high-speed signal 需要更好的 PCB material，尤其 NVLink 6 使用 bidirectional signaling，對 insertion loss 的 tolerance 更低。Paladin HD2 connector 與 NVLink Switch 之間的 lane 數也讓 PCB design 更複雜。因此 NVLink 6 Switch board 升級到 32-layer PCB，使用 M8+ grade CCL，至少採 LDK2 glass fiber cloth，甚至可能使用 Quartz fiber cloth。

Atomic Claim 758/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0562

Claim: PaladinHD2 connectors 與 NVLink Switch 之間的 lane 數量，也提高了 PCB design complexity。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 759/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0563::SPLIT02

Claim: The NVLink 6 switch-board PCB uses M8+-grade CCL.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 760/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0563::SPLIT01

Claim: The NVLink 6 switch-board PCB is upgraded to 32 layers.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 761/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0563::SPLIT04

Claim: The NVLink 6 switch board may use Quartz fiber cloth.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 762/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0561

Claim: High-speed signals 需要更好的 PCB materials；尤其 NVLink 6 因採 bidirectional signaling，對 insertion loss 的 tolerance 更低。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 763/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0563::SPLIT03

Claim: The NVLink 6 switch board requires at least LDK2 glass fiber cloth.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

We have more details on the switch tray and various components in the VR NVL72 Component BoM and Power Budget Model ↗.

VR NVL72 Component BoM and Power Budget Model ↗ 有更多 switch tray 與各 component 的細節。

Zooming out, backplane copper cables are used to connect NVLink Switch trays to the GPU trays for the VR NVL72 system. Although the bandwidth doubles, with bi-directional SerDes, the number of cables required does not change from the GB300 backplane generation to the Vera Rubin NVL72 backplane generation. The number of connectors and the number of DPs per connector also does not change from Grace Blackwell NVL72 to VR NVL72.

拉回 rack level，VR NVL72 使用 backplane copper cable 連接 NVLink Switch tray 與 GPU tray。雖然 bandwidth 翻倍，但因採 bidirectional SerDes，從 GB300 到 Vera Rubin NVL72，所需 cable 數量不變；connector 數與每 connector DP 數也都和 Grace Blackwell NVL72 一樣。

Atomic Claim 764/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0566::SPLIT01

Claim: The number of backplane connectors is unchanged from Grace Blackwell NVL72 to VR NVL72.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 765/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0565

Claim: 雖然 bandwidth 翻倍，但因使用 bidirectional SerDes，從 GB300 backplane 到 Vera Rubin NVL72 backplane，所需 cable 數量並未增加。
Frame: COMPARISON · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 766/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0564

Claim: 從 rack-level 來看，VR NVL72 使用 backplane copper cables 連接 NVLink Switch trays 與 GPU trays。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 767/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0566::SPLIT02

Claim: The number of DPs per backplane connector is unchanged from Grace Blackwell NVL72 to VR NVL72.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Grace Blackwell NVL72 Scale-up Topology. Source: SemiAnalysis AI Networking Model ↗

Grace Blackwell NVL72 Scale-up Topology。Source: SemiAnalysis AI Networking Model ↗

Vera Rubin NVL72 Scale-up Topology. Source: SemiAnalysis AI Networking Model ↗

Vera Rubin NVL72 Scale-up Topology。Source: SemiAnalysis AI Networking Model ↗

While the VR NVL72 system features GPUs and scale-up switches that are connected by copper cables, the VR HGX system features servers consisting of eight Rubin GPUs and four NVLink Switch chips. The second meaningful difference between the NVL72 and HGX deployments is that the former has a scale-out bandwidth of 1.6T per GPU while the latter only has a scale-out bandwidth of 800G per GPU. How is it that all Rubin 200 deployments use CX-9 NICs even though some deployments have half the per GPU scale-out bandwidth?

VR NVL72 的 GPU 與 scale-up switch 透過 copper cable 相連；VR HGX 則是一台 server 內含 8 顆 Rubin GPU、4 顆 NVLink Switch chip。NVL72 與 HGX deployment 第二個重要差異，是前者每 GPU scale-out bandwidth 1.6T，後者只有 800G。但所有 Rubin 200 deployment 都使用 CX-9 NIC，為什麼有些 deployment 的 per-GPU scale-out bandwidth 卻只有一半？

Atomic Claim 768/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0605

Claim: The Rubin NVL72 configuration provides 1.6T scale-out bandwidth per GPU, compared with 800G per GPU for HGX.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 769/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0568::RESEG01

Claim: 每台 VR HGX server 包含 8 顆 Rubin GPUs。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 770/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0568::RESEG02

Claim: 每台 VR HGX server 包含 4 顆 NVLink Switch chips。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
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Atomic Claim 771/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0567::RESEG01

Claim: VR NVL72 system 的 GPUs 與 scale-up switches 透過 copper cables 連接。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: CLAIM_ONLY
開啟本版 Claim 與證據

The HGX Rubin NVL8 server consists of eight 800G CX-9 NIC packages – one NIC per GPU – which means that the scale-out bandwidth does not increase from its predecessor, the HGX B300 server. The Vera Rubin NVL72 deployment on the other hand doubles the per GPU scale-out bandwidth to 1.6T, but not by doubling the bandwidth per NIC. Rather, the “1.6T NIC” attached to each Rubin chip is comprised of two 800G CX-9 packages that is connected to the Vera CPU by PCIe Gen 6.0 lanes.

HGX Rubin NVL8 server 由 8 顆 800G CX-9 NIC package 組成，每 GPU 一顆，因此 scale-out bandwidth 和前代 HGX B300 並沒有增加。VR NVL72 則把每 GPU scale-out bandwidth 加倍到 1.6T，但不是提高單顆 NIC bandwidth，而是每顆 Rubin 配兩顆 800G CX-9，透過 PCIe Gen6 lane 連到 Vera CPU。

Atomic Claim 772/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0571::SPLIT02

Claim: HGX Rubin NVL8 does not increase scale-out bandwidth over HGX B300.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 773/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0573::SPLIT01

Claim: The 1.6T NIC attached to each Rubin chip comprises two 800G CX-9 packages.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 774/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0572

Claim: 相較之下，Vera Rubin NVL72 把每顆 GPU 的 scale-out bandwidth 翻倍至 1.6T，但不是藉由把單一 NIC bandwidth 翻倍。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 775/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0573::SPLIT02

Claim: The pair of CX-9 packages attached to each Rubin chip connects to Vera CPU through PCIe Gen 6.0 lanes.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 776/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0571::SPLIT01

Claim: HGX Rubin NVL8 uses eight 800G CX-9 NIC packages, one per GPU.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Each compute tray on the VR NVL72 has eight 800G CX-9 NICs, but there are two possibilities for the number of OSFP cages - either one 1.6T OSFP cage per GPU for a total of 4 per compute tray, or two 800G OSFP cages per GPU for a total of 8 cages per compute tray. We think that the latter would be the more popular deployment assumption, and will be the base case for our discussion of scale-out networking architectures in later sections of the article.

每個 VR NVL72 compute tray 有 8 顆 800G CX-9 NIC。OSFP cage 有兩種可能：每 GPU 一個 1.6T OSFP cage、每 tray 共 4 個；或每 GPU 兩個 800G OSFP cage、每 tray 共 8 個。我們認為後者會更普遍，也會作為後面 scale-out networking architecture 討論的 base case。

Atomic Claim 777/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0576

Claim: SemiAnalysis 認為後者，也就是每顆 GPU 配 2 個 800G OSFP cages 的方案，會是更普遍的 deployment assumption。
Frame: CLAIM_ONLY · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 778/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0575::SPLIT01

Claim: One VR NVL72 option uses one 1.6T OSFP cage per GPU, totaling four per compute tray.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 779/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0574

Claim: VR NVL72 每個 compute tray 配置 8 顆 800G CX-9 NICs。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 780/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0575::SPLIT02

Claim: Another VR NVL72 option uses two 800G OSFP cages per GPU, totaling eight per compute tray.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
開啟本版 Claim 與證據

Source: Nvidia VR NVL72 Component BoM and Power Budget Model

Connecting GPUs in the Scale-Out InfiniBand Network

Broadly, there are three flavors of scale-out deployments for Vera Rubin NVL72. We have InfiniBand-based clusters which employ the NVIDIA Quantum series of switches, NVIDIA Ethernet-based clusters employing Spectrum series switches and lastly, non-Nvidia Ethernet such as Tomahawk-based, Cisco Silicon One or Teralynx-based Ethernet switches. Some Ethernet-based clusters deployed by hyperscalers will use AECs for NIC-to-TOR and switch-to-switch connections, while other Ethernet-based clusters using only optical interconnects will usually adopt a multi-plane and multi-rail networking architecture. What is particularly noteworthy about Vera Rubin NVL72 deployments, however, is that it is the first Nvidia GPU generation where we will be seeing some Co-Packaged-Optics (CPO) deployments in the scale-out backend network.

整體來說，Vera Rubin NVL72 的 scale-out deployment 大致有三種。第一是 InfiniBand cluster，使用 NVIDIA Quantum 系列 switch；第二是 NVIDIA Ethernet cluster，使用 Spectrum 系列 switch；第三是 non-Nvidia Ethernet，例如採 Tomahawk、Cisco Silicon One 或 Teralynx-based Ethernet switch。部分 hyperscaler 的 Ethernet cluster 會在 NIC-to-ToR、switch-to-switch connection 使用 AEC；另一些純 optical interconnect 的 Ethernet cluster，通常會採 multi-plane、multi-rail networking architecture。Vera Rubin NVL72 特別值得注意的一點，是這會成為第一個在 scale-out backend network 出現部分 Co-Packaged Optics（CPO）deployment 的 Nvidia GPU 世代。

Atomic Claim 781/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0581

Claim: 其他只使用 optical interconnects 的 Ethernet-based clusters，通常會採 multi-plane、multi-rail networking architecture。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 782/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0582

Claim: 原文預期：Vera Rubin NVL72 是第一個會在 scale-out backend network 中看到部分 Co-Packaged-Optics deployments 的 Nvidia GPU generation。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 783/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0618

Claim: The non-Nvidia Ethernet VR NVL72 scale-out options include Tomahawk-based switches.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 784/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0580::SPLIT02

Claim: Some hyperscaler Ethernet-based clusters will use AECs for switch-to-switch connections.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 785/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0580::SPLIT01

Claim: Some hyperscaler Ethernet-based clusters will use AECs for NIC-to-TOR connections.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 786/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0615

Claim: The InfiniBand-based VR NVL72 scale-out option uses Nvidia Quantum switches.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 787/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0617

Claim: 第三類則是非 Nvidia Ethernet 方案。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 788/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0619

Claim: 第三類也包含 Cisco Silicon One。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 789/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0616

Claim: The Nvidia Ethernet VR NVL72 scale-out option uses Spectrum switches.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 790/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0620

Claim: Teralynx-based Ethernet switches are a non-Nvidia VR NVL72 scale-out option.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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While there are both InfiniBand and Spectrum-X based clusters, the InfiniBand-based Quantum X800-34XX series of switches is more popular with Neoclouds than with hyperscalers. For InfiniBand, there are two deployment types – the first is the Quantum X800-Q3400 with pluggable optics and the second is the Quantum X800-Q3450 CPO-based switch that use co-packaged Optical Engines (OE) instead of pluggable transceivers.

雖然 InfiniBand、Spectrum-X cluster 都會存在，但 InfiniBand-based Quantum X800-34XX 系列 switch 在 Neocloud 的採用會比 hyperscaler 更高。InfiniBand 有兩種 deployment：第一種是採 pluggable optics 的 Quantum X800-Q3400；第二種是 Quantum X800-Q3450 CPO switch，改用 co-packaged Optical Engine（OE），而不是 pluggable transceiver。

Atomic Claim 791/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0624

Claim: 雖然同時有 InfiniBand 與 Spectrum-X cluster，但 InfiniBand-based Quantum X800-34XX series switches 在 Neoclouds 中比在 hyperscalers 中更普遍。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 792/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0586

Claim: 第二種是 Quantum X800-Q3450 CPO-based switch，使用 co-packaged Optical Engines，而不是 pluggable transceivers。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 793/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0585

Claim: 對 InfiniBand 而言有兩種 deployment types；第一種是 Quantum X800-Q3400，使用 pluggable optics。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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The Quantum X800-Q3400 is logically a multi-plane switch combining 4 Quantum-3 ASICs into a single switch box, though we will dive into this equivalence later in the article. This multi-plane “topology” is abstracted away and as far as network engineers are concerned, the Q3400 is a single switch with 144 ports – or a “little boy” switch.

Quantum X800-Q3400 在邏輯上其實是一個 multi-plane switch box，把 4 顆 Quantum-3 ASIC 組在一起；後面會再深入說明這種等效關係。不過 multi-plane topology 已被完整抽象化，對 network engineer 而言，Q3400 就是一台有 144 個 port 的單一 switch，也就是一台『little boy』switch。

Atomic Claim 794/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0627

Claim: 關於 InfiniBand：這種 multi-plane「topology」被抽象化；對 network engineers 而言，Q3400 就是一台 144-port switch，也就是文中所稱的「little boy」switch。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 795/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0587

Claim: Quantum X800-Q3400 在 logical 上是一個 multi-plane switch，把 4 顆 Quantum-3 ASICs 整合在單一 switch box 內。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Source: SemiAnalysis AI Networking Model ↗

The InfiniBand architecture for the HGX Rubin NVL8 server is therefore effectively a single-plane, 8-rail network consisting of one 800G uplink from each HGX Rubin NVL8 GPU to a leaf switch.

因此 HGX Rubin NVL8 server 的 InfiniBand architecture，本質上是一套 single-plane、8-rail network：每顆 HGX Rubin NVL8 GPU 各有一條 800G uplink，連到 leaf switch。

Atomic Claim 796/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0590

Claim: 因此，HGX Rubin NVL8 server 的 InfiniBand architecture，實際上相當於 single-plane、8-rail network；每顆 HGX Rubin NVL8 GPU 各有一條 800G uplink 連到 leaf switch。
Frame: NARY_RELATION · Mode: INFERRED · Mapping: COMPLETE
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Source: SemiAnalysis AI Networking Model ↗

For the Vera Rubin NVL72 deployment however, there are two 800G OSFP cages per GPU for a total of 1.6T per GPU bandwidth. Having two 800G logical ports per GPU is advantageous because it allows multi-plane network deployments without complex fiber management – by splitting one logical GPU two ways to two different leaf switches. As such, larger network clusters can be built with two 800G logical ports than if only one 1.6T logical port were used. In fact, as we have explained in multiple prior articles such as the networking sections of NVIDIA’s Optical Boogeyman ↗ and Microsoft’s AI Strategy Deconstructed ↗, this relationship is dictated by a simple formula for the maximum number of hosts that can be supported using a switch of k ports on an L-layer:

Vera Rubin NVL72 則是每 GPU 有兩個 800G OSFP cage，合計 1.6T per GPU。每 GPU 有兩個 800G logical port 的好處，是不用複雜 fiber management，就能把同一 logical GPU 拆成兩路，分別連到不同 leaf switch，做 multi-plane network。因此，相較只用單一 1.6T logical port，兩個 800G logical port 可以建立更大的 network cluster。正如我們先前在 NVIDIA Optical Boogeyman ↗、Microsoft AI Strategy Deconstructed ↗ 等文章 networking section 多次解釋，最大 host 數量其實由一個很簡單的公式決定：對一個 k-port switch、L-layer network 而言，可支援的最大 host 數有固定關係。

Atomic Claim 797/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0591

Claim: 但在 Vera Rubin NVL72 deployment 中，每顆 GPU 有 2 個 800G OSFP cages，因此每顆 GPU 合計 bandwidth 為 1.6T。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 798/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0592::SPLIT01

Claim: In the two-800G-logical-port-per-GPU VR NVL72 configuration, one logical GPU can connect to two different leaf switches.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 799/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0592::SPLIT02

Claim: The two-800G-logical-port-per-GPU VR NVL72 configuration enables multi-plane deployment without complex fiber management.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 800/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0593

Claim: 因此，相較只使用 1 個 1.6T logical port，使用 2 個 800G logical ports 可以建立更大的 network clusters。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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2(k2)L

Illustratively, consider two hypothetical VR NVL deployments with 1.6T and 800G logical ports respectively. A 1-plane, 3-layer network with one 1.6T logical ports achieves only a maximum cluster size of 93,312 GPUs, or:

舉例來說，假設兩套 hypothetical VR NVL deployment 分別使用 1.6T、800G logical port。若採 1-plane、3-layer network，且每 GPU 只有一個 1.6T logical port，最大 cluster size 只能到 93,312 顆 GPU。

Atomic Claim 801/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0596

Claim: 在原文所述假設情境中，1-plane、3-layer network 若使用單一 1.6T logical port，maximum cluster size 僅為 93,312 顆 GPUs。
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: PARTIAL
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2(115,2001,6002)3=2(722)3=93,312

Atomic Claim 802/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0597

Claim: 在原文所述假設情境中，上述 93,312 GPUs 的計算式為：(2\left(\frac{\frac{115{,}200}{1{,}600}}{2}\right)^3 = 2\left(\frac{72}{2}\right)^3 = 93,312)。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: PARTIAL
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By one 1.6T logical port, we mean that the two 800G OSFP cages connected to each GPU are connected to a single, dual-port 1.6T transceiver at the leaf layer because the two 800G ports are effectively performing the function of one 1.6T port – and hence the term “logical”.

這裡所謂一個 1.6T logical port，是指每 GPU 的兩個 800G OSFP cage，在 leaf layer 端接到同一顆 dual-port 1.6T transceiver；因為這兩個 800G port 實際上共同執行一個 1.6T port 的功能，所以稱為『logical』port。

Atomic Claim 803/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0598

Claim: 所謂 1 個 1.6T logical port，是指每顆 GPU 連接的 2 個 800G OSFP cages，在 leaf layer 接到單一 dual-port 1.6T transceiver；因為兩個 800G ports 實際共同執行一個 1.6T port 的功能，所以稱為 logical。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Source: SemiAnalysis AI Networking Model ↗

To scale beyond the maximum cluster size of 93,312 GPUs, a 2-plane network can be deployed in which each of the two 800G OSFP cages supporting a GPU are linked to separate leaf switches on different network plans. This allows you to build a 186,624-GPU cluster size as diagrammed below and even scale up to 746,496-GPU cluster sizes.

若要超過 93,312 GPU 的 maximum cluster size，可以改用 2-plane network：每顆 GPU 的兩個 800G OSFP cage 分別連到不同 network plane 的 leaf switch。這樣可以建立 186,624-GPU cluster，如下圖所示，甚至還能進一步 scale 到 746,496 GPU。

Atomic Claim 804/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0600::EPI01

Claim: In the hypothetical two-plane 800G-port VR NVL deployment, the illustrated configuration can build a 186,624-GPU cluster.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 805/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0600::EPI02

Claim: In the hypothetical 800G-port VR NVL deployment, scaling can reach 746,496 GPUs under the source network assumptions.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 806/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0599

Claim: 在原文所述假設情境中，要超過 93,312 顆 GPU 的 maximum cluster size，可以部署 2-plane network：每顆 GPU 的兩個 800G OSFP cages 分別連到不同 network planes 上的 leaf switches。
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: PARTIAL
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2(115,2008002)3=2(1442)3=746,496

Atomic Claim 807/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0601

Claim: 在原文所述假設情境中，746,496 GPUs 的計算式為：(2\left(\frac{\frac{115{,}200}{800}}{2}\right)^3 = 2\left(\frac{144}{2}\right)^3 = 746,496)。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Source: SemiAnalysis AI Networking Model ↗

We think the second cluster with two switch planes will likely be the more prevalent reference architecture for Vera Rubin NVL72 InfiniBand deployments.

我們認為第二種、也就是兩個 switch plane 的 cluster，會是 Vera Rubin NVL72 InfiniBand deployment 更常見的 reference architecture。

Atomic Claim 808/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0602

Claim: SemiAnalysis 認為，採 2 個 switch planes 的第二種 cluster，可能會成為 Vera Rubin NVL72 InfiniBand deployments 更常見的 reference architecture。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: COMPLETE
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Aside from the X800-Q3400 air-cooled switch, NVIDIA will also offer a CPO version, which is the X800-Q3450 containing the same 144 ports of 800G. As pointed out earlier, what is unique about both switches is that each switch box consists of four 28.8T Quantum-3 Switch ASICs for a total of 115.2T per box switching capacity. When used in conjunction with the VR NVL72 servers, the signal from the NIC at the leaf layer is split four ways – 200G each way – to each switch ASIC within the box. Such a configuration bears logical equivalence to a 4-plane network architecture.

除了 air-cooled X800-Q3400，NVIDIA 也會推出 CPO 版本 X800-Q3450，同樣提供 144 個 800G port。前面提過，這兩台 switch box 的特殊之處，是內部都由四顆 28.8T Quantum-3 Switch ASIC 組成，整箱 switching capacity 合計 115.2T。搭配 VR NVL72 server 時，leaf layer NIC 的 signal 會被拆成四路，每路 200G，分別送到 box 內四顆 switch ASIC；因此從邏輯上看，這種 configuration 等效於 4-plane network architecture。

Atomic Claim 809/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0603::SPLIT01

Claim: Nvidia will offer X800-Q3450 as a CPO version alongside the air-cooled X800-Q3400.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 810/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0604

Claim: 每個 switch box 包含 4 顆 28.8T Quantum-3 Switch ASICs，每 box 總 switching capacity 為 115.2T。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 811/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0603::SPLIT02

Claim: X800-Q3450 will have 144 800G ports, the same as X800-Q3400.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 812/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0606

Claim: The VR NVL72 Quantum switch-box fan-out into four 200G paths is logically equivalent to a four-plane network.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 813/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0605

Claim: 搭配 VR NVL72 servers 時，leaf layer 的 NIC signal 會分成 4 路，每路 200G，分別送到 box 內各顆 switch ASIC。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Source: SemiAnalysis AI Networking Model ↗

Ethernet-Based Cluster Deployments

Although InfiniBand has been the more popular network architecture for previous NVIDIA chips such as the H100 and GB200, NVIDIA is aggressively pushing out Spectrum Ethernet-based networks and have introduced various switch SKUs:

過去 H100、GB200 等 NVIDIA chip 主要採 InfiniBand network architecture；但 NVIDIA 現在正積極推 Spectrum Ethernet network，並導入多種 switch SKU：

Atomic Claim 814/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0645

Claim: Nvidia is promoting Spectrum Ethernet networking, following the greater historical prevalence of InfiniBand on H100 and GB200 platforms.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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SN6600, a 102.4T liquid-cooled switch;

SN6600：102.4T、liquid-cooled switch。

Atomic Claim 815/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0609

Claim: SN6600 是 102.4T liquid-cooled switch。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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SN6800, a 4 ASIC, 2048-radix 409.6T multi-plane CPO switch, offering 512 ports of 800G;

SN6800：4 ASIC、2048 radix、409.6T multi-plane CPO switch，提供 512 個 800G port。

Atomic Claim 816/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT04

Claim: SN6800 is a multi-plane CPO switch.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 817/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT03

Claim: SN6800 provides 409.6T switching bandwidth.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 818/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT02

Claim: SN6800 has a radix of 2048.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 819/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT05

Claim: SN6800 offers 512 800G ports.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 820/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0610::SPLIT01

Claim: SN6800 contains four ASICs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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SN6810, a high-radix 102.4T CPO switch with three further deployment options: 512 ports of 200G, 256 ports of 400G and 128 ports of 800G.

SN6810：high-radix 102.4T CPO switch，另有三種 deployment option：512 個 200G port、256 個 400G port、128 個 800G port。

Atomic Claim 821/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0611::SPLIT03

Claim: SN6810 supports a deployment option of 256 ports at 400G.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 822/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0611::SPLIT02

Claim: SN6810 supports a deployment option of 512 ports at 200G.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 823/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0611::SPLIT04

Claim: SN6810 supports a deployment option of 128 ports at 800G.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 824/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0611::SPLIT01

Claim: SN6810 is a high-radix 102.4T CPO switch.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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For the SN6600 switch, the scale-out reference architecture is an 8-plane network where each GPU fans out eight ways to eight different planes. This is similar to the reference architecture for the 8-plane scale-out network using SN6810 switches.

SN6600 的 scale-out reference architecture 採 8-plane network，每顆 GPU fan-out 成 8 路，分別連到 8 個不同 plane。這和使用 SN6810 switch 的 8-plane scale-out reference architecture 類似。

Atomic Claim 825/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0613

Claim: 這與使用 SN6810 switches 的 8-plane scale-out reference architecture 類似。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 826/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0612

Claim: 對 SN6600 而言，scale-out reference architecture 是 8-plane network，每顆 GPU 分成 8 路連到 8 個不同 planes。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Source: SemiAnalysis AI Networking Model ↗

We think that the SN6800 switch with 512 ports of 800G will be quite attractive to Neoclouds because it simplifies deployments. Similar to the X800-Q3400 scale-out network, an SN6800 scale-out network could consist of two switch planes though the SN6800 enables a much larger feasible scale-out world size.

我們認為 SN6800 的 512×800G port configuration 對 Neocloud 很有吸引力，因為 deployment 更簡單。和 X800-Q3400 scale-out network 類似，SN6800 scale-out network 也可以由兩個 switch plane 組成，但 SN6800 能支援的 feasible scale-out world size 大很多。

Atomic Claim 827/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0614

Claim: SemiAnalysis 認為，具有 512 個 800G ports 的 SN6800 對 Neoclouds 會相當有吸引力，因為它能簡化 deployments。
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Atomic Claim 828/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0615

Claim: 類似 X800-Q3400 scale-out network，SN6800 的 scale-out network 也可能採 2 個 switch planes，但 SN6800 可支援更大的 feasible scale-out world size。
Frame: COMPARISON · Mode: HYPOTHETICAL · Mapping: COMPLETE
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The diagram below shows what such a network could look like – though it only shows one of two planes as readers can deduce by the fact that we are only depicting 1x800G from each GPU. Note also that each SN6800 switch box consists of four ASICs, each with its own switch plane, which we will elaborate on later in the article.

下圖示意這種 network 可能長什麼樣子；圖中只畫兩個 plane 中的一個，從每 GPU 只顯示 1×800G connection 就可以看出來。另外，每個 SN6800 switch box 內有四顆 ASIC，每顆 ASIC 都對應自己的 switch plane，後面會再進一步說明。

Source: SemiAnalysis AI Networking Model ↗

For a 512-port switch, we can connect up to 131,072 GPUs with two layers of switches or a ludicrous 33,554,432 GPUs on 3 layers.

如果使用 512-port switch，兩層 switch 最多可連 131,072 顆 GPU；三層甚至可以連到荒謬的 33,554,432 顆 GPU。

Atomic Claim 829/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0616::SPLIT01

Claim: With 512-port switches, two switch layers can connect up to 131,072 GPUs.
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Atomic Claim 830/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0616::SPLIT02

Claim: With 512-port switches, three switch layers can connect up to 33,554,432 GPUs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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2(5122)2=131,072

2(5122)3=33,554,432

What advantages do CPO switches such as the SN6800 deliver for Neoclouds like Coreweave and Lambda when it comes to large-scale cluster deployments?

對 CoreWeave、Lambda 這類 Neocloud 而言，SN6800 這種 CPO switch 在 large-scale cluster deployment 上究竟有什麼優勢？

As discussed in our recent deep dive article on co-packaged optics, ↗ the first reason is that a significant amount of power can be saved by eliminating most of the transceiver content. If we compare the power consumption of one 800G DR4 optical transceiver (16-17W) to the power required by optical engines (OEs) and external light source (ELS) modules to delivery an equivalent 800G of bandwidth in the scale-out network, we see an average ~70% reduction in power used for optical transceivers. Taking a step back, this would translate to 10% in savings for the total networking equipment power consumption in a 3-Layer HGX Rubin NVL8 cluster. This reduction in networking equipment power consumption is however relatively insignificant and amounts to only ~1% of total cluster power consumption because the server’s power budget dominates the equation.

如我們最近 co-packaged optics deep dive ↗ 所討論，第一個優勢是移除大部分 transceiver content 後可以節省相當多 power。如果比較一顆 800G DR4 optical transceiver（約 16–17W）和在 scale-out network 提供同等 800G bandwidth 所需的 optical engine（OE）+ external light source（ELS）module，CPO 平均可降低約 70% optical transceiver power。拉回整體 network 看，對一套 3-layer HGX Rubin NVL8 cluster，大約可降低 10% total networking equipment power。不過因 server power budget 才是整體最大宗，換成 total cluster power 後，這個 networking power saving 其實只約 1%，影響相對有限。

Atomic Claim 831/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0619

Claim: 第一個理由是：移除大部分 transceiver content，可以節省大量 power。
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Atomic Claim 832/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0623

Claim: 不過，這個 networking equipment power reduction 相對有限，只約占 total cluster power consumption 的 1%，因為 server power budget 才是主要部分。
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Atomic Claim 833/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0659

Claim: 把單顆 800G DR4 optical transceiver 的 16–17W 功耗，與在 scale-out network 中用 optical engines（OE）及 external light source（ELS）modules 提供等效 800G bandwidth 的功耗相比，optical transceivers 相關 power 平均可降低約 70%。
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Atomic Claim 834/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0622

Claim: 拉到整體系統看，這相當於 3-layer HGX Rubin NVL8 cluster 的 total networking equipment power consumption 節省約 10%。
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Atomic Claim 835/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-switches-3

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates switches power changes by +23% with CPO versus non-CPO in its 3-layer network scenario.
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Atomic Claim 836/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-optical transceivers-3

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates optical transceivers power changes by -64% with CPO versus non-CPO in its 3-layer network scenario.
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Atomic Claim 837/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-switches-2

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates switches power changes by +22% with CPO versus non-CPO in its 2-layer network scenario.
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Atomic Claim 838/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-networking-3

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates networking power changes by -10% with CPO versus non-CPO in its 3-layer network scenario.
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Atomic Claim 839/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-networking-2

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates networking power changes by -15% with CPO versus non-CPO in its 2-layer network scenario.
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Atomic Claim 840/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-total-2

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates total power changes by -1% with CPO versus non-CPO in its 2-layer network scenario.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 841/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-total-3

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates total power changes by -1% with CPO versus non-CPO in its 3-layer network scenario.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 842/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-68-optical transceivers-2

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates optical transceivers power changes by -78% with CPO versus non-CPO in its 2-layer network scenario.
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

The second benefit is a reduction in cost stemming from eliminating almost all transceivers. There is even more room for price reduction if we are looking at NVIDIA LinkX transceivers, which tend to be priced at significant premium to their generic equivalent. If we compare total networking costs for a 3-Layer network with and without CPO-based switches in the scale-out domain, we see an average of ~75% reduction in transceiver costs. However, as with the power savings above, such costs savings tend not to move the needle dramatically considering the full cluster costs.

第二個好處是幾乎移除所有 transceiver 後帶來的 cost reduction。如果比較 NVIDIA LinkX transceiver，降價空間甚至更大，因為 LinkX 相較 generic equivalent 通常有明顯 premium。比較 scale-out domain 使用與不使用 CPO switch 的 3-layer network，我們看到 transceiver cost 平均可降低約 75%。但和前面的 power saving 一樣，若放到 full cluster cost 裡看，這些 savings 仍不至於大幅改變整體 economics。

Atomic Claim 843/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0627

Claim: 比較 scale-out domain 使用與不使用 CPO-based switches 的 3-layer network，採用 CPO 後 transceiver cost 平均約可降低 75%。
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Atomic Claim 844/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0625

Claim: 若比較 NVIDIA LinkX transceivers，降價空間可能更大，因為 LinkX 相較 generic equivalents 通常具有顯著 premium。
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Atomic Claim 845/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0628

Claim: SemiAnalysis judges the modeled CPO transceiver cost savings to have limited impact on total cluster cost.
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Atomic Claim 846/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0624

Claim: CPO 的第二項優勢是降低成本，主要來自幾乎移除所有 transceivers。
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Atomic Claim 847/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-total-2

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates total capital cost changes by -2% with CPO versus non-CPO in its 2-layer network scenario.
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Atomic Claim 848/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-networking-3

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates networking capital cost changes by -9% with CPO versus non-CPO in its 3-layer network scenario.
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Atomic Claim 849/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-switches-3

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates switches capital cost changes by +81% with CPO versus non-CPO in its 3-layer network scenario.
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Atomic Claim 850/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-networking-2

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates networking capital cost changes by -18% with CPO versus non-CPO in its 2-layer network scenario.
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Atomic Claim 851/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-switches-2

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates switches capital cost changes by +72% with CPO versus non-CPO in its 2-layer network scenario.
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Atomic Claim 852/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-optical transceivers-2

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates optical transceivers capital cost changes by -80% with CPO versus non-CPO in its 2-layer network scenario.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 853/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-total-3

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates total capital cost changes by -1% with CPO versus non-CPO in its 3-layer network scenario.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 854/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-CPO-69-optical transceivers-3

Claim: The February Rubin NVL8 HGX neocloud InfiniBand model estimates optical transceivers capital cost changes by -68% with CPO versus non-CPO in its 3-layer network scenario.
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

We outline these calculations in more detail and discuss this topic at greater length in our CPO Book Report ↗.

這些計算與更多討論，我們在 CPO Book Report ↗ 裡有更完整拆解。

Increased overall network reliability is another compelling point. Transceivers can be unreliable, with a large cluster certain to have ongoing link flaps. Meta’s study presented at ECOC ↗ showed strong reliability results over 15M 400G port-device hours, which is about equivalent 15 CPO switches tested for 11 months in a lab. It is an encouraging start – but we think this point could get stronger with more in field test deployments.

另一個有吸引力的點是整體 network reliability 提高。Transceiver 本身可能不可靠，大型 cluster 幾乎一定會持續發生 link flap。Meta 在 ECOC ↗ 公布的研究，在 1,500 萬個 400G port-device hour 上得到很好的 reliability result，大約等於 15 台 CPO switch 在 lab 連續測 11 個月。這是很鼓舞的開始，但我們認為還需要更多 real-field deployment data，這項優勢才會更有說服力。

Atomic Claim 855/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0632

Claim: Meta 在 ECOC 發表的研究顯示，經過 1,500 萬個 400G port-device hours 測試後，CPO 顯示出良好的可靠性；這約等同於 15 台 CPO switches 在實驗室中測試 11 個月。
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Atomic Claim 856/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0631

Claim: 在大型 cluster 中，持續發生 link flaps 幾乎是不可避免的。
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Atomic Claim 857/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0630

Claim: 關於 Ethernet：Transceivers 可能存在可靠性問題。
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Atomic Claim 858/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0629

Claim: 提升整體 network reliability 是採用 CPO 的另一項重要優勢。
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Atomic Claim 859/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0633

Claim: SemiAnalysis regards the Meta CPO reliability test as encouraging but wants more field-deployment evidence.
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The last factor in favor of adoption of CPO that we would like to mention is the fact that some of Nvidia’s CPO switch SKUs contain the integrated fiber shuffle and can simplify the installation and maintenance of multi-plane network architectures. Recall that the SN6800 contains four Switch ASICs in a multi-plane configuration connected to ports via an integrated fiber shuffle, delivering 409.6T aggregate bandwidth, while the SN6810 uses one Switch ASIC, but without any integrated fiber shuffle, to deliver 102.4T aggregate bandwidth.

最後一個支持 CPO adoption 的因素，是 Nvidia 某些 CPO switch SKU 內建 fiber shuffle，可以簡化 multi-plane network architecture 的 installation、maintenance。回顧一下，SN6800 在 multi-plane configuration 中整合四顆 Switch ASIC，並透過 integrated fiber shuffle 接到 port，aggregate bandwidth 達 409.6T；SN6810 則只有一顆 Switch ASIC、沒有 integrated fiber shuffle，aggregate bandwidth 為 102.4T。

Atomic Claim 860/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0636::SPLIT01

Claim: SN6800 contains four switch ASICs in a multi-plane configuration.
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Atomic Claim 861/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0636::SPLIT03

Claim: SN6800 delivers 409.6T aggregate bandwidth.
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Atomic Claim 862/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0634

Claim: 支持採用 CPO 的最後一項因素，是 Nvidia 部分 CPO switch SKUs 內建 integrated fiber shuffle。
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Atomic Claim 863/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0636::SPLIT02

Claim: SN6800 connects ASICs to ports through an integrated fiber shuffle.
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Atomic Claim 864/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0637::SPLIT02

Claim: SN6810 has no integrated fiber shuffle.
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Atomic Claim 865/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0637::SPLIT03

Claim: SN6810 delivers 102.4T aggregate bandwidth.
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Atomic Claim 866/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0675

Claim: SN6810 使用 1 顆 Switch ASIC。
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Atomic Claim 867/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0635

Claim: 這種 integrated fiber shuffle 可以簡化 multi-plane network architecture 的安裝與維護。
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But first, we will explain why we think multi-plane networking architectures are here to stay as an important preface.

不過在此之前，我們先解釋為什麼 multi-plane networking architecture 很可能會長期存在，這是理解後面內容的重要前提。

Large-scale cluster deployments where cluster sizes exceed 100k GPUs typically utilize multi-plane network architectures because single-plane network architectures do not have enough logical ports at current switch generations to support larger networks without resorting to a high number of switch layers of 3 or more layers.

當 large-scale cluster 超過 100k GPU 時，通常會使用 multi-plane network architecture，因為以現有 switch generation 的 logical port 數量來看，single-plane network 若不堆到三層以上，很難支援更大的 cluster。

Atomic Claim 868/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0638

Claim: 超過 10 萬顆 GPU 的大型 cluster 通常採用 multi-plane network architecture，因為現世代 switch 的 single-plane architecture 沒有足夠 logical ports；若要支援更大 network，否則通常必須增加到 3 層以上的 switch layers。
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Recall from above that a Vera Rubin NVL72 cluster built with Q3400-X800 switches at 1.6T logical ports per GPU cannot scale beyond the maximum cluster size of 93,312 GPUs. Even if future switch generations continue to double the maximum possible switching capacity per switch box, the per GPU bandwidth is also expected to double, which means that the effective logical port count in a cluster network is unlikely to change.

回顧前面，以 Q3400-X800 switch 建立、每 GPU 使用 1.6T logical port 的 Vera Rubin NVL72 cluster，maximum cluster size 只有 93,312 GPU。即使未來 switch generation 持續讓每 switch box 的 maximum switching capacity 翻倍，per-GPU bandwidth 預計也會一起翻倍，因此 cluster network 的 effective logical port count 很可能不會真正增加。

Atomic Claim 869/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0640

Claim: 即使未來每一代 switch 的單一 switch box 最大 switching capacity 繼續倍增，每顆 GPU 的 bandwidth 也預期會同步倍增，因此 cluster network 的有效 logical port 數量可能不會明顯改變。
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Atomic Claim 870/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0639

Claim: 以 Q3400-X800 switches 建構、每顆 GPU 使用 1.6T logical port 的 Vera Rubin NVL72 cluster，最大規模無法超過 93,312 顆 GPU。
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What this means is that deployment of large-scale GPU clusters will continue to require multi-plane network architectures. Do note however that multi-plane networking architectures are not limited by size and we have also seen NVIDIA reference architecture deployments with multi-plane clusters that are significantly below 100k GPUs each.

這代表 large-scale GPU cluster 未來仍會需要 multi-plane network architecture。不過 multi-plane 並不是只有超大 cluster 才會使用；我們也看過 NVIDIA reference architecture 在明顯低於 100k GPU 的 cluster 上採 multi-plane design。

Atomic Claim 871/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0641

Claim: 這表示大型 GPU cluster 的部署未來仍會需要 multi-plane network architecture。
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: PARTIAL
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Atomic Claim 872/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0642

Claim: 不過，multi-plane networking architecture 並不是只有大型 cluster 才會使用。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 873/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0643

Claim: SemiAnalysis observes Nvidia reference multi-plane clusters with substantially fewer than 100,000 GPUs.
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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In multi-plane network architectures using the SN6600 switch instead of the CPO switch, each GPU fans out to multiple switch boxes using fiber shuffles. This requires customers to deploy shuffle boxes, patch panels and unwieldy octopus cables outside the switch box that introduce complexity in installation and maintenance.

若 multi-plane network 使用 SN6600 這類非 CPO switch，每顆 GPU 需要透過 fiber shuffle fan-out 到多個 switch box。Customer 因此得在 switch box 外額外部署 shuffle box、patch panel，以及難以處理的 octopus cable，讓 installation、maintenance 更複雜。

Atomic Claim 874/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0645::SPLIT04

Claim: External shuffle boxes, patch panels and octopus cables complicate installation and maintenance of SN6600 multi-plane networks.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 875/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0644

Claim: 在使用 SN6600 switch、而非 CPO switch 的 multi-plane network architecture 中，每顆 GPU 會透過 fiber shuffles fan out 到多個 switch boxes。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 876/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0645::SPLIT01

Claim: SN6600 multi-plane networking requires customers to deploy shuffle boxes outside the switch box.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 877/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0645::SPLIT03

Claim: SN6600 multi-plane networking requires customers to deploy octopus cables outside the switch box.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 878/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0645::SPLIT02

Claim: SN6600 multi-plane networking requires customers to deploy patch panels outside the switch box.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Some of Nvidia’s CPO SKUs – such as the SN6800 and Q3450 –contain such a fiber shuffle within the switch box, with each optical engine fanning out to different logical ports. They therefore deliver higher aggregate bandwidth – 409.6T and 115.2T respectively than is possible with a switch box based on a single Switch ASIC.

Nvidia 某些 CPO SKU，例如 SN6800、Q3450，直接把這種 fiber shuffle 整合進 switch box，每個 optical engine 再 fan-out 到不同 logical port。因此它們可以提供比單一 Switch ASIC switch box 更高的 aggregate bandwidth，分別達 409.6T、115.2T。

Atomic Claim 879/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0646::SPLIT03

Claim: In these integrated-shuffle CPO SKUs, each optical engine fans out to different logical ports.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 880/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0646::SPLIT02

Claim: Nvidia’s Q3450 integrates a fiber shuffle inside the switch box.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 881/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0686

Claim: The discussed multi-ASIC integrated-shuffle switches SN6800 and Q3450 provide aggregate bandwidth of 409.6T and 115.2T respectively, above single-ASIC switch boxes.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 882/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0646::SPLIT01

Claim: Nvidia’s SN6800 integrates a fiber shuffle inside the switch box.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

For the SN6800 CPO switch, even though the bandwidth engine responsible for converting electrical to optical signals scales from 1.6T to 3.2T or 2x compared to the SN6600 switch, each 3.2T OE within the SN6800 switch box is split into four 800G logical ports that fan out within the box itself and exit the front panel through fiber connectors. This allows a single 1.6T GPU to fan out to two independent switch planes. In fact, the SN6800 switch box consists of four ASICs, which is similar to the X800-Q3400 switch box.

以 SN6800 CPO switch 為例，雖然負責 electrical-to-optical conversion 的 bandwidth engine 相較 SN6600 從 1.6T 提高到 3.2T、也就是 2x，但 SN6800 switch box 內每顆 3.2T OE 會在 box 裡直接切成四個 800G logical port，再從 front panel 的 fiber connector fan-out 出去。這讓單一 1.6T GPU 可以拆成兩路，分別連到兩個獨立 switch plane。事實上，SN6800 switch box 內有四顆 ASIC，這和 X800-Q3400 switch box 的概念很相似。

Atomic Claim 883/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0651::SPLIT02

Claim: The four-ASIC SN6800 switch box is architecturally similar to X800-Q3400.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 884/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0649::SPLIT01

Claim: SN6800 CPO switch doubles electrical-to-optical engine bandwidth from SN6600 1.6T to 3.2T.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 885/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0650

Claim: In the SN6800 reference network, a GPU with 1.6T scale-out connectivity can fan out to two independent switch planes.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 886/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0649::SPLIT02

Claim: Each SN6800 3.2T optical engine splits into four 800G logical ports inside the box.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 887/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0651::SPLIT01

Claim: The SN6800 switch box contains four ASICs.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 888/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0649::SPLIT03

Claim: The internally fanned-out SN6800 optical-engine ports exit the front panel through fiber connectors.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Source: SemiAnalysis AI Networking Model ↗

As the per GPU bandwidth continues to scale to 3.2T, it is not hard to imagine a 4-plane network using SN6800 switches, where each 3.2T GPU is split four ways to connect to four different switch boxes at 800G per link.

如果未來 per-GPU bandwidth 繼續 scale 到 3.2T，就很容易想像用 SN6800 建一套 4-plane network：每顆 3.2T GPU 被拆成四路，每條 800G，分別連到四個不同 switch box。

Atomic Claim 889/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0652

Claim: 在原文所述假設情境中，隨著每顆 GPU bandwidth 提升到 3.2T，可以設想使用 SN6800 switches 的 4-plane network：每顆 3.2T GPU 分成 4 路，以每條 800G link 連到 4 個不同 switch boxes。
Frame: NARY_RELATION · Mode: HYPOTHETICAL · Mapping: PARTIAL
開啟本版 Claim 與證據

In fact, if you have not already noticed – there are strong parallels between the X800-Q3400 switch (non-CPO) explained earlier in the article and a CPO switch in that both facilitate high-radix, multi-plane networking architectures while encasing within the box complex cabling that saves customers on the hassle of cable management.

如果你還沒注意到，前面介紹的 non-CPO X800-Q3400 switch 和 CPO switch 其實高度相似：兩者都能支援 high-radix、multi-plane network architecture，也都把複雜 cabling 收進 switch box 裡，替 customer 省掉大量 cable management 麻煩。

Atomic Claim 890/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0653

Claim: X800-Q3400 switch 與 CPO switch 有明顯相似性：兩者都能支援 high-radix、multi-plane networking architecture。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 891/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0654

Claim: Both X800-Q3400 and the compared Nvidia CPO switches package complex cabling inside the switch box.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Outside of the NVIDIA ecosystem, the main switch ASIC players are Broadcom, which will be manufacturing the Tomahawk 6 and Tomahawk 6 CPO ASICs, as well as Cisco, which recently announced the G300 102.4T ASIC. There are two flavors of hyperscaler backend network deployments:

NVIDIA ecosystem 之外，主要 switch ASIC player 包括 Broadcom——將生產 Tomahawk 6、Tomahawk 6 CPO ASIC——以及 Cisco，後者最近公布 G300 102.4T ASIC。Hyperscaler backend network deployment 大致有兩種：

Atomic Claim 892/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT03

Claim: Broadcom will manufacture Tomahawk 6 ASICs.
Frame: RELATION · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 893/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT01

Claim: Broadcom is a main switch-ASIC player outside the Nvidia ecosystem.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 894/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT02

Claim: Cisco is a main switch-ASIC player outside the Nvidia ecosystem.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 895/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT04

Claim: Broadcom will manufacture Tomahawk 6 CPO ASICs.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 896/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0655::SPLIT05

Claim: Cisco recently announced the 102.4T G300 ASIC.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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8-plane “flat” network utilizing the full 512 switch radix;

8-plane『flat』network，完整使用 512 switch radix。

Atomic Claim 897/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0657

Claim: 關於 Ethernet：第一種是 8-plane「flat」network，使用完整 512 switch radix。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Source: SemiAnalysis AI Networking Model ↗

Single plane network with 1.6T OSFP cages at the NIC.

Single-plane network，NIC 端使用 1.6T OSFP cage。

Atomic Claim 898/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0658

Claim: 第二種 hyperscaler backend deployment 是 single-plane network，NIC 端使用 1.6T OSFP cages。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Source: SemiAnalysis AI Networking Model ↗

For Meta, we think the VR NVL72 deployments will comprise only of non-scheduled fabric (NSF) clusters built using Tomahawk 6-based Minipack-4 OCP Rack 102.4T switches in each datacenter. While Meta will be using optics to connect all the switches within its cluster, it will use 1.6T AECs for NIC-to-TOR connections once 1.6T AECs become broadly available in the market. We expect the 1.6T AEC ramp to happen in the second half of calendar year 2026.

Meta 方面，我們認為 VR NVL72 deployment 會全部採 non-scheduled fabric（NSF）cluster，每個 datacenter 使用 Tomahawk 6-based Minipack-4 OCP Rack 102.4T switch。Meta 的 cluster 內 switch-to-switch connection 會全部使用 optics；等 1.6T AEC 在市場上廣泛供應後，NIC-to-ToR 則會改用 1.6T AEC。我們預期 1.6T AEC ramp 會發生在 2026 年下半年。

Atomic Claim 899/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0659

Claim: SemiAnalysis 認為，Meta 的 VR NVL72 deployments 將只採用 non-scheduled fabric（NSF）clusters，並在每個 datacenter 使用以 Tomahawk 6 為基礎的 Minipack-4 OCP Rack 102.4T switches。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 900/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0660::SPLIT02

Claim: SemiAnalysis expects Meta to use 1.6T AECs for NIC-to-TOR once they are broadly available.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 901/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0660::SPLIT01

Claim: SemiAnalysis expects Meta to use optics to connect all switches within its VR NVL72 clusters.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 902/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0661

Claim: SemiAnalysis 預期 1.6T AEC 將在 2026 年下半年開始 ramp。
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Source: SemiAnalysis AI Networking Model ↗

The catch is that 102.4T Minipack-4 switches may not be shipped in time for Vera Rubin NVL72 rack deployments, and if this were to be the case, some NSF clusters will be shipped using 51.2T Minipack-3 switches instead. This means that gearboxes within the AECs will have to be used to convert 200G per lane SerDes speed at the NIC to 100G per lane SerDes speed at the switch.

但問題是 102.4T Minipack-4 switch 可能趕不上 Vera Rubin NVL72 rack deployment。若真的如此，部分 NSF cluster 會先使用 51.2T Minipack-3 switch。這代表 AEC 內必須加入 gearbox，把 NIC 端每 lane 200G SerDes speed 轉成 switch 端每 lane 100G。

Atomic Claim 903/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0662

Claim: The 102.4T Minipack-4 switches might not ship in time for Meta’s VR NVL72 rack deployment.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 904/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0664

Claim: 這表示 AEC 內的 gearboxes 必須把 NIC 端每 lane 200G 的 SerDes speed，轉換成 switch 端每 lane 100G 的 SerDes speed。
Frame: NARY_RELATION · Mode: INFERRED · Mapping: COMPLETE
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Atomic Claim 905/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0663

Claim: 如果 102.4T Minipack-4 switches 無法及時出貨，部分 NSF clusters 將改用 51.2T Minipack-3 switches。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Meta will not be the only hyperscaler using 1.6T AECs for its VR200 deployments, however. We think xAI will use 1.6T AECs for both NIC-to-TOR and switch-to-switch connectivity at the leaf, spine and core layers. It will be a single-plane network replacing most 1.6T transceivers at the switch boxes – and this can give Credo plenty of pricing power.

Meta 不會是唯一在 VR200 deployment 使用 1.6T AEC 的 hyperscaler。我們認為 xAI 會在 NIC-to-ToR，以及 leaf、spine、core layer 的 switch-to-switch connection 全面使用 1.6T AEC。整體會是一套 single-plane network，取代 switch box 上大部分 1.6T transceiver；這也可能給 Credo 很強的 pricing power。

Atomic Claim 906/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0667::SPLIT02

Claim: The proposed xAI AEC network would replace most 1.6T transceivers at switch boxes.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 907/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0666::SPLIT01

Claim: SemiAnalysis expects xAI VR200 deployments to use 1.6T AECs for NIC-to-TOR connectivity.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 908/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0665

Claim: 原文預期：Meta 不會是唯一在 VR200 deployments 採用 1.6T AEC 的 hyperscaler。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Atomic Claim 909/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0667::SPLIT03

Claim: The proposed xAI AEC network could give Credo substantial pricing power.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 910/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0667::SPLIT01

Claim: The proposed xAI 1.6T AEC network would be single-plane.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 911/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0666::SPLIT04

Claim: SemiAnalysis expects xAI VR200 deployments to use 1.6T AECs for core-layer switch-to-switch connectivity.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 912/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0666::SPLIT02

Claim: SemiAnalysis expects xAI VR200 deployments to use 1.6T AECs for leaf-layer switch-to-switch connectivity.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 913/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0666::SPLIT03

Claim: SemiAnalysis expects xAI VR200 deployments to use 1.6T AECs for spine-layer switch-to-switch connectivity.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Hyperscaler Customization and Assembly Logistics

Customization

For GB300, although the reference design has four ConnectX-8 NICs for the backend network and one Bluefield-3 for frontend network, most hyperscalers have their own design and alternative networking configurations, especially for Bluefield-3. Beside networking configuration, the power delivery modules, the local NVMe storage, and the management module are also highly customized and differentiated across customers.

GB300 reference design 的 backend network 有四顆 ConnectX-8 NIC，frontend network 則使用一顆 BlueField-3；但大多數 hyperscaler 都有自己的 design 與替代 networking configuration，尤其 BlueField-3 部分差異很大。除了 networking，power delivery module、local NVMe storage、management module 也都會依 customer 高度客製化。

Atomic Claim 914/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0670::SPLIT01

Claim: GB300 power-delivery modules are highly customized and differentiated across customers.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 915/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0669::SPLIT01

Claim: The GB300 reference design uses one BlueField-3 for the frontend network.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 916/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0670::SPLIT03

Claim: GB300 management modules are highly customized and differentiated across customers.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 917/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0668

Claim: GB300 reference design 的 backend network 配置 4 張 ConnectX-8 NIC。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 918/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0669::SPLIT02

Claim: Most hyperscalers have their own GB300 networking configurations, especially alternatives to BlueField-3.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 919/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0670::SPLIT02

Claim: GB300 local NVMe storage are highly customized and differentiated across customers.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
開啟本版 Claim 與證據

For example, for some racks, even Amazon is deploying ConnectX-8 in GB300s in many cases. Also, most hyperscalers are deploying their in-house DPU instead of Bluefield-3 for frontend networking. The power delivery module and management modules in GB300 are also highly customized as every customer has differing preferences for these modules. As such, the front half of GB300 is highly customizable with each hyperscalers’ design differing from each other significantly.

例如某些 rack 中，連 Amazon 都會在不少 GB300 deployment 使用 ConnectX-8。多數 hyperscaler 的 frontend networking 也會用自家 in-house DPU 取代 BlueField-3。GB300 的 power delivery module、management module 同樣高度客製化，因為每個 customer 對這些 module 都有不同 preference。因此 GB300 chassis 前半部其實高度 customizable，各 hyperscaler design 彼此差異很大。

Atomic Claim 920/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0674

Claim: 因此，GB300 的前半部具有高度客製化能力，不同 hyperscaler 的設計彼此差異很大。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 921/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0672

Claim: 多數 hyperscalers 在 frontend networking 會部署自研 DPU，而不是 BlueField-3。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 922/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0673::SPLIT01

Claim: GB300 power-delivery modules are highly customized because customer preferences differ.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 923/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0671

Claim: 例如在部分 racks 中，Amazon 在許多 GB300 deployments 也會採用 ConnectX-8。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 924/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0673::SPLIT02

Claim: GB300 management modules are highly customized because customer preferences differ.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

For VR NVL72, although some level of customization is still available, there are a lot more limitations on the form factor. Given the modular and the cableless design of VR NVl72, the customized modules at the front of the chassis must match the form factor and dimension of Nvidia’s reference design. The modules available for customization are power delivery, Bluefield-4, and management modules. We expect most hyperscaler customers to adopt their in-house DSP instead of Bluefield-4. Given the limitation on form factor and dimensions, hyperscalers are redesigning the board layout and module form factor of their in-house DPU to match that of Bluefield-4. For the power delivery modules and management, some customers are also looking to combine them. Amazon does have a JBOK / Nitro Box NIC version for VR NVL72

VR NVL72 仍保留一定 customization，但 form factor 限制多很多。因為 modular、cableless design，chassis 前端任何 custom module 都必須符合 Nvidia reference design 的 form factor、dimension。可客製的 module 主要是 power delivery、BlueField-4、management。我們預期多數 hyperscaler customer 會使用自家 in-house DPU 取代 BlueField-4；但受 form factor 限制，他們必須重新設計自家 DPU board layout、module form factor，做成和 BlueField-4 相同尺寸。Power delivery、management module 方面，也有 customer 考慮把兩者合併。Amazon 則有一個給 VR NVL72 使用的 JBOK／Nitro Box NIC 版本。

Atomic Claim 925/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0677::SPLIT02

Claim: VR NVL72 permits customization of BlueField-4 modules, within reference-design form-factor and dimensional constraints.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 926/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0680

Claim: Some VR NVL72 customers are considering combining power-delivery and management modules.
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 927/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0676

Claim: 由於 VR NVL72 採用 modular 與 cableless design，chassis 前方的客製化 modules 必須符合 Nvidia reference design 的 form factor 與尺寸。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 928/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0677::SPLIT03

Claim: VR NVL72 permits customization of management modules, within reference-design form-factor and dimensional constraints.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 929/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0681

Claim: Amazon 為 VR NVL72 提供一種 JBOK / Nitro Box NIC 版本。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 930/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0677::SPLIT01

Claim: VR NVL72 permits customization of power-delivery modules, within reference-design form-factor and dimensional constraints.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 931/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0675

Claim: VR NVL72 雖然仍保留一定程度的客製化空間，但在 form factor 上的限制比 GB300 更多。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 932/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0678

Claim: SemiAnalysis 預期多數 hyperscaler 客戶會採用自研 DPU，而不是 BlueField-4。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 933/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0679

Claim: 受到 form factor 與尺寸限制，hyperscalers 正重新設計自研 DPU 的 board layout 與 module form factor，使其符合 BlueField-4 的規格。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Assembly Automation and Logistics

At CES 2026, Jensen mentioned that with the streamlined cableless design and automation assembly process, compute tray assembly time has significantly reduced from 2 hours to 5 minutes from Blackwell to Rubin. There are only three L10 level compute tray assembly partners with automation capability for the Rubin platform – Foxconn, Quanta, and Wistron.

Jensen 在 CES 2026 表示，Rubin 採 streamlined cableless design、automation assembly 後，compute tray assembly time 相較 Blackwell 已從 2 小時大幅縮短到 5 分鐘。Rubin platform 目前只有三家 L10 compute tray assembly partner 具備 automation capability：Foxconn、Quanta、Wistron。

Atomic Claim 934/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0684::SPLIT03

Claim: Wistron is one of the only three Rubin L10 compute-tray assembly partners with automation capability.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 935/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0684::SPLIT02

Claim: Quanta is one of the only three Rubin L10 compute-tray assembly partners with automation capability.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 936/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0683

Claim: Jensen 在 CES 2026 表示，cableless design 配合自動化 assembly，使 compute-tray 組裝時間從 Blackwell 的兩小時縮短為 Rubin 的五分鐘。
Frame: NARY_RELATION · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 937/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0684::SPLIT01

Claim: Foxconn is one of the only three Rubin L10 compute-tray assembly partners with automation capability.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗

At L6, board level PCBA, Wistron and Foxconn are the main supplier of Blackwell and Rubin. For L10, Blackwell had lots of different compute tray manufacturers as they buy the Bianca boards from Nvidia to sell to their clients. For Rubin, there are only three suppliers that have the capability to do automation of Rubin compute tray. For smaller ODM or OEM, they either have their compute tray made at the three automation suppliers mentioned above or they will do it in-house without automation. Although not as efficient, compute tray assembly without automation should be much easier compared to Blackwell as well given the seamless modular design. Then at L11, the various ODMs/OEMs assemble the compute tray into the rack.

L6 board-level PCBA 階段，Wistron、Foxconn 是 Blackwell、Rubin 主要 supplier。L10 階段，Blackwell 有很多不同 compute tray manufacturer，因為它們可以向 Nvidia 購買 Bianca board 再整合後賣給 customer；Rubin 則只有三家 supplier 具備 automated compute-tray assembly 能力。較小 ODM／OEM 可以把 compute tray 委託上述三家 automation supplier 製造，也可以自行用非自動化方式組裝。即使效率較低，由於 Rubin modular design 更 seamless，沒有 automation 的 assembly 也應該比 Blackwell 簡單很多。到 L11，則由各 ODM／OEM 把 compute tray 裝進 rack。

Atomic Claim 938/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0688

Claim: 較小型的 ODM 或 OEM，要嘛把 compute tray 交由前述 3 家具備 automation capability 的供應商製造，要嘛自行以非自動化方式組裝。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 939/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0690

Claim: 接著在 L11 階段，各 ODM / OEM 會把 compute tray 組裝進 rack。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 940/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0687

Claim: 對 Rubin 而言，只有 3 家供應商具備自動化組裝 Rubin compute tray 的能力。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 941/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0689

Claim: SemiAnalysis 預期，受惠於 seamless modular design，Rubin 非自動化 compute-tray assembly 也會比 Blackwell 容易許多。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 942/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0685::SPLIT02

Claim: Wistron is a main L6 board-level PCBA supplier for Rubin.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 943/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0686::SPLIT01

Claim: Blackwell has many different L10 compute-tray manufacturers.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 944/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0685::SPLIT04

Claim: Foxconn is a main L6 board-level PCBA supplier for Rubin.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 945/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0685::SPLIT03

Claim: Foxconn is a main L6 board-level PCBA supplier for Blackwell.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 946/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0685::SPLIT01

Claim: Wistron is a main L6 board-level PCBA supplier for Blackwell.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 947/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0686::SPLIT02

Claim: Blackwell L10 manufacturers buy Bianca boards from Nvidia to sell to their clients.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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VR NVL72 TCO: BoM and Power Budget Analysis

The VR NVL72 Component BoM and Power Budget Model ↗ provides a detailed analysis on the BoM and the Power Budget of the rack system.

VR NVL72 Component BoM and Power Budget Model ↗ 提供 rack system 的 BoM 與 Power Budget 詳細分析。

Atomic Claim 948/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BOM-MID

Claim: The visible VR NVL72 BOM quantity column lists 18 PCB midplanes per rack.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 949/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BOM-BF4

Claim: The visible VR NVL72 BOM quantity column lists 18 BlueField-4 modules per rack.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 950/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BOM-ORCHID

Claim: The visible VR NVL72 BOM quantity column lists 72 Orchid boards per rack.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 951/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-BOM-STRATA

Claim: The visible VR NVL72 BOM quantity column lists 36 Strata boards per rack.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Source: VR NVL72 Component BoM and Power Budget Model ↗

The VR NVL72 is more expensive on a per-GPU capital cost basis, ~45% higher vs GB300s and ~14-15% higher vs the MI4XX given a higher server cost on a per GPU basis. This results in a higher Capital Cost of Ownership (TCO). For example VR NVL 72 Hyperscaler Arista has a capital cost of $3.28to[[04_{k}nowledg{e}_{b}ase/MI400|MI4XX]][[04_{k}nowledg{e}_{b}ase/Hyperscaler|Hyperscaler]]of$2.86 per hour per GPU over a 4 year useful life. Our TCO Model runs on a 4y useful life for the purpose of calculating capital cost per hour to reflect a conservative business case, but most Neoclouds and Hyperscalers will use a 5-6y depreciation period and we think it is best to look at EBIT margins using this depreciation period. Our preferred yardstick is Project IRR, which is agnostic to the chosen depreciation period.

以 per-GPU capital cost 看，VR NVL72 比 GB300 高約 45%，相較 MI4XX 也高約 14–15%，主因是 per-GPU server cost 更高，因此 Capital Cost of Ownership（TCO）也比較高。例如 VR NVL72 若部署在 hyperscaler、使用 Arista networking，四年 useful life 下每 GPU 每小時 capital cost 約 $3.28；MI4XX hyperscaler 則約 $2.86。我們的 TCO Model 為了採保守 business case，capital cost/hour 使用 4 年 useful life；但多數 Neocloud、hyperscaler 實際 depreciation period 會是 5–6 年，因此看 EBIT margin 時，我們認為應使用 5–6 年折舊。更偏好的 yardstick 是 Project IRR，因為它不受 depreciation period 選擇影響。

Atomic Claim 952/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0692::SPLIT01

Claim: VR NVL72 per-GPU capital cost is about 45% higher than GB300 in the source model.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 953/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0692::SPLIT02

Claim: VR NVL72 per-GPU capital cost is about 14-15% higher than MI4XX in the source model.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 954/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0692::SPLIT03

Claim: The source attributes higher VR NVL72 per-GPU capital cost to higher server cost per GPU.
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: COMPLETE
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Atomic Claim 955/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0694

Claim: 例如，以 4 年 useful life 計算，採用 Arista networking 的 VR NVL72 Hyperscaler 部署，其 capital cost 為每顆 GPU 每小時 3.28 美元；相較之下，MI4XX Hyperscaler 為 2.86 美元。
Frame: NARY_RELATION · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 956/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0696::SPLIT01

Claim: Most neoclouds and hyperscalers will use a 5-6-year depreciation period according to the source.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 957/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0693

Claim: 因此，VR NVL72 的 Capital Cost of Ownership（TCO）較高。
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 958/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0696::SPLIT02

Claim: SemiAnalysis recommends assessing EBIT margins using the 5-6-year depreciation period commonly used by neoclouds and hyperscalers.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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However, one advantage for Nvidia’s VR SOCAMM option is that NVIDIA directly procures memory, allowing them to negotiate long-term agreements, volume-preferential terms with memory suppliers and most importantly, VVIP pricing. We think this will shield end customers from spikes in memory costs as we outline in our AI server apocalypse note ↗, and is another example of how, as the Central Bank of AI ↗, Nvidia is effectively hedging DRAM prices for all of its customers.

不過 Nvidia VR 的 SOCAMM option 有一個優勢：NVIDIA 自己直接採購 memory，因此可以和 memory supplier 談 long-term agreement、volume-preferential term，最重要的是拿到 VVIP pricing。我們認為這能讓 end customer 比較不受 memory cost spike 影響，正如 AI server apocalypse note ↗ 所述。這也是 Nvidia 作為『Central Bank of AI』↗ 的另一個例子：它等於替所有 customer 對沖 DRAM price。

Atomic Claim 959/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0699

Claim: SemiAnalysis 認為，這種 NVIDIA 直接採購 memory 的模式能降低終端客戶受到 memory cost spikes 衝擊的程度。
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 960/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0698::SPLIT04

Claim: Direct memory procurement enables Nvidia to negotiate VVIP pricing with memory suppliers.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 961/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0698::SPLIT03

Claim: Direct memory procurement enables Nvidia to negotiate volume-preferential terms with memory suppliers.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 962/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0698::SPLIT02

Claim: Direct memory procurement enables Nvidia to negotiate long-term agreements with memory suppliers.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 963/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0698::SPLIT01

Claim: Nvidia directly procures memory for the VR SOCAMM option.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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By contrast, AMD is much more exposed to DRAM price increases as it has about double the amount of DRAM, with about 55 TB per rack of LPDDR5 and 55 TB per rack of DDR5. For the AMD’s Helios rack scale system, AMD sells the GPU/board and does procure the LPDDR5 memory, but it does not procure DDR5 DRAM for rack compute trays; rack assemblers/ODMs source and integrate DDR5 memory. This leaves buyers of AMD’s racks more exposed because AMD is only able to potentially “hedge” the LPDDR5 portion via long-term contracts leaving the DDR5 portion completely exposed. Having double the DRAM content also nearly doubles the overall exposure.

相較之下，AMD 對 DRAM price increase 的 exposure 大很多，因為 DRAM content 幾乎是兩倍：每 rack 約 55TB LPDDR5，再加約 55TB DDR5。Helios rack-scale system 中，AMD 銷售 GPU／board，也會直接採購 LPDDR5；但 compute tray 使用的 DDR5 並不是 AMD 採購，而是由 rack assembler／ODM 自行採購、整合。這代表 AMD rack buyer 更容易受 DRAM 漲價影響：AMD 最多只能用 long-term contract『hedge』LPDDR5 部分，DDR5 則完全暴露在市場價格下。總 DRAM content 又接近兩倍，overall exposure 也幾乎跟著翻倍。

Atomic Claim 964/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0702::SPLIT02

Claim: AMD procures Helios LPDDR5 memory.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 965/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0703

Claim: AMD Helios rack assemblers/ODMs procure and integrate the compute trays’ DDR5 memory themselves.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 966/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0701::SPLIT04

Claim: AMD Helios has about 55TB DDR5 per rack.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 967/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0701::SPLIT03

Claim: AMD Helios has about 55TB LPDDR5 per rack.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 968/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0702::SPLIT03

Claim: AMD does not procure DDR5 DRAM for Helios rack compute trays.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 969/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0704::SPLIT03

Claim: The DDR5 portion remains completely exposed to price changes under the described AMD procurement model.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 970/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0704::SPLIT01

Claim: The source judges AMD rack buyers more exposed to memory price increases.
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: COMPLETE
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Atomic Claim 971/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0702::SPLIT01

Claim: AMD sells the GPU/board for Helios rack-scale systems.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 972/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0705

Claim: In the source comparison, roughly twice the AMD Helios rack DRAM content nearly doubles its exposure to memory-price changes.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 973/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0704::SPLIT02

Claim: AMD can potentially hedge only the LPDDR5 portion through long-term contracts.
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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Atomic Claim 974/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0701::SPLIT02

Claim: The source estimates AMD rack DRAM content at approximately twice the Nvidia alternative.
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Atomic Claim 975/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0701::SPLIT01

Claim: The source judges AMD more exposed to DRAM price increases because its rack has about twice the DRAM content.
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Helios memory costs are more likely to be passed through or re-priced by assemblers and therefore exhibit greater hikes in a memory upcycle. Therefore, we model lower memory price hikes for VR and GB compared to MI4XX below. Our MI400 rack assumptions reflect $8.70/GB[[04_{k}nowledg{e}_{b}ase/LPDDR|LPDDR]]pricingfor[[02_{c}ompanies/AMD|AMD]]versus$6.77/GB for Nvidia, embedding volume discount structures vs the market contract price of $10.63/GB but reflecting the slack of volume economics vs NVIDIA.

Helios memory cost 更可能由 assembler 直接 pass-through 或重新定價，因此 memory upcycle 時漲幅會更大。基於這點，我們在下面 model 對 VR、GB 採較低 memory price hike，MI4XX 則較高。MI400 rack assumption 中，AMD LPDDR pricing 為 $8.70/GB，Nvidia 為 $6.77/GB；兩者都低於 market contract price $10.63/GB，反映 volume discount，但 AMD 的 volume economics 明顯不如 NVIDIA。

Atomic Claim 976/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0706

Claim: 在 memory upcycle 中，Helios 的 memory costs 更可能被 assemblers 轉嫁或重新定價，因此價格漲幅可能更大。
Frame: CLAIM_ONLY · Mode: EXPECTED · Mapping: PARTIAL
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Atomic Claim 977/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT01

Claim: The source MI400 rack assumptions use AMD LPDDR pricing of $8.70/GB.
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Atomic Claim 978/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT04

Claim: The modeled AMD and Nvidia LPDDR prices embed volume discounts versus the market contract price.
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Atomic Claim 979/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT02

Claim: The source comparison uses Nvidia LPDDR pricing of $6.77/GB.
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Atomic Claim 980/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT03

Claim: The source LPDDR pricing comparison uses a market contract price of $10.63/GB.
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Atomic Claim 981/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0708::SPLIT05

Claim: The source interprets the modeled AMD-Nvidia LPDDR price gap as reflecting Nvidia greater volume economics.
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Atomic Claim 982/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0707

Claim: 因此，SemiAnalysis 對 VR 與 GB 所建模的 memory price hikes，低於 MI4XX。
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Our AI Memory Model ↗ expects significant increases in LPDDR5 and DDR5 contract prices into 2Q26 and beyond and we expect to make further revisions higher in total server capex.

我們的 AI Memory Model ↗ 預期 LPDDR5、DDR5 contract price 在 2Q26 及之後都會大幅上升，因此 total server CapEx 之後很可能還要繼續上修。

Atomic Claim 983/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0710::SPLIT01

Claim: The SemiAnalysis Memory Model expects significant DDR5 contract-price increases into 2Q26 and beyond.
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Atomic Claim 984/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0709

Claim: SemiAnalysis AI Memory Model 預期 LPDDR5 contract prices 在 2Q26 及之後顯著上升。
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 985/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0710::SPLIT02

Claim: SemiAnalysis expects to revise total server CapEx higher as memory contract prices rise.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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NVIDIA’s 2300W configuration represents the Max-P configuration, while the efficiency optimized Max-Q configuration runs at 1800W. Regardless of which configuration Nvidia claims both can hit the same peak clocks and therefore achieve marketed 50 PFLOPS FP4 performance. While the underlying hardware is the same, the TCO implications are due to operating costs from different levels of power consumption.

NVIDIA 2,300W configuration 就是 Max-P；以 efficiency 最佳化的 Max-Q 則是 1,800W。不論哪種設定，Nvidia 都宣稱可以達到相同 peak clock，因此 marketed FP4 performance 都可達 50 PFLOPS。Underlying hardware 完全相同，TCO 差異主要來自不同 power consumption 對 operating cost 的影響。

Atomic Claim 986/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0714

Claim: With the same underlying Rubin hardware, Max-P versus Max-Q TCO differences arise from power-dependent operating costs.
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Atomic Claim 987/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0713

Claim: 因此兩種 configuration 都可達到市場宣稱的 50 PFLOPS FP4 performance。
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Atomic Claim 988/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0711

Claim: NVIDIA 的 2300W configuration 是 Max-P，而以效率最佳化的 Max-Q configuration 則運作在 1800W。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 989/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0712

Claim: Nvidia 表示，不論採用 Max-P 或 Max-Q configuration，兩者都能達到相同的 peak clocks。
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Below we share detailed numbers on cost of servers, storage, networking, etc as well as what Nvidia plans to do with Groq.

下面我們會分享 server、storage、networking 等更詳細成本數字，以及 Nvidia 對 Groq 的規劃。

Source: SemiAnalysis AI TCO Model ↗

Source: SemiAnalysis AI TCO Model ↗

Operating costs are similar for VR Max-P vs MI4XX given their comparable chip TDPs and given that most operating costs scale with respect to IT power requirements.

VR Max-P 與 MI4XX 的 operating cost 相近，因為兩者 chip TDP 類似，而且大多數 operating cost 都會隨 IT power requirement 變動。

Atomic Claim 990/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0716

Claim: 由於 chip TDP 相近，而且多數 operating costs 會隨 IT power requirements 變動，因此 VR Max-P 與 MI4XX 的 operating costs 大致相近。
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VR Max-Q on the other hand, exhibits lower Operating costs relative to MI4XX given the lower chip TDP. For example a VR NVL 72 cluster deployed at a Hyperscaler with Arista networking would have a operating cost of $0.75 per gpu per hour, representing ~20% lower costs vs MI4XX deployed with a Hyperscaler with the same Arista networking. This highlights the advantages of the Max-Q configuration, particularly from an operating cost perspective, as the lower power TDP reduces rack-level power density for a meaningful cost savings over time.

VR Max-Q 則因 chip TDP 較低，operating cost 明顯低於 MI4XX。例如 hyperscaler 部署 VR NVL72、使用 Arista networking，operating cost 約 $0.75/GPU/hour，比同樣使用 Arista networking 的 MI4XX hyperscaler deployment 低約 20%。這凸顯 Max-Q configuration 在 operating cost 上的優勢：較低 power TDP 降低 rack-level power density，長期可帶來相當有感的 cost saving。

Atomic Claim 991/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0717

Claim: 相較之下，VR Max-Q 因 chip TDP 較低，其 operating costs 低於 MI4XX。
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Atomic Claim 992/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0719

Claim: 這凸顯 Max-Q configuration 在 operating cost 上的優勢：較低 TDP 會降低 rack-level power density，長期可帶來顯著成本節省。
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Atomic Claim 993/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0718

Claim: 例如，採用 Arista networking 的 VR NVL72 Hyperscaler cluster，operating cost 約為每顆 GPU 每小時 0.75 美元，比採用相同 Arista networking 的 MI4XX 約低 20%。
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Source: SemiAnalysis AI TCO Model ↗

Source: SemiAnalysis AI TCO Model ↗

The MI4XX currently has a performance per TCO advantage based on marketed dense FLOPS over VR. VR has a higher TCO per GPU compared to MI4XX, yet VR marketed PFLOPs are lower vs MI4XX resulting in a TCO per PFLOP disadvantage for the VR vs MI4XX.

若只用 marketed dense FLOPs 衡量，MI4XX 目前的 performance per TCO 優於 VR。VR per-GPU TCO 高於 MI4XX，但 marketed PFLOPs 又低於 MI4XX，因此 VR 的 TCO per PFLOP 較差。

Atomic Claim 994/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0720

Claim: 以 marketed dense FLOPS 衡量，MI4XX 目前相較 VR 具有 performance-per-TCO 優勢。
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Atomic Claim 995/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0721

Claim: VR 每顆 GPU 的 TCO 高於 MI4XX，但 marketed PFLOPs 又低於 MI4XX，因此 VR 在 TCO per PFLOP 上處於劣勢。
Frame: NARY_RELATION · Mode: ESTIMATED · Mapping: PARTIAL
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NVIDIA is offering sparsity for FP4, marketing 50 PFLOPS of FP4, while AMD has opsted to remove sparsity support since CDNA4 for inference dtypes. Harnessing the 50 PFLOPS sparse vs 35 PFLOPS dense drops the cost per perf in units of $/hr per Marketed PFLOP by 35% – a valid comparison if AI Labs can indeed successfully harness Sparse FP4 on the VR NVL72.

NVIDIA 的 FP4 提供 sparsity，marketing 數字是 50 PFLOPS；AMD 則自 CDNA4 起，在 inference dtype 上取消 sparsity support。如果 AI Lab 真能成功利用 VR NVL72 的 Sparse FP4，那麼從 35 PFLOPS dense 提升到 50 PFLOPS sparse，會讓以 $/hr per Marketed PFLOP 衡量的 cost/perf 降低約 35%。在能真正利用 Sparse FP4 的前提下，這個比較是合理的。

Atomic Claim 996/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0722::SPLIT02

Claim: Nvidia markets 50 PFLOPS of sparse FP4.
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Atomic Claim 997/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0724

Claim: 若 AI Labs 能在 VR NVL72 上有效利用 Sparse FP4，從 35 PFLOPS dense 提升到 50 PFLOPS sparse，可讓以每小時每 marketed PFLOP 計算的 cost/performance 降低約 35%。
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Atomic Claim 998/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0722::SPLIT01

Claim: Nvidia offers sparsity support for FP4.
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Atomic Claim 999/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0723

Claim: AMD 自 CDNA4 起，已選擇在 inference dtypes 移除 sparsity support。
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As always, one caveat is that this comparison is done based on a marketed dense PFLOP basis. Effective dense PFLOP (i.e. the real world chip throughput) can differ based on Model Flops Utilization % (MFU), and in general we have seen NVIDIA chip operate at a higher MFU % vs AMD chips, suggesting that performance per TCO based on effective dense PFLOPs could be better for NVIDIA systems vs AMD – however, MFU is dependent on actual workloads with no one-size-fits-all MFU % that is consistently applicable to either systems.

一如既往，這裡的 caveat 是比較基礎仍是 marketed dense PFLOP。Effective dense PFLOP，也就是 real-world chip throughput，會受 Model FLOPs Utilization（MFU）影響。我們整體上觀察到 NVIDIA chip 的 MFU 通常高於 AMD，因此若改用 effective dense PFLOPs 計算 performance per TCO，NVIDIA system 可能比 AMD 更好。不過 MFU 高低高度依賴實際 workload，不存在一個 one-size-fits-all MFU% 可以固定套用到任一 system。

Atomic Claim 1000/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0727::SPLIT01

Claim: SemiAnalysis generally observes Nvidia chips operating at higher MFU than AMD chips.
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Atomic Claim 1001/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0727::SPLIT02

Claim: Higher observed MFU suggests Nvidia systems could have better performance per TCO on an effective-dense-PFLOP basis than AMD.
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Atomic Claim 1002/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0726

Claim: Effective dense PFLOP，也就是真實世界 chip throughput，會隨 Model Flops Utilization（MFU）而不同。
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Atomic Claim 1003/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0727::SPLIT03

Claim: MFU depends on the actual workload; no single MFU percentage consistently applies to either system.
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Indeed, real world use of FP4 Sparsity will probably not reach 50 PFLOPS but it will probably deliver better effective FLOPs than FP4 Dense, but we have yet to evaluate what that real-world performance could be. Running VR NVL72 on 1800W would probably mean lower FP4 Sparse FLOPs than on 2300W.

實務上 FP4 Sparsity 很可能達不到完整 50 PFLOPS，但 effective FLOPs 應該仍會優於 FP4 Dense；至於 real-world performance 究竟有多少，目前還沒有足夠資料評估。另外，VR NVL72 若跑在 1,800W，Sparse FP4 performance 很可能會低於 2,300W 設定。

Atomic Claim 1004/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0730

Claim: 在原文所述假設情境中，VR NVL72 若以 1800W 運作，其 FP4 Sparse FLOPs 很可能低於 2300W configuration。
Frame: NARY_RELATION · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Atomic Claim 1005/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0728

Claim: 原文預期：在真實世界使用情境下，FP4 Sparsity 的實際 performance 很可能無法達到 50 PFLOPS。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 1006/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0729::SPLIT01

Claim: Sparse FP4 will probably deliver better effective FLOPs than dense FP4.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 1007/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0729::SPLIT02

Claim: SemiAnalysis has not yet evaluated the real-world performance achievable with sparse FP4.
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Atomic Claim 1008/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-0-OPERATING_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), MI4XX / Arista / neocloud operating cost is US$1.01 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1009/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-3-OPERATING_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Spectrum / neocloud operating cost is US$0.97 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1010/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-1-TOTAL_TCO

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), MI4XX / Arista / hyperscaler total tco is US$3.77 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1011/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-3-CAPITAL_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Spectrum / neocloud capital cost is US$3.94 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1012/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-4-CAPITAL_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Arista / hyperscaler capital cost is US$3.28 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1013/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-1-OPERATING_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), MI4XX / Arista / hyperscaler operating cost is US$0.92 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1014/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-4-TOTAL_TCO

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Arista / hyperscaler total tco is US$4.16 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1015/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-2-CAPITAL_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Arista / neocloud capital cost is US$3.69 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1016/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-4-OPERATING_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Arista / hyperscaler operating cost is US$0.88 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1017/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-0-TOTAL_TCO

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), MI4XX / Arista / neocloud total tco is US$4.25 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1018/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-2-TOTAL_TCO

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Arista / neocloud total tco is US$4.66 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1019/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-5-OPERATING_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Spectrum / hyperscaler operating cost is US$0.88 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1020/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-3-TOTAL_TCO

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Spectrum / neocloud total tco is US$4.91 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1021/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-5-TOTAL_TCO

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Spectrum / hyperscaler total tco is US$4.15 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1022/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-1-CAPITAL_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), MI4XX / Arista / hyperscaler capital cost is US$2.86 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1023/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-5-CAPITAL_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Spectrum / hyperscaler capital cost is US$3.27 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1024/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-0-CAPITAL_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), MI4XX / Arista / neocloud capital cost is US$3.24 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1025/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-82-2-OPERATING_COST

Claim: In the February 2026 Max-P 2300W comparison model (4-year asset life), VR NVL72 / Arista / neocloud operating cost is US$0.97 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Source: SemiAnalysis AI TCO Model ↗

Atomic Claim 1026/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-0-TOTAL_TCO

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), MI4XX / Arista / neocloud total tco is US$4.25 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1027/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-3-OPERATING_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Spectrum / neocloud operating cost is US$0.83 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1028/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-1-CAPITAL_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), MI4XX / Arista / hyperscaler capital cost is US$2.86 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1029/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-2-TOTAL_TCO

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Arista / neocloud total tco is US$4.51 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1030/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-4-OPERATING_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Arista / hyperscaler operating cost is US$0.75 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1031/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-5-OPERATING_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Spectrum / hyperscaler operating cost is US$0.75 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1032/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-0-CAPITAL_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), MI4XX / Arista / neocloud capital cost is US$3.24 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1033/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-5-CAPITAL_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Spectrum / hyperscaler capital cost is US$3.27 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1034/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-3-CAPITAL_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Spectrum / neocloud capital cost is US$3.94 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1035/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-1-OPERATING_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), MI4XX / Arista / hyperscaler operating cost is US$0.92 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1036/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-4-CAPITAL_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Arista / hyperscaler capital cost is US$3.28 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1037/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-2-CAPITAL_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Arista / neocloud capital cost is US$3.69 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1038/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-5-TOTAL_TCO

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Spectrum / hyperscaler total tco is US$4.02 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1039/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-1-TOTAL_TCO

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), MI4XX / Arista / hyperscaler total tco is US$3.77 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1040/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-2-OPERATING_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Arista / neocloud operating cost is US$0.83 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1041/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-0-OPERATING_COST

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), MI4XX / Arista / neocloud operating cost is US$1.01 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1042/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-3-TOTAL_TCO

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Spectrum / neocloud total tco is US$4.77 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Atomic Claim 1043/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR-COV-VR-TCO-83-4-TOTAL_TCO

Claim: In the February 2026 Max-Q 1800W comparison model (4-year asset life), VR NVL72 / Arista / hyperscaler total tco is US$4.03 per logical GPU-hour.
Frame: ATTRIBUTE · Mode: ESTIMATED · Mapping: COMPLETE
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Source: SemiAnalysis AI TCO Model ↗

Inference throughput too can diverge materially from marketed peak FLOPS, meaning spec-sheet compute does not directly translate into real-world token generation performance. While the B300 is rated at 4,500 Dense FP8 TFLOPs versus 5,000 Dense FP8 TFLOPs for MI355, implying a 10% theoretical compute disadvantage and with same marketed memory bandwidth of 8TB/s measured inference token throughput from our InferenceX ↗ benchmarks shows B300 delivering roughly 6.3x the performance at 100 interactivity for Deepseek R1, using 8k input tokens and 1k output tokens.

Inference throughput 同樣可能和 marketed peak FLOPs 有巨大落差，代表 spec-sheet compute 並不能直接轉化成 real-world token generation performance。B300 marketed dense FP8 為 4,500 TFLOPs，MI355 則為 5,000 TFLOPs，照規格看 B300 theoretical compute 約落後 10%；兩者 marketed memory bandwidth 又同為 8TB/s。但我們 InferenceX ↗ 實測 DeepSeek R1、8k input／1k output，在 interactivity=100 時，B300 token throughput 大約是 MI355 的 6.3x。

Atomic Claim 1044/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0731

Claim: inference throughput 也可能和 marketed peak FLOPS 有顯著差異，因此規格表上的 compute performance 並不會直接轉化成真實世界的 token generation performance。
Frame: CLAIM_ONLY · Mode: ASSERTED · Mapping: PARTIAL
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Atomic Claim 1045/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0732::SPLIT04

Claim: B300 marketed memory bandwidth is 8TB/s.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1046/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0732::SPLIT05

Claim: MI355 marketed memory bandwidth is 8TB/s.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1047/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0772

Claim: B300 額定為 4,500 dense FP8 TFLOPs。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1048/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0732::SPLIT03

Claim: B300 rated dense FP8 compute is 10% below MI355.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1049/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0732::SPLIT06

Claim: SemiAnalysis InferenceX measures B300 token throughput at roughly 6.3x MI355 for Deepseek R1, 8k input tokens, 1k output tokens and 100 interactivity.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 1050/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2-0773

Claim: MI355 額定為 5,000 dense FP8 TFLOPs。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Given that total cost of ownership is only 1.75x higher, this results in a superior performance-per-TCO profile for B300 despite the more modest marketed figures. Such a wildly different result despite very similar specs underscores that real world performance is not dictated by peak FLOPS or memory bandwidth alone. Software and network capabilities are also major factors that contribute to training and token throughput in real workloads.

即使 B300 total cost of ownership 約高 1.75x，performance gap 仍足以讓 B300 的 performance per TCO 更好，儘管 marketed figure 看起來沒有那麼突出。規格非常接近、real-world 結果卻差這麼多，再次說明實際 performance 並不只由 peak FLOPs 或 memory bandwidth 決定；software、network capability 同樣是 training throughput、token throughput 的主要因素。

Atomic Claim 1051/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0734

Claim: The B300/MI355 InferenceX comparison illustrates that peak FLOPs and memory bandwidth alone do not determine real-world performance.
Frame: CLAIM_ONLY · Mode: ATTRIBUTED · Mapping: PARTIAL
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Atomic Claim 1052/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0733

Claim: 由於 total cost of ownership 只高約 1.75 倍，B300 即使 marketed figures 較保守，仍呈現更優的 performance-per-TCO profile。
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1053/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0735::SPLIT02

Claim: The source identifies network capabilities as a major contributor to real-workload training performance and token throughput beyond peak FLOPs and memory bandwidth.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1054/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0735::SPLIT01

Claim: The source identifies software capabilities as a major contributor to real-workload training performance and token throughput beyond peak FLOPs and memory bandwidth.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Rubin and MI4XX will ship with new microarchitectures, real world performance is especially difficult to predict without and benchmarking like we do with InferenceX.

Rubin、MI4XX 都會搭載新 microarchitecture，在沒有像 InferenceX 這類實際 benchmark 前，real-world performance 特別難準確預測。

Atomic Claim 1055/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0736::SPLIT03

Claim: New Rubin and MI4XX microarchitectures make real-world performance especially difficult to predict without benchmarks such as InferenceX.
Frame: ATTRIBUTE · Mode: INFERRED · Mapping: COMPLETE
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Atomic Claim 1056/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0736::SPLIT01

Claim: Rubin will ship with a new microarchitecture.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 1057/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0736::SPLIT02

Claim: MI4XX will ship with a new microarchitecture.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Notably, both operating modes share identical memory bandwidth specifications at 8TB/s. Yet, despite the parity in memory bandwidth inference performance still diverges materially.

值得注意的是，兩種 operating mode 的 memory bandwidth specification 完全相同，都是 8TB/s；但即使 memory bandwidth 一樣，inference performance 仍可能出現非常大的差異。

Atomic Claim 1058/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0737

Claim: The February article states that “both operating modes” have 8TB/s memory bandwidth, but does not resolve the antecedent; the preceding paragraph compares B300 and MI355.
Frame: CLAIM_ONLY · Mode: ATTRIBUTED · Mapping: CLAIM_ONLY
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Atomic Claim 1059/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0738

Claim: The article says inference performance can differ despite equal memory bandwidth; its “operating modes” antecedent remains ambiguous.
Frame: CLAIM_ONLY · Mode: ATTRIBUTED · Mapping: CLAIM_ONLY
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Source: SemiAnalysis InferenceX ↗

Groq LPU Decode Rack

Since Nvidia acquired Groq entered into a licensing agreement for Groq’s technology and hired Groq’s key people December 2025, speculation has brewed on how exactly Nvidia will implement Groq’s technology. We believe that Nvidia will introduce a new LPU rack at GTC 2026. The LPU rack is designed to be used alongside Nvidia GPUs for inference.

自 Nvidia 在 2025 年 12 月與 Groq 達成 technology licensing agreement，並延攬 Groq 核心團隊後，市場一直在猜 Nvidia 到底會怎麼使用 Groq technology。我們認為 Nvidia 會在 GTC 2026 推出新的 LPU rack，定位是和 Nvidia GPU 搭配使用、專門服務 inference。

Atomic Claim 1060/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0740

Claim: SemiAnalysis 預期 Nvidia 將在 GTC 2026 推出新的 LPU rack。
Frame: NARY_RELATION · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 1061/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0739::SPLIT03

Claim: Market speculation followed about how Nvidia would implement Groq technology.
Frame: ATTRIBUTE · Mode: ATTRIBUTED · Mapping: COMPLETE
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Atomic Claim 1062/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0739::SPLIT01

Claim: Nvidia entered into a Groq technology licensing agreement in December 2025.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1063/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0739::SPLIT02

Claim: Nvidia hired key Groq people in December 2025.
Frame: RELATION · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1064/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0741

Claim: LPU rack 的設計目標，是在 inference workload 中與 Nvidia GPUs 搭配使用。
Frame: NARY_RELATION · Mode: ASSERTED · Mapping: COMPLETE
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With CPX being designed specifically for inference pre-fill, the LPU system is designed for inference decode given the LPU’s emphasis on higher bandwidth SRAM. This comes at the expense of total throughput so this LPU decode system could be positioned at serving requests that require very high tokens per second per user, with the user paying much higher $/token to compensate for higher cost to serve.

CPX 專門為 inference prefill 設計；LPU system 則因 LPU 強調 high-bandwidth SRAM，更適合 inference decode。代價是 total throughput 較低，因此這套 LPU decode system 可以定位在服務需要非常高 tokens/s/user 的 request，使用者則支付更高 $/token，補償較高 serving cost。

Atomic Claim 1065/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0742::SPLIT02

Claim: The LPU system is designed for inference decode because of its emphasis on higher-bandwidth SRAM.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1066/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0742::SPLIT01

Claim: CPX is designed specifically for inference prefill.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1067/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0744

Claim: 若 LPU decode system 定位於極高 tokens-per-second-per-user 的服務，使用者可能支付更高 $/token，以補償較高 serving cost。
Frame: CLAIM_ONLY · Mode: HYPOTHETICAL · Mapping: PARTIAL
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Atomic Claim 1068/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0743

Claim: 這會犧牲 total throughput，因此該 LPU decode system 可能定位於服務需要極高 tokens per second per user 的 requests。
Frame: ATTRIBUTE · Mode: HYPOTHETICAL · Mapping: COMPLETE
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It will be designed to sit alongside Nvidia GPUs that handle decode for lower interactivity requests. We have shared more details of the system specification to Accelerator Model clients, where we highlight one part of the supply chain that could be a big beneficiary ↗.

它會和 Nvidia GPU 並列部署；GPU 負責較低 interactivity request 的 decode，LPU 則服務更高 interactivity。更多 system specification 我們已分享給 Accelerator Model client，其中也點出一個可能成為大受益者的 supply-chain 環節 ↗。

Atomic Claim 1069/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0745::SPLIT02

Claim: In the proposed LPU/GPU deployment, Nvidia GPUs will handle decode for lower-interactivity requests.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 1070/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0745::SPLIT01

Claim: The proposed LPU system will sit alongside Nvidia GPUs.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
開啟本版 Claim 與證據

Some details we will share here is that there are 256 LPUs per rack and it is the 3rd generation Groq chip on Samsung 4nm (the 2nd generation is being skipped). We share an important supply chain detail that has an impact on growth and market share as well as topology in the Accelerator Model note. ↗

這裡可以先透露幾個細節：每 rack 會有 256 顆 LPU，採用第三代 Groq chip、Samsung 4nm 製程；第二代會直接跳過。我們在 Accelerator Model note ↗ 另外分享了一項重要 supply-chain 細節，會影響 growth、market share 與 topology。

Atomic Claim 1071/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0748::SPLIT02

Claim: The proposed third-generation Groq chip uses Samsung 4nm.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 1072/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0748::SPLIT01

Claim: The proposed LPU rack uses the third-generation Groq chip.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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Atomic Claim 1073/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0748::SPLIT03

Claim: The second-generation Groq chip is being skipped.
Frame: ATTRIBUTE · Mode: ASSERTED · Mapping: COMPLETE
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Atomic Claim 1074/1074 · 2026-02-25_vera-rubin-extreme-co-design-an-evolution::VR2R-0747

Claim: The LPU rack proposed in the February 2026 article has 256 LPUs per system.
Frame: ATTRIBUTE · Mode: EXPECTED · Mapping: COMPLETE
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