clm_3d598583444a4049ab5148c66c3323c2_r1

VR2R-0546::SPLIT01

回到這篇 SA Coverage

① SA Source

• Source: 開啟完整 SA 文章
• Section: GB200 Hardware Architecture - Component Supply Chain & BOM
• Line hint: 701

Context Before

2024年7月17日

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Evidence

Although the NVLink 6 Switch used in the VR NVL72 system delivers the same per switch 28.8T aggregate bandwidth as NVLink 5 Switch, the SerDes speed on the NVLink 6 Switch is double the SerDes speed of NVLink 5 Switch but with the same number of DPs. As such, in order to deliver double the aggregate scale-up bandwidth required for NVLink 6, Vera Rubin NVL72 racks will contain double the number of NVLink Switches as compared to GB200 racks. This translates to four NVLink Switch chips per tray on 9 switch trays, or 36 NVLink Switch chips in each rack.

Context After

Each VR NVL72 Switch tray contains four NVLink 6 Switch ASICs and one system management module. The design of the Rubin NVLink 6 Switch tray is also simpler and relatively seamless compared to the first Oberon NVLink 5 Switch released for GB200 because Rubin NVLink 6 Switch trays will not use flyover cables. As such, all NVLink signals will run over the PCB.

The NVLink 6 Switch board is liquid cooled and will be covered with a cold plate, which is a single module. Connected to the NVSwitch tray is the system management module (SMM) that comes with a CPU and acts as a host to the switch tray. The switch tray to SMM connection uses flyover cables, but this is the only flyover cable connection required in the entire Vera Rubin NVL72 system. Given that the PCIe connection is lower speed and the NVLink Switch tray contains relatively few modules, assembly of the switch tray is unlikely to be challenging.

② Atomic Claim

VR NVL72 has four NVLink switch chips per switch tray.

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "SWITCH_CHIPS_PER_TRAY",
  "context_nodes": [
    {
      "id": "04_knowledge_base/NVLink",
      "label": "NVLink"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/VR NVL72",
    "label": "VR NVL72"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [],
    "value_text": "VR NVL72 has four NVLink switch chips per switch tray."
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	VR NVL72	04_knowledge_base/VR NVL72
context_0	NVLink	NVLink

⑤ V2 Draft（需要修正時直接編輯）

Inline repair

只編輯以下三個 Draft 區塊。完成後將 review_action 設為 REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。

V2 Atomic Claim Draft

VR NVL72 has four NVLink switch chips per switch tray.

V2 Semantic Frame Draft

{
  "attribute": "SWITCH_CHIPS_PER_TRAY",
  "context_nodes": [
    {
      "id": "04_knowledge_base/NVLink",
      "label": "NVLink"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/VR NVL72",
    "label": "VR NVL72"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [],
    "value_text": "VR NVL72 has four NVLink switch chips per switch tray."
  }
}

V2 Revision Metadata Draft

{
  "epistemic_mode": "ASSERTED",
  "mapping_status": "COMPLETE"
}

⑥ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。