VR2R-0299::SPLIT02
① SA Source
- Source: 開啟完整 SA 文章
- Section:
PCB vs Flyover Cables - Line hint:
419
Context Before
PCB vs Flyover Cables
Nevertheless, it is still challenging to drive a PCIe Gen6 signal over around 500mm of PCB distance from the Strata Module to the front of the Orchid Module. In addition to having high quality SerDes, proper signal integrity is still achievable by upgrading PCB materials.
Evidence
First, we must understand why high-speed signals perform worse on PCB versus flyover cables. As SerDes rates increase, high-speed channels become increasingly constrained by insertion loss introduced by PCB traces, vias, dielectric materials and conductor roughness. Insertion loss is defined as the signal power that is lost as a signal is traveling through an interconnect channel.
Context After
Source: Doosan, SemiAnalysis
② Atomic Claim
As SerDes rates increase, insertion loss introduced by vias increasingly constrains high-speed channels.
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "CHANNEL_LOSS_SOURCE",
"context_nodes": [
{
"id": "04_knowledge_base/SerDes",
"label": "SerDes"
},
{
"id": "04_knowledge_base/Via",
"label": "vias"
}
],
"entity": {
"id": "04_knowledge_base/Insertion loss",
"label": "Insertion loss"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "As SerDes rates increase, insertion loss introduced by vias increasingly constrains high-speed channels."
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | Insertion loss | 04_knowledge_base/Insertion loss |
| context_0 | SerDes | SerDes |
| context_1 | vias | Via |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
As SerDes rates increase, insertion loss introduced by vias increasingly constrains high-speed channels.
V2 Semantic Frame Draft
{
"attribute": "CHANNEL_LOSS_SOURCE",
"context_nodes": [
{
"id": "04_knowledge_base/SerDes",
"label": "SerDes"
},
{
"id": "04_knowledge_base/Via",
"label": "vias"
}
],
"entity": {
"id": "04_knowledge_base/Insertion loss",
"label": "Insertion loss"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "As SerDes rates increase, insertion loss introduced by vias increasingly constrains high-speed channels."
}
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。