clm_e5559e7e21bd4adbba8277842e472efc_r2

VR2R-0296

回到這篇 SA Coverage

① SA Source

• Source: 開啟完整 SA 文章
• Section: PCB vs Flyover Cables
• Line hint: 417

Context Before

But now that the NIC is closer to the OSFP cage, the lower speed PCIe Gen6 signal (64Gbit/s per lane uni-directional) travels the longer distance. By making the PCIe Gen6 signal longer, the signal can travel over PCB given that PCIe Gen6 has better signal integrity than the higher speed 200G Ethernet/InfiniBand signal.

PCB vs Flyover Cables

Evidence

Nevertheless, it is still challenging to drive a PCIe Gen6 signal over around 500mm of PCB distance from the Strata Module to the front of the Orchid Module. In addition to having high quality SerDes, proper signal integrity is still achievable by upgrading PCB materials.

Context After

First, we must understand why high-speed signals perform worse on PCB versus flyover cables. As SerDes rates increase, high-speed channels become increasingly constrained by insertion loss introduced by PCB traces, vias, dielectric materials and conductor roughness. Insertion loss is defined as the signal power that is lost as a signal is traveling through an interconnect channel.

② Atomic Claim

即便如此，要讓 PCIe Gen6 signal 從 Strata Module 經約 500mm 的 PCB 距離走到 Orchid Module 前端，仍然很有挑戰。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe Gen6"
      },
      "role": "host_interface"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCB",
        "label": "PCB"
      },
      "role": "routing_medium"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVIDIA Strata Board",
        "label": "Strata Module"
      },
      "role": "source_module"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVIDIA Orchid Board",
        "label": "Orchid Module"
      },
      "role": "destination_module"
    }
  ],
  "qualifiers": {
    "condition_text": "approximately 500mm path",
    "numeric_mentions": [
      "500mm"
    ],
    "temporal_mentions": []
  },
  "relation_type": "PCIE6_LONG_REACH_PCB_CHALLENGE"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
host_interface	PCIe Gen6	PCIe
routing_medium	PCB	PCB
source_module	Strata Module	04_knowledge_base/NVIDIA Strata Board
destination_module	Orchid Module	04_knowledge_base/NVIDIA Orchid Board

⑤ V2 Draft（需要修正時直接編輯）

Inline repair

只編輯以下三個 Draft 區塊。完成後將 review_action 設為 REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。

V2 Atomic Claim Draft

即便如此，要讓 PCIe Gen6 signal 從 Strata Module 經約 500mm 的 PCB 距離走到 Orchid Module 前端，仍然很有挑戰。

V2 Semantic Frame Draft

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe Gen6"
      },
      "role": "host_interface"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCB",
        "label": "PCB"
      },
      "role": "routing_medium"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVIDIA Strata Board",
        "label": "Strata Module"
      },
      "role": "source_module"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVIDIA Orchid Board",
        "label": "Orchid Module"
      },
      "role": "destination_module"
    }
  ],
  "qualifiers": {
    "condition_text": "approximately 500mm path",
    "numeric_mentions": [
      "500mm"
    ],
    "temporal_mentions": []
  },
  "relation_type": "PCIE6_LONG_REACH_PCB_CHALLENGE"
}

V2 Revision Metadata Draft

{
  "epistemic_mode": "ASSERTED",
  "mapping_status": "COMPLETE"
}

⑥ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。