VR2R-0120::SPLIT04
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Vera - Line hint:
149
Context Before
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Evidence
NVIDIA was aggressive on the CPU front ↗, with Vera doubling performance over Grace by moving to a 3nm reticle-sized compute die and disaggregating the memory controllers and I/O into chiplets. Core count increases from 72 to 88, with 91 cores printed on die to leave redundancy for yield improvement. These cores mark the return of NVIDIA’s custom ARM CPU designs, with the ‘Olympus’ core now supporting SMT multi-threading for a total of 176 processing threads. L3 cache also received a 40% capacity bump to 162MB. Memory bus width doubled to 1024-bit and speed increased to 9600MT/s for 2.5x bandwidth, while maximum capacity tripled to 1.5TB with 8 SOCAMM modules. The NVLink-C2C to the Rubin GPUs also doubled in bandwidth to 1.8TB/s. PCIe6 and CXL3.1 are now supported as well. All this results in transistor count increasing 2.2x to 227 billion.
Context After
NVLink 6 Switch
② Atomic Claim
For Nvidia’s CPU design, Vera CPU disaggregates I/O into chiplets.
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "IO_DISAGGREGATION",
"context_nodes": [
{
"id": "02_companies/NVDA",
"label": "Nvidia"
},
{
"id": "04_knowledge_base/CPU",
"label": "CPU"
},
{
"id": "04_knowledge_base/Chiplet architecture",
"label": "chiplets"
}
],
"entity": {
"id": "04_knowledge_base/NVIDIA Vera CPU",
"label": "Vera CPU"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "For Nvidia’s CPU design, Vera CPU disaggregates I/O into chiplets."
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | Vera CPU | 04_knowledge_base/NVIDIA Vera CPU |
| context_0 | Nvidia | NVDA |
| context_1 | CPU | CPU |
| context_2 | chiplets | 04_knowledge_base/Chiplet architecture |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
For Nvidia’s CPU design, Vera CPU disaggregates I/O into chiplets.
V2 Semantic Frame Draft
{
"attribute": "IO_DISAGGREGATION",
"context_nodes": [
{
"id": "02_companies/NVDA",
"label": "Nvidia"
},
{
"id": "04_knowledge_base/CPU",
"label": "CPU"
},
{
"id": "04_knowledge_base/Chiplet architecture",
"label": "chiplets"
}
],
"entity": {
"id": "04_knowledge_base/NVIDIA Vera CPU",
"label": "Vera CPU"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "For Nvidia’s CPU design, Vera CPU disaggregates I/O into chiplets."
}
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。