VR2-0065
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Rubin - Line hint:
115
Context Before
Additionally, Nvidia claims up to an effective 50 PFLOPS of FP4 performance can be achieved with an updated 3rd generation Transformer Engine that replaces 2:4 structured sparsity from prior generations. We will detail this architectural feature for Rubin below.
Notably, the Tensor core width doubling only applies to FP4 and FP8, with BF16 and TF32 remaining the same as Blackwell, resulting in performance scaling only 1.6x of Blackwell. This architectural decision reflects NVIDIA’s belief that most training and inference workloads will move away from TF32 and BF16 and onto FP8 and FP4.
Evidence
On the memory front, the move to HBM4 means double the bus width per stack, running at 10.8 GT/s for 22TB/s total bandwidth or 2.75x Blackwell at the same 288GB capacity as GB300. Memory bandwidth has been upgraded significantly from the original 13TB/s advertised at GTC 2025. In order to catch up to AMD MI450’s memory bandwidth, Nvidia requested much higher HBM4 pin speeds from the DRAM suppliers - well above the speeds that was in the JEDEC specification for HBM4.
Context After
While Nvidia is targeting 22TB/s, we understand that memory suppliers are having challenges hitting Nvidia’s requirements and we see it likely that initial shipments will come in slightly below at closer to 20TB/s. We have discussed the implications to SK Hynix, Samsung, and Micron extensively for Accelerator and HBM model subscribers. ↗ Micron is well behind Samsung and Hynix and we believe they are effectively out of the picture for Rubin HBM4. ↗ We have more details on qualifications and pin speeds in the Accelerator and HBM model ↗
The NVLink-C2C chiplet houses the SerDes for the Vera CPU connection, doubled in bandwidth to 1.8TB/s, while the larger NVLink 6 chiplet on the other end of the chip features 36 custom ‘400G’ SerDes links for 2x NVLink bandwidth to all 72 Rubin GPUs.
② Atomic Claim
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "SPEED",
"context_nodes": [
{
"id": "04_knowledge_base/HBM4",
"label": "HBM4"
}
],
"entity": {
"id": "04_knowledge_base/Vera Rubin",
"label": "Rubin"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"10.8 GT/s"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"10.8 GT/s"
],
"value_text": "Rubin HBM4 運行速率為 10.8 GT/s。"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | Rubin | 04_knowledge_base/Vera Rubin |
| context_0 | HBM4 | HBM4 |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
V2 Semantic Frame Draft
{
"attribute": "SPEED",
"context_nodes": [
{
"id": "04_knowledge_base/HBM4",
"label": "HBM4"
}
],
"entity": {
"id": "04_knowledge_base/Vera Rubin",
"label": "Rubin"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"10.8 GT/s"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"10.8 GT/s"
],
"value_text": "Rubin HBM4 運行速率為 10.8 GT/s。"
}
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。