clm_e24146e954cd4c4fbb86e6975756d390_r2

VR2R-0207

回到這篇 SA Coverage

① SA Source

• Source: 開啟完整 SA 文章
• Section: Midplane
• Line hint: 311

Context Before

Source: Nvidia VR NVL72 BoM and Power Budget Model ↗

Evidence

The midplane acts as a bridge for the PCIe signal between the two Strata modules and the modules at the front of the chassis. The midplane module is vertically placed across the middle of the chassis with Paladin HD2 board-to-board connector on both sides of the module. Strata modules connect to one side of the midplane while the Orchid modules, the BlueField-4 module, the PDB module, and the management modules connects to the other side.

Context After

BlueField-4

② Atomic Claim

midplane 作為 PCIe signal bridge，連接兩個 Strata modules 與 chassis 前方的 modules。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/Midplane",
        "label": "midplane"
      },
      "role": "bridge"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe"
      },
      "role": "protocol"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVIDIA Strata Board",
        "label": "Strata module"
      },
      "role": "rear_module"
    }
  ],
  "qualifiers": {
    "condition_text": "other endpoint is front-of-chassis modules",
    "numeric_mentions": [
      "2"
    ],
    "temporal_mentions": []
  },
  "relation_type": "MIDPLANE_BRIDGES_PCIE_SIGNALS"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
bridge	midplane	Midplane
protocol	PCIe	PCIe
rear_module	Strata module	04_knowledge_base/NVIDIA Strata Board

⑤ V2 Draft（需要修正時直接編輯）

Inline repair

只編輯以下三個 Draft 區塊。完成後將 review_action 設為 REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。

V2 Atomic Claim Draft

midplane 作為 PCIe signal bridge，連接兩個 Strata modules 與 chassis 前方的 modules。

V2 Semantic Frame Draft

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/Midplane",
        "label": "midplane"
      },
      "role": "bridge"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe"
      },
      "role": "protocol"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVIDIA Strata Board",
        "label": "Strata module"
      },
      "role": "rear_module"
    }
  ],
  "qualifiers": {
    "condition_text": "other endpoint is front-of-chassis modules",
    "numeric_mentions": [
      "2"
    ],
    "temporal_mentions": []
  },
  "relation_type": "MIDPLANE_BRIDGES_PCIE_SIGNALS"
}

V2 Revision Metadata Draft

{
  "epistemic_mode": "ASSERTED",
  "mapping_status": "COMPLETE"
}

⑥ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。