VR2R-0558
① SA Source
- Source: 開啟完整 SA 文章
- Section:
GB200 Hardware Architecture - Component Supply Chain & BOM - Line hint:
711
Context Before
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Evidence
The diagram below shows how the NVLink 6 signal traverses through the tray. Each of the green lines represents nine 400G logical ports of NVLink 6, or 18 TX/RX lanes of 200G. Because there is only 1 DP per lane using bidirectional SerDes, there are a total of 18 DPs between any connector and any switch for a total of 72 DPs per connector, which is the same as prior generation of NVLink 5 Switch Tray.
Context After
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
② Atomic Claim
Reference topology 中每條 green line 代表 NVLink 6 的 9 個 400G logical ports，或 18 條 200G TX/RX lanes。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "REFERENCE_TOPOLOGY_PORT_AND_LANE_COUNT",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/NVLink",
"label": "NVLink 6"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": "reference topology",
"numeric_mentions": [
"9",
"400G",
"18",
"200G"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"9",
"400G",
"18",
"200G"
],
"value_text": "each green line represents nine 400G logical ports or eighteen 200G TX/RX lanes."
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | NVLink 6 | NVLink |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
Reference topology 中每條 green line 代表 NVLink 6 的 9 個 400G logical ports，或 18 條 200G TX/RX lanes。
V2 Semantic Frame Draft
{
"attribute": "REFERENCE_TOPOLOGY_PORT_AND_LANE_COUNT",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/NVLink",
"label": "NVLink 6"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": "reference topology",
"numeric_mentions": [
"9",
"400G",
"18",
"200G"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"9",
"400G",
"18",
"200G"
],
"value_text": "each green line represents nine 400G logical ports or eighteen 200G TX/RX lanes."
}
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。