VR-COV-VR-CCL-FOIL
① SA Source
- Source: 開啟完整 SA 文章
- Section:
PCB vs Flyover Cables - Line hint:
421
Context Before
Nevertheless, it is still challenging to drive a PCIe Gen6 signal over around 500mm of PCB distance from the Strata Module to the front of the Orchid Module. In addition to having high quality SerDes, proper signal integrity is still achievable by upgrading PCB materials.
First, we must understand why high-speed signals perform worse on PCB versus flyover cables. As SerDes rates increase, high-speed channels become increasingly constrained by insertion loss introduced by PCB traces, vias, dielectric materials and conductor roughness. Insertion loss is defined as the signal power that is lost as a signal is traveling through an interconnect channel.
Evidence
Context After
Source: Doosan, SemiAnalysis
The three main mechanisms contributing to insertion loss in a PCB channel are conductor loss from skin effect and copper surface roughness, dielectric loss from laminate absorption, and geometry loss from discontinuities such as vias and layer changes.
② Atomic Claim
The CCL composition illustration identifies copper foil as the conductive layer.
- Epistemic Mode:
ATTRIBUTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "COPPER_FOIL_FUNCTION",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/高階CCL",
"label": "高階CCL"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "conductive layer"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | 高階CCL | 04_knowledge_base/高階CCL |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
The CCL composition illustration identifies copper foil as the conductive layer.
V2 Semantic Frame Draft
{
"attribute": "COPPER_FOIL_FUNCTION",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/高階CCL",
"label": "高階CCL"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "conductive layer"
}
}V2 Revision Metadata Draft
{
"epistemic_mode": "ATTRIBUTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。