VR2R-0079::SPLIT04
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Rubin - Line hint:
119
Context Before
On the memory front, the move to HBM4 means double the bus width per stack, running at 10.8 GT/s for 22TB/s total bandwidth or 2.75x Blackwell at the same 288GB capacity as GB300. Memory bandwidth has been upgraded significantly from the original 13TB/s advertised at GTC 2025. In order to catch up to AMD MI450’s memory bandwidth, Nvidia requested much higher HBM4 pin speeds from the DRAM suppliers - well above the speeds that was in the JEDEC specification for HBM4.
While Nvidia is targeting 22TB/s, we understand that memory suppliers are having challenges hitting Nvidia’s requirements and we see it likely that initial shipments will come in slightly below at closer to 20TB/s. We have discussed the implications to SK Hynix, Samsung, and Micron extensively for Accelerator and HBM model subscribers. ↗ Micron is well behind Samsung and Hynix and we believe they are effectively out of the picture for Rubin HBM4. ↗ We have more details on qualifications and pin speeds in the Accelerator and HBM model ↗
Evidence
Context After
Transistor count has climbed 60% to 336 billion.
A notable omission from Rubin is the mention of Sparse FLOPs. In previous generations, 2:4 structured sparsity was used to double marketing FLOPs numbers. However, adoption was minimal especially at low precisions due to accuracy losses from the rigid sparsity structure forcing half of the values to be zero. Programmers basically ignored structured sparsity as it was not useful, which caused hardware designs to change as well. Blackwell Ultra GB300 added 50% more dense FP4 while keeping sparse FP4 FLOPs the same, while AMD’s MI355X stopped supporting structured sparsity on MXFP8, MXFP6 and MXFP4 formats to save silicon area.
② Atomic Claim
較大的 NVLink 6 chiplet 對全部 72 顆 Rubin GPU 提供 2 倍 NVLink bandwidth。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/NVLink",
"label": "NVLink 6"
},
"role": "bandwidth_source"
},
{
"node": {
"id": "04_knowledge_base/Vera Rubin",
"label": "Rubin"
},
"role": "platform"
},
{
"node": {
"id": "04_knowledge_base/GPU",
"label": "GPU"
},
"role": "bandwidth_endpoint_type"
}
],
"qualifiers": {
"condition_text": "to all 72 Rubin GPUs",
"numeric_mentions": [
"2x",
"72 GPUs"
],
"temporal_mentions": []
},
"relation_type": "NVLINK_BANDWIDTH_DOUBLED_TO_ENDPOINTS"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| bandwidth_source | NVLink 6 | NVLink |
| platform | Rubin | 04_knowledge_base/Vera Rubin |
| bandwidth_endpoint_type | GPU | GPU |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
較大的 NVLink 6 chiplet 對全部 72 顆 Rubin GPU 提供 2 倍 NVLink bandwidth。
V2 Semantic Frame Draft
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/NVLink",
"label": "NVLink 6"
},
"role": "bandwidth_source"
},
{
"node": {
"id": "04_knowledge_base/Vera Rubin",
"label": "Rubin"
},
"role": "platform"
},
{
"node": {
"id": "04_knowledge_base/GPU",
"label": "GPU"
},
"role": "bandwidth_endpoint_type"
}
],
"qualifiers": {
"condition_text": "to all 72 Rubin GPUs",
"numeric_mentions": [
"2x",
"72 GPUs"
],
"temporal_mentions": []
},
"relation_type": "NVLINK_BANDWIDTH_DOUBLED_TO_ENDPOINTS"
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。