VR2R-0562
① SA Source
- Source: 開啟完整 SA 文章
- Section:
GB200 Hardware Architecture - Component Supply Chain & BOM - Line hint:
717
Context Before
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Evidence
As previously explained, high speed signals require better PCB materials, especially for NVLink 6 which has much lower tolerance for insertion loss given the use of bidirectional signaling. The number of lanes between the PaladinHD2 connectors and the NVLink Switch also creates complexity for PCB design. Hence, the NVLink 6 Switch board PCB is upgraded to 32 layers with M8+ graded CCL - minimally LDK2 glass fiber cloth or potentially Quartz fiber cloth.
Context After
We have more details on the switch tray and various components in the VR NVL72 Component BoM and Power Budget Model ↗.
Zooming out, backplane copper cables are used to connect NVLink Switch trays to the GPU trays for the VR NVL72 system. Although the bandwidth doubles, with bi-directional SerDes, the number of cables required does not change from the GB300 backplane generation to the Vera Rubin NVL72 backplane generation. The number of connectors and the number of DPs per connector also does not change from Grace Blackwell NVL72 to VR NVL72.
② Atomic Claim
PaladinHD2 connectors 與 NVLink Switch 之間的 lane 數量，也提高了 PCB design complexity。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/Paladin connector",
"label": "PaladinHD2"
},
"role": "connector"
},
{
"node": {
"id": "04_knowledge_base/NVLink",
"label": "NVLink"
},
"role": "switch_interconnect"
},
{
"node": {
"id": "04_knowledge_base/PCB",
"label": "PCB"
},
"role": "board"
}
],
"qualifiers": {
"condition_text": "lane count between PaladinHD2 connectors and NVLink Switch",
"numeric_mentions": [],
"temporal_mentions": []
},
"relation_type": "LANE_COUNT_DRIVES_PCB_DESIGN_COMPLEXITY"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| connector | PaladinHD2 | 04_knowledge_base/Paladin connector |
| switch_interconnect | NVLink | NVLink |
| board | PCB | PCB |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
PaladinHD2 connectors 與 NVLink Switch 之間的 lane 數量，也提高了 PCB design complexity。
V2 Semantic Frame Draft
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/Paladin connector",
"label": "PaladinHD2"
},
"role": "connector"
},
{
"node": {
"id": "04_knowledge_base/NVLink",
"label": "NVLink"
},
"role": "switch_interconnect"
},
{
"node": {
"id": "04_knowledge_base/PCB",
"label": "PCB"
},
"role": "board"
}
],
"qualifiers": {
"condition_text": "lane count between PaladinHD2 connectors and NVLink Switch",
"numeric_mentions": [],
"temporal_mentions": []
},
"relation_type": "LANE_COUNT_DRIVES_PCB_DESIGN_COMPLEXITY"
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。