VR2R-0131
① SA Source
- Source: 開啟完整 SA 文章
- Section:
NVLink 6 Switch - Line hint:
157
Context Before
Source: Nvidia VR NVL72 Component BoM and Power Budget Model ↗
Evidence
While the rack-level switching bandwidth has doubled, the number of NVLink Switch chips per rack has also doubled to 36, with each switch tray now housing 4 Switch chips. This means the new NVLink 6 Switch chip has the same 28.8T bandwidth as NVLink5 Switch, with half the number of ports but running at double the rate using ‘400G’ bi-directional SerDes. This allows the high bandwidth switch design to remain as a single monolithic die, saving on design complexity. The layout remains the same as NVIDIA’s previous switches, with 2 sides for IO and a central logic section crossbar and 3.6 TFlop SHARP in-network compute acceleration.
Context After
ConnectX-9
② Atomic Claim
The described NVLink 6 SerDes design allows the high-bandwidth switch to remain a single monolithic die, reducing design complexity.
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"frame_type": "CLAIM_ONLY",
"qualifiers": {
"condition_text": "This 指涉前述 400G SerDes design",
"numeric_mentions": [],
"temporal_mentions": []
},
"reason": "SWITCH_AND_MONOLITHIC_DIE_SUBJECTS_NOT_CANONICALIZED_IN_CLAIM",
"statement": "The described NVLink 6 SerDes design allows the high-bandwidth switch to remain a single monolithic die, reducing design complexity."
}④ Canonical Entity Mapping
- 此
CLAIM_ONLYrevision 沒有 canonical Entity mapping。
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
The described NVLink 6 SerDes design allows the high-bandwidth switch to remain a single monolithic die, reducing design complexity.
V2 Semantic Frame Draft
{
"frame_type": "CLAIM_ONLY",
"qualifiers": {
"condition_text": "This 指涉前述 400G SerDes design",
"numeric_mentions": [],
"temporal_mentions": []
},
"reason": "SWITCH_AND_MONOLITHIC_DIE_SUBJECTS_NOT_CANONICALIZED_IN_CLAIM",
"statement": "The described NVLink 6 SerDes design allows the high-bandwidth switch to remain a single monolithic die, reducing design complexity."
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "PARTIAL"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。