VR2R-0723
① SA Source
- Source: 開啟完整 SA 文章
- Section:
VR NVL72 TCO: BoM and Power Budget Analysis - Line hint:
967
Context Before
Source: SemiAnalysis AI TCO Model ↗
The MI4XX currently has a performance per TCO advantage based on marketed dense FLOPS over VR. VR has a higher TCO per GPU compared to MI4XX, yet VR marketed PFLOPs are lower vs MI4XX resulting in a TCO per PFLOP disadvantage for the VR vs MI4XX.
Evidence
NVIDIA is offering sparsity for FP4, marketing 50 PFLOPS of FP4, while AMD has opsted to remove sparsity support since CDNA4 for inference dtypes. Harnessing the 50 PFLOPS sparse vs 35 PFLOPS dense drops the cost per perf in units of $/hr per Marketed PFLOP by 35% – a valid comparison if AI Labs can indeed successfully harness Sparse FP4 on the VR NVL72.
Context After
As always, one caveat is that this comparison is done based on a marketed dense PFLOP basis. Effective dense PFLOP (i.e. the real world chip throughput) can differ based on Model Flops Utilization % (MFU), and in general we have seen NVIDIA chip operate at a higher MFU % vs AMD chips, suggesting that performance per TCO based on effective dense PFLOPs could be better for NVIDIA systems vs AMD – however, MFU is dependent on actual workloads with no one-size-fits-all MFU % that is consistently applicable to either systems.
Indeed, real world use of FP4 Sparsity will probably not reach 50 PFLOPS but it will probably deliver better effective FLOPs than FP4 Dense, but we have yet to evaluate what that real-world performance could be. Running VR NVL72 on 1800W would probably mean lower FP4 Sparse FLOPs than on 2300W.
② Atomic Claim
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "02_companies/AMD",
"label": "AMD"
},
"role": "vendor"
},
{
"node": {
"id": "04_knowledge_base/Sparsity",
"label": "sparsity"
},
"role": "feature"
}
],
"qualifiers": {
"condition_text": "inference dtypes",
"numeric_mentions": [
"CDNA4"
],
"temporal_mentions": [
"since CDNA4"
]
},
"relation_type": "AMD_REMOVES_SPARSITY_FOR_INFERENCE_DTYPES_SINCE_CDNA4"
}④ Canonical Entity Mapping
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
AMD 自 CDNA4 起，已選擇在 inference dtypes 移除 sparsity support。
V2 Semantic Frame Draft
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "02_companies/AMD",
"label": "AMD"
},
"role": "vendor"
},
{
"node": {
"id": "04_knowledge_base/Sparsity",
"label": "sparsity"
},
"role": "feature"
}
],
"qualifiers": {
"condition_text": "inference dtypes",
"numeric_mentions": [
"CDNA4"
],
"temporal_mentions": [
"since CDNA4"
]
},
"relation_type": "AMD_REMOVES_SPARSITY_FOR_INFERENCE_DTYPES_SINCE_CDNA4"
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。