VR2R-0084::SPLIT02
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Rubin - Line hint:
123
Context Before
The NVLink-C2C chiplet houses the SerDes for the Vera CPU connection, doubled in bandwidth to 1.8TB/s, while the larger NVLink 6 chiplet on the other end of the chip features 36 custom ‘400G’ SerDes links for 2x NVLink bandwidth to all 72 Rubin GPUs.
Transistor count has climbed 60% to 336 billion.
Evidence
A notable omission from Rubin is the mention of Sparse FLOPs. In previous generations, 2:4 structured sparsity was used to double marketing FLOPs numbers. However, adoption was minimal especially at low precisions due to accuracy losses from the rigid sparsity structure forcing half of the values to be zero. Programmers basically ignored structured sparsity as it was not useful, which caused hardware designs to change as well. Blackwell Ultra GB300 added 50% more dense FP4 while keeping sparse FP4 FLOPs the same, while AMD’s MI355X stopped supporting structured sparsity on MXFP8, MXFP6 and MXFP4 formats to save silicon area.
Context After
Rubin’s adaptive compression engine in the improved Transformer Engine is a key feature to re-boost naturally sparser inference performance by doing dynamic computation of sparsity in-flight and eliminating zeros in the data stream without zeroing out non-zero values, thus maintaining model accuracy while still boosting performance. This is done automatically on existing models built for Blackwell without the need for a new programming model or specific optimizations. While models that utilize Post Training Quantization or Quantization Aware Training will be tuned to maximize adaptive compression speedups, they are not strictly needed to take advantage of dynamic compression.
This means the sparser the workload, the closer the performance will be to the 50 PFLOPS marketed peak performance. NVIDIA thus brands the 50 PFLOPS figure as FP4 Inference while the 35 PFLOPS FP4 Training number is for dense workloads. As accuracy is preserved, this allows the marketing team to claim 5x FLOPs for Rubin over GB200, comparing 50 PFLOPS dynamically compressed FP4 to 10 PFLOPS dense FP4. Whether actual GEMM performance reaches 50 PFLOPS depends on how many zeros are in the tensor. The more zeros, the closer it can reach. The less zeros in the tensor, the lower the speedup. Overall, we expect to see much greater traction for Rubin’s adaptive sparsity compression as opposed to structured sparsity thanks to the automatic implementation.
② Atomic Claim
Programmers 對 structured sparsity 的低採用促使 hardware designs 隨之改變。
- Epistemic Mode:
ASSERTED - Mapping Status:
CLAIM_ONLY
③ Semantic Frame
{
"frame_type": "CLAIM_ONLY",
"qualifiers": {
"condition_text": "caused by programmer non-adoption of structured sparsity",
"numeric_mentions": [],
"temporal_mentions": []
},
"reason": "GENERIC_HARDWARE_DESIGN_CHANGE_NOT_CANONICALIZED",
"statement": "Low programmer adoption of structured sparsity caused hardware designs to change as well."
}④ Canonical Entity Mapping
- 此
CLAIM_ONLYrevision 沒有 canonical Entity mapping。
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
Programmers 對 structured sparsity 的低採用促使 hardware designs 隨之改變。
V2 Semantic Frame Draft
{
"frame_type": "CLAIM_ONLY",
"qualifiers": {
"condition_text": "caused by programmer non-adoption of structured sparsity",
"numeric_mentions": [],
"temporal_mentions": []
},
"reason": "GENERIC_HARDWARE_DESIGN_CHANGE_NOT_CANONICALIZED",
"statement": "Low programmer adoption of structured sparsity caused hardware designs to change as well."
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "CLAIM_ONLY"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。