2025-06-13_amd-advancing-ai-mi350x-and-mi400-ualoe72-mi500-ual256::AMD25-0023
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Introducing the MI400 Helios Rack - Line hint:
345
Context Before

Source: AMD, SemiAnalysis Estimates
Evidence
Context After
We have already discussed the different level of memory access in the previous AMD ↗ 2.0 article ↗. With the exception of HBM memory, all other system memory capacity is customizable and can be tailored to customer request.

② Atomic Claim
MI400 compute tray 將 LPDDR5 放在 GPU 兩側,Venice CPU 位於 tray 前方,並有 12 個 MRDIMM slots。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/MI400",
"label": "MI400"
},
"role": "gpu"
},
{
"node": {
"id": "04_knowledge_base/LPDDR5",
"label": "LPDDR5"
},
"role": "memory"
},
{
"node": {
"id": "04_knowledge_base/AMD Venice",
"label": "Venice"
},
"role": "cpu"
},
{
"node": {
"id": "04_knowledge_base/MRDIMM",
"label": "MRDIMM"
},
"role": "dimm"
},
{
"node": {
"id": "04_knowledge_base/Compute Tray",
"label": "Compute Tray"
},
"role": "tray"
}
],
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"12"
],
"temporal_mentions": []
},
"relation_type": "MI400_COMPUTE_TRAY_MEMORY_CPU_LAYOUT"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| gpu | MI400 | MI400 |
| memory | LPDDR5 | LPDDR5 |
| cpu | Venice | 04_knowledge_base/AMD Venice |
| dimm | MRDIMM | MRDIMM |
| tray | Compute Tray | 04_knowledge_base/Compute Tray |
⑤ Human Review
請在 Properties 逐項確認:
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。