clm_153018ae7d394b7392c6ead565afff30_r1

2025-06-13_amd-advancing-ai-mi350x-and-mi400-ualoe72-mi500-ual256::AMD25-0025

① SA Source

• Source: 開啟完整 SA 文章
• Section: Introducing the MI400 Helios Rack
• Line hint: 363

Context Before

Within the compute tray, the scale-up link will function for the most part the same as we estimated back in April. The major difference when it comes to scale-up is once again the name change of the scale up link from IFoE to UALoE, but the scale up bandwidth of MI400s of 1.8TB/s (uni-directional) per GPU achieved using 72 lanes of 200Gbit/s each is the same as we estimated previously.

As a result of this, at least at the marketing level, most of the flexible I/O lanes coming out of the GPU will be on the UALink protocol: UALink to the Vulcano NICs, xGMI4 (a subset of UALink) to the CPU, and the aforementioned UALoE for the scale up network for communicating with GPUs in different compute trays. In the chart we colored all the “UALink” protocol lanes as purple.

Evidence

The MI450X GPU will have direct access to three different levels of memory, which indicates that the rack solution will be optimized for inference workloads as the availability of multiple memory tiers enables more efficient KVCaching.

Context After

In-package HBM (288GB/432GB, 18TB/s)

② Atomic Claim

MI450X GPU 預計可直接存取三層 memory；SemiAnalysis 認為此 multi-tier memory 設計有利 inference 的 KV caching。

• Epistemic Mode: EXPECTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "memory_tiers",
  "context_nodes": [
    {
      "id": "04_knowledge_base/GPU",
      "label": "GPU"
    },
    {
      "id": "04_knowledge_base/KV cache",
      "label": "KV cache"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/AMD MI450X",
    "label": "MI450X"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "3"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "3"
    ],
    "value_text": "direct access to three levels of memory; optimized for inference/KV caching"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	MI450X	04_knowledge_base/AMD MI450X
context_0	GPU	GPU
context_1	KV cache	04_knowledge_base/KV cache

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。