clm_c66e69a7d75a4980b55e07f00942d171_r1

GB2-0035

① SA Source

• Source: 開啟完整 SA 文章
• Section: NVLink Scale Up Interconnect
• Line hint: 297

Context Before

Source: SemiAnalysis

Nvidia claims that if they used optics with transceivers, they would have needed to add 20kW per NVL72 rack. We did the math and calculated that it would need to use 648 1.6T twin port transceivers with each transceiver consuming approximately 30Watts so the math works out to be 19.4kW/rack which is basically the same as Nvidia’s claim. At about $850per[[04_{k}nowledg{e}_{b}ase/1.6T|1.6T]]transceiver,thisworksouttobe$550,800 per rack in just transceiver costs alone. When you mark that up by Nvidia’s 75% gross margin, that would mean $2,203,200 per rack of NVLink transceivers that the end customer would need to pay. This is one of the main reasons why DGX H100 NVL256 never shipped due to the massive cost of transceivers. ↗ Furthermore, bleeding edge transceivers like the 1.6T NVLink transceivers have way worse reliability compared to copper cables or even prior generation optics.

Evidence

Each GPU has 900GB/s unidirectional bandwidth. Each differential pair (DP) is capable of transmitting 200Gb/s in 1 direction thus it will take 72 DP per GPU for both directions. Since there are 72 GPUs per NVL72 rack, that would mean there is 5184 differential pairs.

Context After

This is a massive increase in copper content generation on generation. In a bit of a whiplash, we have seen some investors estimate that there is around $3kof[[04_{k}nowledg{e}_{b}ase/NVLink|NVLink]]interconnectcontentper[[04_{k}nowledg{e}_{b}ase/GPU|GPU]]bringingthetotalto$216k/NVL72 rack but this is completely wrong.

② Atomic Claim

NVL72 每顆 GPU 為 900GB/s 單向頻寬，每 differential pair 為 200Gb/s 單向；雙向每 GPU 需 72 DP，72 顆 GPU 合計 5,184 DPs。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "nvlink_differential_pair_count",
  "context_nodes": [
    {
      "id": "04_knowledge_base/GPU",
      "label": "GPU"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/GB200 NVL72",
    "label": "GB200 NVL72"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "900GB/s",
      "200Gb/s",
      "72",
      "72",
      "5184"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "900GB/s",
      "200Gb/s",
      "72",
      "72",
      "5184"
    ],
    "value_text": "72 DP per GPU; 72 GPUs -> 5,184 differential pairs"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	GB200 NVL72	04_knowledge_base/GB200 NVL72
context_0	GPU	GPU

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。