SA260324R-0326
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Feynman NVL1152 Networking Topologies - Line hint:
412
Context Before
To double the scale-up bandwidth using copper interconnect, NVIDIA would have to achieve a per lane bandwidth of 448Gbit/s uni-di (and implemented with simultaneous bi-directional SerDes so that each physical channel carries 448G of RX and 448G of TX). However, this is a challenging feat as they would first have to prove the feasibility of 448Gb/s PAM4 SerDes at large volumes, then implement echo cancellation to achieve bidirectional bandwidth, which is in itself extremely difficult. We believe Nvidia is going for 448G uni-di only.
Evidence
Context After
and thin fiber strands can be used to connect the optical connectors to the NVLink 8 Switches in place of flyover cables, but we believe this is very unlikely.
② Atomic Claim
Feynman 可能採用 in-rack optics,讓 switch blade 透過 optical connector blind-mate 到 midplane。
- Epistemic Mode:
HYPOTHETICAL - Mapping Status:
PARTIAL
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/NVIDIA Feynman Architecture",
"label": "Feynman"
},
"role": "generation"
},
{
"node": {
"id": "04_knowledge_base/Midplane",
"label": "midplane"
},
"role": "midplane"
}
],
"qualifiers": {
"condition_text": "switch blade, optics, and optical connector are not canonical-linked in this atomic claim",
"numeric_mentions": [],
"temporal_mentions": []
},
"relation_type": "HYPOTHETICAL_FEYNMAN_IN_RACK_OPTICS"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| generation | Feynman | 04_knowledge_base/NVIDIA Feynman Architecture |
| midplane | midplane | Midplane |
⑤ Human Review
請在 Properties 逐項確認:
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。