SA260324R-0322
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Feynman NVL1152 Networking Topologies - Line hint:
404
Context Before
Within each Feynman Kyber rack, we tentatively assume double the bandwidth per logical GPU and double the NVLink Switch bandwidth to 28.8T and 57.6T respectively. Though Jensen, in the Financial Q+A the day after the GTC Keynote, characterized NVL1152 as “all CPO”, the key technical blog outlining the new rack form factors only strictly referenced CPO for rack to rack interconnect.
Evidence
We will discuss the potential topography for both options.
Context After
To double the scale-up bandwidth using copper interconnect, NVIDIA would have to achieve a per lane bandwidth of 448Gbit/s uni-di (and implemented with simultaneous bi-directional SerDes so that each physical channel carries 448G of RX and 448G of TX). However, this is a challenging feat as they would first have to prove the feasibility of 448Gb/s PAM4 SerDes at large volumes, then implement echo cancellation to achieve bidirectional bandwidth, which is in itself extremely difficult. We believe Nvidia is going for 448G uni-di only.
② Atomic Claim
SemiAnalysis 表示，後續會討論這兩種 option 的可能 topology。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"frame_type": "CLAIM_ONLY",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"reason": "META_TRANSITION_TO_HYPOTHETICAL_TOPOLOGIES",
"statement": "SemiAnalysis 表示，後續會討論這兩種 option 的可能 topology。"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| — | — | — |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。