SA260324R-0296_r1

SA260324R-0296

① SA Source

• Source: 開啟完整 SA 文章
• Section: CMX
• Line hint: 374

Context Before

KV cache grows linearly with input sequence length and number of users and is the primary tradeoff when it comes to prefill performance (time to first token). At scale, on-device HBM does not have enough capacity. Host DRAM extends beyond HBM capacity with an additional tier of cache, but also hits limits on total amount per node, memory bandwidth, and network bandwidth.

Evidence

Enter NVMe storage for additional KVcache offload.

Context After

NVIDIA introduced a “new” intermediate storage “tier G3.5” within the inference memory hierarchy at CES in January. Tier G3.5 NVMe sits in between tier G3 DRAM and tier G4 shared storage (also NVMe, or SATA/SAS SSD, or HDD). Previously referred to as ICMS (Inference Context Memory Storage) and now branded as the CMX platform, this is just another re-brand of storage servers attached to compute servers via Bluefield NICs. The only difference from NVMe architectures is the swap from Connect-X NICs to Bluefield NICs.

② Atomic Claim

因此可使用 NVMe storage，進一步 offload KV cache。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "additional_nodes": [],
  "frame_type": "RELATION",
  "object": {
    "id": "04_knowledge_base/KV cache",
    "label": "KV cache"
  },
  "predicate": "ENABLES_OFFLOAD_OF",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "subject": {
    "id": "04_knowledge_base/NVMe",
    "label": "NVMe"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
subject	NVMe	NVMe
object	KV cache	04_knowledge_base/KV cache

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。