SA260324R-0203
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Nvidia's CPO Roadmap - Line hint:
241
Context Before
Nvidia’s approach has been to use copper where they can, and optics where they must. The architecture of NVL1152 in the Feynman generation will follow the same principle. It is clear that the NVL1152 will adopt CPO to connect between racks, but from GPUs to NVLink Switches is currently copper POR.
Evidence
Nvidia is unable to achieve another doubling of electrical lane speed from 224Gbit/s bi-di to 448Gbit/s uni-di means bandwidth isn’t that amazing.
Context After
While 448G high speed SerDes have big challenges for shoreline, reach, and power versus using a die-to-die connection to an optical engine, the manufacturing challenges, cost, and reliability for Feynman necessitate using copper to the Switch.
② Atomic Claim
Nvidia 無法再把 electrical lane speed 從 224Gbit/s bi-di 翻倍到 448Gbit/s uni-di，因此可提供的 bandwidth 並沒有大幅提升。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "ELECTRICAL_LANE_SPEED_SCALING_LIMIT",
"context_nodes": [],
"entity": {
"id": "02_companies/NVDA",
"label": "Nvidia"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"224Gbit/s",
"448Gbit/s"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"224Gbit/s",
"448Gbit/s"
],
"value_text": "無法把 electrical lane speed 從 224Gbit/s bi-di 再翻倍到 448Gbit/s uni-di，因此 bandwidth 提升有限。"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | Nvidia | NVDA |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。