SA260324R-0179_r1

SA260324R-0179

① SA Source

• Source: 開啟完整 SA 文章
• Section: Inter-node/Intra-rack
• Line hint: 215

Context Before

This means that each node has 16 x 15 x 2 lanes for inter-node C2C and

Evidence

2 x 15 lanes for inter-node FPGA which is a total of 510 lanes or 1020 differential pairs (for Rx and Tx).

Context After

Therefore, the backplane is 16 x 1020/2 = 8,160 differential pairs – we divide by 2 as each device Tx channel is a corresponding device’s Rx channel.

② Atomic Claim

inter-node FPGA 則有 2×15 lanes，使總數達到 510 lanes，也就是 1020 differential pairs（Rx 與 Tx）。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "INTER_NODE_LANE_COUNT",
  "context_nodes": [],
  "entity": {
    "id": "04_knowledge_base/FPGA",
    "label": "FPGA"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "2x15",
      "510",
      "1020"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "2x15",
      "510",
      "1020"
    ],
    "value_text": "inter-node FPGA 為 2×15 lanes；加總後為 510 lanes、1020 differential pairs（Rx 與 Tx）。"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	FPGA	FPGA

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。