SA260324R-0172_r1

SA260324R-0172

① SA Source

• Source: 開啟完整 SA 文章
• Section: Intra-Tray Topology
• Line hint: 207

Context Before

The LPU also has 1x100G going to one FPGA, with each FPGA interfacing with 8 LPUs. The 2 FPGAs each have 8x PCIe Gen 5 going to the CPUs.

Evidence

The LPU needs to traverse through the FPGA to interface with the CPU as LPUs don’t have PCIe PHYs to interface directly.

Context After

② Atomic Claim

LPU 必須經過 FPGA 才能和 CPU 介接，因為 LPU 沒有 PCIe PHY 可以直接連線。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/Groq LPU",
        "label": "LPU"
      },
      "role": "source_device"
    },
    {
      "node": {
        "id": "04_knowledge_base/FPGA",
        "label": "FPGA"
      },
      "role": "bridge"
    },
    {
      "node": {
        "id": "04_knowledge_base/CPU",
        "label": "CPU"
      },
      "role": "destination_device"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe"
      },
      "role": "protocol"
    }
  ],
  "qualifiers": {
    "condition_text": "LPU 沒有 PCIe PHY 可直接介接 CPU",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "REQUIRES_FPGA_BRIDGE_TO_CPU"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
source_device	LPU	04_knowledge_base/Groq LPU
bridge	FPGA	FPGA
destination_device	CPU	CPU
protocol	PCIe	PCIe

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。