SA260324R-0170

① SA Source

Context Before

This is why the belly-to-belly layout is used: it reduces the ‘X’ and ‘Y’ distance between all the LPUs and instead have routing go in the ‘Z’ dimension.

Evidence

The LPU also has 1x100G going to one FPGA, with each FPGA interfacing with 8 LPUs.

Context After

The 2 FPGAs each have 8x PCIe Gen 5 going to the CPUs. The LPU needs to traverse through the FPGA to interface with the CPU as LPUs don’t have PCIe PHYs to interface directly.

② Atomic Claim

LPU 另有 1×100G 連到一顆 FPGA,而每顆 FPGA 會介接 8 顆 LPU。

  • Epistemic Mode: ASSERTED
  • Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/Groq LPU",
        "label": "LPU"
      },
      "role": "accelerator"
    },
    {
      "node": {
        "id": "04_knowledge_base/FPGA",
        "label": "FPGA"
      },
      "role": "fabric_expansion_logic"
    }
  ],
  "qualifiers": {
    "condition_text": "each FPGA interfaces with 8 LPUs",
    "numeric_mentions": [
      "1x100G",
      "1",
      "8"
    ],
    "temporal_mentions": []
  },
  "relation_type": "LPU_FPGA_CONNECTIVITY"
}

④ Canonical Entity Mapping

RoleSurface LabelCanonical Target
acceleratorLPU04_knowledge_base/Groq LPU
fabric_expansion_logicFPGAFPGA

⑤ Human Review

請在 Properties 逐項確認:

  • 原文 → Atomic Claim 是否忠實
  • Atomic Claim → Semantic Frame 是否忠實
  • Canonical Entity mapping 是否正確
  • Epistemic mode 是否保留原文語氣
  • 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。