SA260324R-0154_r1

SA260324R-0154

① SA Source

• Source: 開啟完整 SA 文章
• Section: LPX Compute Tray
• Line hint: 189

Context Before

Third, the FPGAs are connected to the backplane to talk to other FPGAs in the node, we believe this is to help manage control flow and timing of all the LPUs. The FPGAs also bring extra system DRAM of up to 256GB each.

Evidence

This pool of memory can be used for KVCache if the user wants the entire decode process served by the LPX.

Context After

On the front panel there are 8 x OSFP cages for cross-rack C2C, while there will be 2 cages (likely QSFP-DD) that goes to the Spectrum-switches that is used to connect the LPUs and the GPUs for the disaggregated decode system. We will share more about this when we describe the network.

② Atomic Claim

如果使用者希望整個 decode process 都由 LPX 提供服務，這個 memory pool 可以拿來存放 KVCache。

• Epistemic Mode: HYPOTHETICAL
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/KV cache",
        "label": "KVCache"
      },
      "role": "cache"
    },
    {
      "node": {
        "id": "04_knowledge_base/Decode",
        "label": "decode"
      },
      "role": "process"
    },
    {
      "node": {
        "id": "04_knowledge_base/Groq LPX",
        "label": "LPX"
      },
      "role": "serving_system"
    }
  ],
  "qualifiers": {
    "condition_text": "memory pool 指涉前文 FPGA 提供的額外 DRAM",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "MEMORY_POOL_CAN_SERVE_KV_CACHE"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
cache	KVCache	04_knowledge_base/KV cache
process	decode	Decode
serving_system	LPX	04_knowledge_base/Groq LPX

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。