SA260324R-0153_r1

SA260324R-0153

① SA Source

• Source: 開啟完整 SA 文章
• Section: LPX Compute Tray
• Line hint: 189

Context Before

Third, the FPGAs are connected to the backplane to talk to other FPGAs in the node, we believe this is to help manage control flow and timing of all the LPUs.

Evidence

The FPGAs also bring extra system DRAM of up to 256GB each.

Context After

This pool of memory can be used for KVCache if the user wants the entire decode process served by the LPX.

② Atomic Claim

每顆 FPGA 還可提供最高 256GB 的額外 system DRAM。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "additional_nodes": [],
  "frame_type": "RELATION",
  "object": {
    "id": "04_knowledge_base/DRAM",
    "label": "DRAM"
  },
  "predicate": "PROVIDES_EXTRA_MEMORY",
  "qualifiers": {
    "condition_text": "per FPGA",
    "numeric_mentions": [
      "256GB"
    ],
    "temporal_mentions": []
  },
  "subject": {
    "id": "04_knowledge_base/FPGA",
    "label": "FPGA"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
subject	FPGA	FPGA
object	DRAM	DRAM

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。