SA260324R-0152_r1

SA260324R-0152

① SA Source

• Source: 開啟完整 SA 文章
• Section: LPX Compute Tray
• Line hint: 189

Context Before

Second, the LPUs also traverse through the FPGAs to reach the host CPU, with the FPGAs converting C2C to PCIe to the CPU.

Evidence

Third, the FPGAs are connected to the backplane to talk to other FPGAs in the node, we believe this is to help manage control flow and timing of all the LPUs.

Context After

The FPGAs also bring extra system DRAM of up to 256GB each. This pool of memory can be used for KVCache if the user wants the entire decode process served by the LPX.

② Atomic Claim

第三，FPGA 會連到 backplane，以和 node 內其他 FPGA 溝通；SemiAnalysis 認為這可能是為了協助管理所有 LPU 的 control flow 與 timing。

• Epistemic Mode: EXPECTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/FPGA",
        "label": "FPGA"
      },
      "role": "controller"
    },
    {
      "node": {
        "id": "04_knowledge_base/Backplane",
        "label": "backplane"
      },
      "role": "interconnect"
    },
    {
      "node": {
        "id": "04_knowledge_base/Groq LPU",
        "label": "LPU"
      },
      "role": "managed_device"
    }
  ],
  "qualifiers": {
    "condition_text": "SemiAnalysis 認為此連線可能用於管理 control flow 與 timing",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "BACKPLANE_CONTROL_AND_TIMING_CONNECTIVITY"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
controller	FPGA	FPGA
interconnect	backplane	Backplane
managed_device	LPU	04_knowledge_base/Groq LPU

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。