SA260324R-0089_r1

SA260324R-0089

① SA Source

• Source: 開啟完整 SA 文章
• Section: SRAM and Memory Hierarchy
• Line hint: 91

Context Before

Since Nvidia has taken over, the next generation LP40 will be fabricated on TSMC N3P and use CoWoS-R, and Nvidia will contribute more of their own IP such as supporting the NVLink protocol rather than Groq’s C2C. This will be the first LPU to be extremely co-designed alongside the Feynman platform. Groq’s original plans for LPU Gen 4 was also with TSMC and Alchip as the back-end design partner. Alchip’s involvement is now redundant with Nvidia able to perform backend design on their own.

Evidence

One of the technical innovations planned is hybrid bonded DRAM to extend on-chip memory with only a slight decrease in latency and bandwidth vs SRAM, but much higher performance compared to DRAM.

Context After

SK Hynix was tapped as the supplier of the DRAM to be used for the 3D stacking. All of this and more was detailed long ago in the Accelerator model. ↗

② Atomic Claim

規劃中的一項技術創新是採用 hybrid-bonded DRAM 擴充 on-chip memory；相較 SRAM，其延遲與頻寬只略為下降，但相較一般 DRAM 具更高效能。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "comparison_expression": "hybrid-bonded DRAM 用於擴充 on-chip memory；相較 SRAM 僅略降延遲與頻寬，但相較一般 DRAM 具更高效能。",
  "entities": [
    {
      "id": "04_knowledge_base/DRAM",
      "label": "DRAM"
    },
    {
      "id": "04_knowledge_base/SRAM",
      "label": "SRAM"
    }
  ],
  "frame_type": "COMPARISON",
  "metric": "LATENCY_AND_BANDWIDTH",
  "operator": "TRADEOFF",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	DRAM	DRAM
entity	SRAM	SRAM

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。