SA260324R-0086_r1

SA260324R-0086

① SA Source

• Source: 開啟完整 SA 文章
• Section: SRAM and Memory Hierarchy
• Line hint: 89

Context Before

Since Nvidia has taken over, the next generation LP40 will be fabricated on TSMC N3P and use CoWoS-R, and Nvidia will contribute more of their own IP such as supporting the NVLink protocol rather than Groq’s C2C. This will be the first LPU to be extremely co-designed alongside the Feynman platform.

Evidence

Groq’s original plans for LPU Gen 4 was also with TSMC

Context After

and Alchip as the back-end design partner. Alchip’s involvement is now redundant with Nvidia able to perform backend design on their own.

② Atomic Claim

Groq 原先對 LPU Gen 4 的規劃，同樣是與 TSMC 合作。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "02_companies/Groq",
        "label": "Groq"
      },
      "role": "planner"
    },
    {
      "node": {
        "id": "04_knowledge_base/Groq LPU",
        "label": "LPU Gen 4"
      },
      "role": "product"
    },
    {
      "node": {
        "id": "02_companies/2330 台積電",
        "label": "TSMC"
      },
      "role": "foundry_partner"
    }
  ],
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "4"
    ],
    "temporal_mentions": [
      "原先"
    ]
  },
  "relation_type": "ORIGINAL_GEN4_PLAN"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
planner	Groq	Groq
product	LPU Gen 4	04_knowledge_base/Groq LPU
foundry_partner	TSMC	02_companies/2330 台積電

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。