SA260324R-0085_r1

SA260324R-0085

① SA Source

• Source: 開啟完整 SA 文章
• Section: SRAM and Memory Hierarchy
• Line hint: 89

Context Before

Since Nvidia has taken over, the next generation LP40 will be fabricated on TSMC N3P and use CoWoS-R, and Nvidia will contribute more of their own IP such as supporting the NVLink protocol rather than Groq’s C2C.

Evidence

This will be the first LPU to be extremely co-designed alongside the Feynman platform.

Context After

Groq’s original plans for LPU Gen 4 was also with TSMC and Alchip as the back-end design partner. Alchip’s involvement is now redundant with Nvidia able to perform backend design on their own.

② Atomic Claim

這將是第一個與 Feynman 平台進行高度共同設計的 LPU。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "additional_nodes": [],
  "frame_type": "RELATION",
  "object": {
    "id": "04_knowledge_base/NVIDIA Feynman Architecture",
    "label": "Feynman"
  },
  "predicate": "FIRST_EXTREMELY_CO_DESIGNED_ALONGSIDE",
  "qualifiers": {
    "condition_text": "first LPU of this kind",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "subject": {
    "id": "04_knowledge_base/Groq LPU",
    "label": "LPU"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
subject	LPU	04_knowledge_base/Groq LPU
object	Feynman	04_knowledge_base/NVIDIA Feynman Architecture

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。