SA260324R-0084
① SA Source
- Source: 開啟完整 SA 文章
- Section:
SRAM and Memory Hierarchy - Line hint:
89
Context Before
Since Nvidia has taken over, the next generation LP40 will be fabricated on TSMC N3P and
Evidence
Context After
This will be the first LPU to be extremely co-designed alongside the Feynman platform. Groq’s original plans for LPU Gen 4 was also with TSMC and Alchip as the back-end design partner. Alchip’s involvement is now redundant with Nvidia able to perform backend design on their own.
② Atomic Claim
它將使用 CoWoS-R;Nvidia 也會投入更多自有 IP,例如支援 NVLink protocol,而不是沿用 Groq 的 C2C。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "02_companies/NVDA",
"label": "Nvidia"
},
"role": "company"
},
{
"node": {
"id": "04_knowledge_base/CoWoS",
"label": "CoWoS-R"
},
"role": "packaging"
},
{
"node": {
"id": "04_knowledge_base/NVLink",
"label": "NVLink"
},
"role": "new_protocol"
},
{
"node": {
"id": "02_companies/Groq",
"label": "Groq"
},
"role": "prior_company"
},
{
"node": {
"id": "04_knowledge_base/Chip-to-Chip Interconnect",
"label": "C2C"
},
"role": "prior_protocol"
}
],
"qualifiers": {
"condition_text": "it 指前一 claim 的 LP40;LP40 本身未建 canonical node",
"numeric_mentions": [],
"temporal_mentions": []
},
"relation_type": "NEXT_GEN_LPU_PACKAGING_AND_INTERCONNECT_IP_SHIFT"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| company | Nvidia | NVDA |
| packaging | CoWoS-R | CoWoS |
| new_protocol | NVLink | NVLink |
| prior_company | Groq | Groq |
| prior_protocol | C2C | 04_knowledge_base/Chip-to-Chip Interconnect |
⑤ Human Review
請在 Properties 逐項確認:
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。