SA260324R-0083_r1

SA260324R-0083

① SA Source

• Source: 開啟完整 SA 文章
• Section: SRAM and Memory Hierarchy
• Line hint: 89

Context Before

One of the benefits of relying on SF4 is that it isn’t constrained like TSMC’s N3, which is putting a cap on accelerator production and is a key reason why the industry remains compute constrained. This is in addition to not having HBM which is also constrained. This allows Nvidia to ramp production of the LPU without sacrificing or eating into their valuable TSMC allocation or HBM allocations, representing true incremental revenue and capacity that noone else can access.

Evidence

Since Nvidia has taken over, the next generation LP40 will be fabricated on TSMC N3P

Context After

and use CoWoS-R, and Nvidia will contribute more of their own IP such as supporting the NVLink protocol rather than Groq’s C2C. This will be the first LPU to be extremely co-designed alongside the Feynman platform. Groq’s original plans for LPU Gen 4 was also with TSMC and Alchip as the back-end design partner. Alchip’s involvement is now redundant with Nvidia able to perform backend design on their own.

② Atomic Claim

自 Nvidia 接手後，下一代 LP40 將採用 TSMC N3P 製程。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "frame_type": "CLAIM_ONLY",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "40",
      "3"
    ],
    "temporal_mentions": [
      "自 Nvidia 接手後"
    ]
  },
  "reason": "LP40 在本 claim 沒有可安全使用的 canonical node；因此不虛構產品 entity，保留 Nvidia、TSMC N3P 的原文關係於 statement。",
  "statement": "Nvidia 接手後，下一代 LP40 將採用 TSMC N3P 製程。"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
—	—	—

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。