SA260324R-0076_r1

SA260324R-0076

① SA Source

• Source: 開啟完整 SA 文章
• Section: SRAM and Memory Hierarchy
• Line hint: 85

Context Before

LPU 3’s near reticle size die layout is very similar to LPU 1. a significant amount of area taken is up by the 500MB of on-chip SRAM, with a very small amount of area dedicated to MatMul cores that offer 1.2 PFLOPs of FP8 compute – a fraction of compute compared to Nvidia GPUs. This compares to LPU 1 with 230MB of SRAM and 750 TFLOPs of INT8, with

Evidence

the performance increase mostly driven by node migration from GF16 to SF4.

Context After

As a single monolithic die, advanced packaging isn’t required.

② Atomic Claim

效能提升主要來自製程節點從 GF16 遷移至 SF4。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "frame_type": "CLAIM_ONLY",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "16",
      "4"
    ],
    "temporal_mentions": []
  },
  "reason": "GF16 在本 claim 中不是 canonical wikilink；為避免自行建立 GF16 node，保留完整製程遷移敘述為 claim-only。",
  "statement": "效能提升主要由製程從 GF16 遷移至 SF4 所驅動。"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
—	—	—

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。