SA260324R-0073

① SA Source

Context Before

It will incorporate NVFP4 number format but given Nvidia is prioritizing time to market we don’t expect any other drastic design changes.

Evidence

LPU 3’s near reticle size die layout is very similar to LPU 1. a significant amount of area taken is up by the 500MB of on-chip SRAM

Context After

, with a very small amount of area dedicated to MatMul cores that offer 1.2 PFLOPs of FP8 compute – a fraction of compute compared to Nvidia GPUs. This compares to LPU 1 with 230MB of SRAM and 750 TFLOPs of INT8, with the performance increase mostly driven by node migration from GF16 to SF4. As a single monolithic die, advanced packaging isn’t required.

② Atomic Claim

LPU 3 接近 reticle size 的 die layout 與 LPU 1 非常相似;其中相當大的 die area 被 500MB on-chip SRAM 占據。

  • Epistemic Mode: ASSERTED
  • Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "DIE_LAYOUT_AND_ON_CHIP_SRAM",
  "context_nodes": [
    {
      "id": "04_knowledge_base/Reticle",
      "label": "reticle"
    },
    {
      "id": "04_knowledge_base/SRAM",
      "label": "SRAM"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/Groq LPU",
    "label": "LPU 3"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "3",
      "1",
      "500MB"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "3",
      "1",
      "500MB"
    ],
    "value_text": "near-reticle-size die layout 與 LPU 1 很相似,且大量面積由 500MB on-chip SRAM 占據"
  }
}

④ Canonical Entity Mapping

RoleSurface LabelCanonical Target
entityLPU 304_knowledge_base/Groq LPU
context_nodereticleReticle
context_nodeSRAMSRAM

⑤ Human Review

請在 Properties 逐項確認:

  • 原文 → Atomic Claim 是否忠實
  • Atomic Claim → Semantic Frame 是否忠實
  • Canonical Entity mapping 是否正確
  • Epistemic mode 是否保留原文語氣
  • 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。