SA260324R-0072
① SA Source
- Source: 開啟完整 SA 文章
- Section:
SRAM and Memory Hierarchy - Line hint:
79
Context Before
It will incorporate NVFP4 number format but
Evidence
given Nvidia is prioritizing time to market we don’t expect any other drastic design changes.
Context After
LPU 3’s near reticle size die layout is very similar to LPU 1. a significant amount of area taken is up by the 500MB of on-chip SRAM, with a very small amount of area dedicated to MatMul cores that offer 1.2 PFLOPs of FP8 compute – a fraction of compute compared to Nvidia GPUs. This compares to LPU 1 with 230MB of SRAM and 750 TFLOPs of INT8, with the performance increase mostly driven by node migration from GF16 to SF4. As a single monolithic die, advanced packaging isn’t required.
② Atomic Claim
考量 Nvidia 正優先追求 time to market，我們不預期還會有其他大幅度的設計變更。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"frame_type": "CLAIM_ONLY",
"qualifiers": {
"condition_text": "given Nvidia is prioritizing time to market",
"numeric_mentions": [],
"temporal_mentions": []
},
"reason": "原文是作者基於 Nvidia time-to-market 優先順序提出的預期，不應提升為已發生的設計事實。",
"statement": "考量 Nvidia 正優先追求 time to market，我們不預期還會有其他大幅度的設計變更。"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| — | — | — |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。