SA260324R-0071_r1

SA260324R-0071

① SA Source

• Source: 開啟完整 SA 文章
• Section: SRAM and Memory Hierarchy
• Line hint: 79

Context Before

This brings us to the Groq 3 LPU or LP30, with LPU gen 2 being skipped over. This chip has no Nvidia design involvement. The SerDes issues affecting v2 appear to be fixed. Behind the paywall, we will reveal the SerDes IP vendor which may come as a surprise. Nvidia also announced an LP35 which is a minor refresh of the LP30 which will remain on SF4 and will require a new tapeout.

Evidence

It will incorporate NVFP4 number format

Context After

but given Nvidia is prioritizing time to market we don’t expect any other drastic design changes.

② Atomic Claim

LP35 將支援 NVFP4 數值格式。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "SUPPORT_STATUS",
  "context_nodes": [],
  "entity": {
    "id": "04_knowledge_base/NVFP4",
    "label": "NVFP4"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [],
    "value_text": "LP35 將支援 NVFP4 數值格式。"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	NVFP4	NVFP4

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。